1Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic/simout
2Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic/simerr
3gem5 Simulator System. http://gem5.org
4gem5 is copyrighted software; use the --copyright option for details.
5
6gem5 compiled Nov 30 2016 14:33:35
7gem5 started Nov 30 2016 16:18:29
8gem5 executing on zizzer, pid 34062
9command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-atomic
10
11Global frequency set at 1000000000000 ticks per second
12info: Entering event queue @ 0. Starting simulation...
13info: Increasing stack size by one page.
14lr.w/sc.w: PASS
15sc.w, no preceding lr.d: PASS
16amoswap.w: PASS
17amoswap.w, sign extend: PASS
18amoswap.w, truncate: PASS
19amoadd.w: PASS
20amoadd.w, truncate/overflow: PASS
21amoadd.w, sign extend: PASS

--- 19 unchanged lines hidden (view full) ---

41amoxor.d (1): PASS
42amoxor.d (0): PASS
43amoand.d: PASS
44amoor.d: PASS
45amomin.d: PASS
46amomax.d: PASS
47amominu.d: PASS
48amomaxu.d: PASS
49Exiting @ tick 57010500 because target called exit()