| stats.txt (11731:c473ca7cc650) | stats.txt (11860:67dee11badea) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000167 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000167 # Number of seconds simulated |
| 4sim_ticks 167328500 # Number of ticks simulated 5final_tick 167328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 167318000 # Number of ticks simulated 5final_tick 167318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 54302 # Simulator instruction rate (inst/s) 8host_op_rate 54316 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 79708249 # Simulator tick rate (ticks/s) 10host_mem_usage 244184 # Number of bytes of host memory used 11host_seconds 2.10 # Real time elapsed on the host | 7host_inst_rate 259842 # Simulator instruction rate (inst/s) 8host_op_rate 259907 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 381385356 # Simulator tick rate (ticks/s) 10host_mem_usage 261864 # Number of bytes of host memory used 11host_seconds 0.44 # Real time elapsed on the host |
| 12sim_insts 113991 # Number of instructions simulated 13sim_ops 114022 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 113991 # Number of instructions simulated 13sim_ops 114022 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 52672 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 17088 # Number of bytes read from this memory 19system.physmem.bytes_read::total 69760 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 52672 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 52672 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 823 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 267 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 1090 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 52672 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 17088 # Number of bytes read from this memory 19system.physmem.bytes_read::total 69760 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 52672 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 52672 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 823 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 267 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 1090 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 314782001 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 102122472 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 416904472 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 314782001 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 314782001 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 314782001 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 102122472 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 416904472 # Total bandwidth to/from this memory (bytes/s) | 25system.physmem.bw_read::cpu.inst 314801755 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 102128880 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 416930635 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 314801755 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 314801755 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 314801755 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 102128880 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 416930635 # Total bandwidth to/from this memory (bytes/s) |
| 33system.physmem.readReqs 1090 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 1090 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 69760 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 69760 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 33system.physmem.readReqs 1090 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 1090 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 69760 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 69760 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 166995000 # Total gap between requests | 79system.physmem.totGap 166987000 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 1090 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 108 unchanged lines hidden (view full) --- 196system.physmem.bytesPerActivate::256-383 39 18.84% 68.12% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 16 7.73% 75.85% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 14 6.76% 82.61% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 7 3.38% 85.99% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 10 4.83% 90.82% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 1 0.48% 91.30% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 18 8.70% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 207 # Bytes accessed per row activation | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 1090 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 108 unchanged lines hidden (view full) --- 196system.physmem.bytesPerActivate::256-383 39 18.84% 68.12% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 16 7.73% 75.85% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 14 6.76% 82.61% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 7 3.38% 85.99% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 10 4.83% 90.82% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 1 0.48% 91.30% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 18 8.70% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 207 # Bytes accessed per row activation |
| 204system.physmem.totQLat 15434500 # Total ticks spent queuing 205system.physmem.totMemAccLat 35872000 # Total ticks spent from burst creation until serviced by the DRAM | 204system.physmem.totQLat 15449500 # Total ticks spent queuing 205system.physmem.totMemAccLat 35887000 # Total ticks spent from burst creation until serviced by the DRAM |
| 206system.physmem.totBusLat 5450000 # Total ticks spent in databus transfers | 206system.physmem.totBusLat 5450000 # Total ticks spent in databus transfers |
| 207system.physmem.avgQLat 14160.09 # Average queueing delay per DRAM burst | 207system.physmem.avgQLat 14173.85 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 32910.09 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 416.90 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgMemAccLat 32923.85 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 416.93 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 416.90 # Average system read bandwidth in MiByte/s | 212system.physmem.avgRdBWSys 416.93 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 3.26 # Data bus utilization in percentage 216system.physmem.busUtilRead 3.26 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 874 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 3.26 # Data bus utilization in percentage 216system.physmem.busUtilRead 3.26 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 874 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 153206.42 # Average gap between requests | 224system.physmem.avgGap 153199.08 # Average gap between requests |
| 225system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 3619980 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) | 225system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 3619980 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) |
| 231system.physmem_0.actBackEnergy 9305250 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 493440 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 55143510 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 7150560 # Energy for precharge power-down per rank (pJ) | 231system.physmem_0.actBackEnergy 9302400 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 492960 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 55152630 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 7141920 # Energy for precharge power-down per rank (pJ) |
| 235system.physmem_0.selfRefreshEnergy 2565480 # Energy for self refresh per rank (pJ) | 235system.physmem_0.selfRefreshEnergy 2565480 # Energy for self refresh per rank (pJ) |
| 236system.physmem_0.totalEnergy 92951370 # Total energy per rank (pJ) 237system.physmem_0.averagePower 555.501490 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 145131750 # Total Idle time Per DRAM Rank | 236system.physmem_0.totalEnergy 92948520 # Total energy per rank (pJ) 237system.physmem_0.averagePower 555.517657 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 145123750 # Total Idle time Per DRAM Rank |
| 239system.physmem_0.memoryStateTime::IDLE 654000 # Time in different power states 240system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 6087000 # Time in different power states | 239system.physmem_0.memoryStateTime::IDLE 654000 # Time in different power states 240system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 6087000 # Time in different power states |
| 242system.physmem_0.memoryStateTime::PRE_PDN 18616750 # Time in different power states | 242system.physmem_0.memoryStateTime::PRE_PDN 18593750 # Time in different power states |
| 243system.physmem_0.memoryStateTime::ACT 15316500 # Time in different power states | 243system.physmem_0.memoryStateTime::ACT 15316500 # Time in different power states |
| 244system.physmem_0.memoryStateTime::ACT_PDN 120922250 # Time in different power states | 244system.physmem_0.memoryStateTime::ACT_PDN 120934750 # Time in different power states |
| 245system.physmem_1.actEnergy 778260 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 398475 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 4162620 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ) | 245system.physmem_1.actEnergy 778260 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 398475 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 4162620 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ) |
| 250system.physmem_1.actBackEnergy 9798300 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 485280 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 44769510 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 12438720 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 4465980 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 90204585 # Total energy per rank (pJ) 256system.physmem_1.averagePower 539.085991 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 144266000 # Total Idle time Per DRAM Rank | 250system.physmem_1.actBackEnergy 9796590 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 484800 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 44771220 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 12438240 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 4464180 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 90201825 # Total energy per rank (pJ) 256system.physmem_1.averagePower 539.101715 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 144258000 # Total Idle time Per DRAM Rank |
| 258system.physmem_1.memoryStateTime::IDLE 729500 # Time in different power states 259system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states | 258system.physmem_1.memoryStateTime::IDLE 729500 # Time in different power states 259system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states |
| 260system.physmem_1.memoryStateTime::SREF 14006250 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 32390000 # Time in different power states | 260system.physmem_1.memoryStateTime::SREF 13998250 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 32388000 # Time in different power states |
| 262system.physmem_1.memoryStateTime::ACT 16564250 # Time in different power states | 262system.physmem_1.memoryStateTime::ACT 16564250 # Time in different power states |
| 263system.physmem_1.memoryStateTime::ACT_PDN 98166500 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 31621 # Number of BP lookups 266system.cpu.branchPred.condPredicted 20020 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 2186 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 28229 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 15507 # Number of BTB hits | 263system.physmem_1.memoryStateTime::ACT_PDN 98166000 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 31578 # Number of BP lookups 266system.cpu.branchPred.condPredicted 20002 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 2179 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 27728 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 15512 # Number of BTB hits |
| 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 271system.cpu.branchPred.BTBHitPct 54.932870 # BTB Hit Percentage | 271system.cpu.branchPred.BTBHitPct 55.943451 # BTB Hit Percentage |
| 272system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. | 272system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. |
| 274system.cpu.branchPred.indirectLookups 5663 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 3671 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 1992 # Number of indirect misses. | 274system.cpu.branchPred.indirectLookups 5649 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 3670 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 1979 # Number of indirect misses. |
| 277system.cpu.branchPredindirectMispredicted 1067 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.read_hits 0 # DTB read hits 280system.cpu.dtb.read_misses 0 # DTB read misses 281system.cpu.dtb.read_accesses 0 # DTB read accesses 282system.cpu.dtb.write_hits 0 # DTB write hits 283system.cpu.dtb.write_misses 0 # DTB write misses 284system.cpu.dtb.write_accesses 0 # DTB write accesses --- 5 unchanged lines hidden (view full) --- 290system.cpu.itb.read_accesses 0 # DTB read accesses 291system.cpu.itb.write_hits 0 # DTB write hits 292system.cpu.itb.write_misses 0 # DTB write misses 293system.cpu.itb.write_accesses 0 # DTB write accesses 294system.cpu.itb.hits 0 # DTB hits 295system.cpu.itb.misses 0 # DTB misses 296system.cpu.itb.accesses 0 # DTB accesses 297system.cpu.workload.num_syscalls 43 # Number of system calls | 277system.cpu.branchPredindirectMispredicted 1067 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.read_hits 0 # DTB read hits 280system.cpu.dtb.read_misses 0 # DTB read misses 281system.cpu.dtb.read_accesses 0 # DTB read accesses 282system.cpu.dtb.write_hits 0 # DTB write hits 283system.cpu.dtb.write_misses 0 # DTB write misses 284system.cpu.dtb.write_accesses 0 # DTB write accesses --- 5 unchanged lines hidden (view full) --- 290system.cpu.itb.read_accesses 0 # DTB read accesses 291system.cpu.itb.write_hits 0 # DTB write hits 292system.cpu.itb.write_misses 0 # DTB write misses 293system.cpu.itb.write_accesses 0 # DTB write accesses 294system.cpu.itb.hits 0 # DTB hits 295system.cpu.itb.misses 0 # DTB misses 296system.cpu.itb.accesses 0 # DTB accesses 297system.cpu.workload.num_syscalls 43 # Number of system calls |
| 298system.cpu.pwrStateResidencyTicks::ON 167328500 # Cumulative time (in ticks) in various power states 299system.cpu.numCycles 334657 # number of cpu cycles simulated | 298system.cpu.pwrStateResidencyTicks::ON 167318000 # Cumulative time (in ticks) in various power states 299system.cpu.numCycles 334636 # number of cpu cycles simulated |
| 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 302system.cpu.committedInsts 113991 # Number of instructions committed 303system.cpu.committedOps 114022 # Number of ops (including micro ops) committed | 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 302system.cpu.committedInsts 113991 # Number of instructions committed 303system.cpu.committedOps 114022 # Number of ops (including micro ops) committed |
| 304system.cpu.discardedOps 5904 # Number of ops (including micro ops) which were discarded before commit | 304system.cpu.discardedOps 5891 # Number of ops (including micro ops) which were discarded before commit |
| 305system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 305system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 306system.cpu.cpi 2.935819 # CPI: cycles per instruction 307system.cpu.ipc 0.340620 # IPC: instructions per cycle | 306system.cpu.cpi 2.935635 # CPI: cycles per instruction 307system.cpu.ipc 0.340642 # IPC: instructions per cycle |
| 308system.cpu.op_class_0::No_OpClass 43 0.04% 0.04% # Class of committed instruction 309system.cpu.op_class_0::IntAlu 70180 61.55% 61.59% # Class of committed instruction 310system.cpu.op_class_0::IntMult 105 0.09% 61.68% # Class of committed instruction 311system.cpu.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction 312system.cpu.op_class_0::FloatAdd 0 0.00% 61.68% # Class of committed instruction 313system.cpu.op_class_0::FloatCmp 0 0.00% 61.68% # Class of committed instruction 314system.cpu.op_class_0::FloatCvt 0 0.00% 61.68% # Class of committed instruction 315system.cpu.op_class_0::FloatMult 0 0.00% 61.68% # Class of committed instruction --- 23 unchanged lines hidden (view full) --- 339system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.68% # Class of committed instruction 340system.cpu.op_class_0::MemRead 23779 20.85% 82.53% # Class of committed instruction 341system.cpu.op_class_0::MemWrite 19915 17.47% 100.00% # Class of committed instruction 342system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 343system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction 344system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 345system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 346system.cpu.op_class_0::total 114022 # Class of committed instruction | 308system.cpu.op_class_0::No_OpClass 43 0.04% 0.04% # Class of committed instruction 309system.cpu.op_class_0::IntAlu 70180 61.55% 61.59% # Class of committed instruction 310system.cpu.op_class_0::IntMult 105 0.09% 61.68% # Class of committed instruction 311system.cpu.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction 312system.cpu.op_class_0::FloatAdd 0 0.00% 61.68% # Class of committed instruction 313system.cpu.op_class_0::FloatCmp 0 0.00% 61.68% # Class of committed instruction 314system.cpu.op_class_0::FloatCvt 0 0.00% 61.68% # Class of committed instruction 315system.cpu.op_class_0::FloatMult 0 0.00% 61.68% # Class of committed instruction --- 23 unchanged lines hidden (view full) --- 339system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.68% # Class of committed instruction 340system.cpu.op_class_0::MemRead 23779 20.85% 82.53% # Class of committed instruction 341system.cpu.op_class_0::MemWrite 19915 17.47% 100.00% # Class of committed instruction 342system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 343system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction 344system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 345system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 346system.cpu.op_class_0::total 114022 # Class of committed instruction |
| 347system.cpu.tickCycles 171660 # Number of cycles that the object actually ticked 348system.cpu.idleCycles 162997 # Total number of cycles that the object has spent stopped 349system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states | 347system.cpu.tickCycles 171594 # Number of cycles that the object actually ticked 348system.cpu.idleCycles 163042 # Total number of cycles that the object has spent stopped 349system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states |
| 350system.cpu.dcache.tags.replacements 0 # number of replacements | 350system.cpu.dcache.tags.replacements 0 # number of replacements |
| 351system.cpu.dcache.tags.tagsinuse 215.204481 # Cycle average of tags in use 352system.cpu.dcache.tags.total_refs 44066 # Total number of references to valid blocks. | 351system.cpu.dcache.tags.tagsinuse 215.201598 # Cycle average of tags in use 352system.cpu.dcache.tags.total_refs 44063 # Total number of references to valid blocks. |
| 353system.cpu.dcache.tags.sampled_refs 268 # Sample count of references to valid blocks. | 353system.cpu.dcache.tags.sampled_refs 268 # Sample count of references to valid blocks. |
| 354system.cpu.dcache.tags.avg_refs 164.425373 # Average number of references to valid blocks. | 354system.cpu.dcache.tags.avg_refs 164.414179 # Average number of references to valid blocks. |
| 355system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 355system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 356system.cpu.dcache.tags.occ_blocks::cpu.data 215.204481 # Average occupied blocks per requestor 357system.cpu.dcache.tags.occ_percent::cpu.data 0.052540 # Average percentage of cache occupancy 358system.cpu.dcache.tags.occ_percent::total 0.052540 # Average percentage of cache occupancy | 356system.cpu.dcache.tags.occ_blocks::cpu.data 215.201598 # Average occupied blocks per requestor 357system.cpu.dcache.tags.occ_percent::cpu.data 0.052539 # Average percentage of cache occupancy 358system.cpu.dcache.tags.occ_percent::total 0.052539 # Average percentage of cache occupancy |
| 359system.cpu.dcache.tags.occ_task_id_blocks::1024 268 # Occupied blocks per task id 360system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 361system.cpu.dcache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id 362system.cpu.dcache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id 363system.cpu.dcache.tags.occ_task_id_percent::1024 0.065430 # Percentage of cache occupancy per task id | 359system.cpu.dcache.tags.occ_task_id_blocks::1024 268 # Occupied blocks per task id 360system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 361system.cpu.dcache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id 362system.cpu.dcache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id 363system.cpu.dcache.tags.occ_task_id_percent::1024 0.065430 # Percentage of cache occupancy per task id |
| 364system.cpu.dcache.tags.tag_accesses 89318 # Number of tag accesses 365system.cpu.dcache.tags.data_accesses 89318 # Number of data accesses 366system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states 367system.cpu.dcache.ReadReq_hits::cpu.data 24534 # number of ReadReq hits 368system.cpu.dcache.ReadReq_hits::total 24534 # number of ReadReq hits | 364system.cpu.dcache.tags.tag_accesses 89312 # Number of tag accesses 365system.cpu.dcache.tags.data_accesses 89312 # Number of data accesses 366system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states 367system.cpu.dcache.ReadReq_hits::cpu.data 24531 # number of ReadReq hits 368system.cpu.dcache.ReadReq_hits::total 24531 # number of ReadReq hits |
| 369system.cpu.dcache.WriteReq_hits::cpu.data 19526 # number of WriteReq hits 370system.cpu.dcache.WriteReq_hits::total 19526 # number of WriteReq hits 371system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits 372system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits 373system.cpu.dcache.StoreCondReq_hits::cpu.data 4 # number of StoreCondReq hits 374system.cpu.dcache.StoreCondReq_hits::total 4 # number of StoreCondReq hits | 369system.cpu.dcache.WriteReq_hits::cpu.data 19526 # number of WriteReq hits 370system.cpu.dcache.WriteReq_hits::total 19526 # number of WriteReq hits 371system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits 372system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits 373system.cpu.dcache.StoreCondReq_hits::cpu.data 4 # number of StoreCondReq hits 374system.cpu.dcache.StoreCondReq_hits::total 4 # number of StoreCondReq hits |
| 375system.cpu.dcache.demand_hits::cpu.data 44060 # number of demand (read+write) hits 376system.cpu.dcache.demand_hits::total 44060 # number of demand (read+write) hits 377system.cpu.dcache.overall_hits::cpu.data 44060 # number of overall hits 378system.cpu.dcache.overall_hits::total 44060 # number of overall hits | 375system.cpu.dcache.demand_hits::cpu.data 44057 # number of demand (read+write) hits 376system.cpu.dcache.demand_hits::total 44057 # number of demand (read+write) hits 377system.cpu.dcache.overall_hits::cpu.data 44057 # number of overall hits 378system.cpu.dcache.overall_hits::total 44057 # number of overall hits |
| 379system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses 380system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses 381system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses 382system.cpu.dcache.WriteReq_misses::total 384 # number of WriteReq misses 383system.cpu.dcache.demand_misses::cpu.data 459 # number of demand (read+write) misses 384system.cpu.dcache.demand_misses::total 459 # number of demand (read+write) misses 385system.cpu.dcache.overall_misses::cpu.data 459 # number of overall misses 386system.cpu.dcache.overall_misses::total 459 # number of overall misses | 379system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses 380system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses 381system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses 382system.cpu.dcache.WriteReq_misses::total 384 # number of WriteReq misses 383system.cpu.dcache.demand_misses::cpu.data 459 # number of demand (read+write) misses 384system.cpu.dcache.demand_misses::total 459 # number of demand (read+write) misses 385system.cpu.dcache.overall_misses::cpu.data 459 # number of overall misses 386system.cpu.dcache.overall_misses::total 459 # number of overall misses |
| 387system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632000 # number of ReadReq miss cycles 388system.cpu.dcache.ReadReq_miss_latency::total 8632000 # number of ReadReq miss cycles | 387system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632500 # number of ReadReq miss cycles 388system.cpu.dcache.ReadReq_miss_latency::total 8632500 # number of ReadReq miss cycles |
| 389system.cpu.dcache.WriteReq_miss_latency::cpu.data 30737000 # number of WriteReq miss cycles 390system.cpu.dcache.WriteReq_miss_latency::total 30737000 # number of WriteReq miss cycles | 389system.cpu.dcache.WriteReq_miss_latency::cpu.data 30737000 # number of WriteReq miss cycles 390system.cpu.dcache.WriteReq_miss_latency::total 30737000 # number of WriteReq miss cycles |
| 391system.cpu.dcache.demand_miss_latency::cpu.data 39369000 # number of demand (read+write) miss cycles 392system.cpu.dcache.demand_miss_latency::total 39369000 # number of demand (read+write) miss cycles 393system.cpu.dcache.overall_miss_latency::cpu.data 39369000 # number of overall miss cycles 394system.cpu.dcache.overall_miss_latency::total 39369000 # number of overall miss cycles 395system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses) 396system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses) | 391system.cpu.dcache.demand_miss_latency::cpu.data 39369500 # number of demand (read+write) miss cycles 392system.cpu.dcache.demand_miss_latency::total 39369500 # number of demand (read+write) miss cycles 393system.cpu.dcache.overall_miss_latency::cpu.data 39369500 # number of overall miss cycles 394system.cpu.dcache.overall_miss_latency::total 39369500 # number of overall miss cycles 395system.cpu.dcache.ReadReq_accesses::cpu.data 24606 # number of ReadReq accesses(hits+misses) 396system.cpu.dcache.ReadReq_accesses::total 24606 # number of ReadReq accesses(hits+misses) |
| 397system.cpu.dcache.WriteReq_accesses::cpu.data 19910 # number of WriteReq accesses(hits+misses) 398system.cpu.dcache.WriteReq_accesses::total 19910 # number of WriteReq accesses(hits+misses) 399system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2 # number of LoadLockedReq accesses(hits+misses) 400system.cpu.dcache.LoadLockedReq_accesses::total 2 # number of LoadLockedReq accesses(hits+misses) 401system.cpu.dcache.StoreCondReq_accesses::cpu.data 4 # number of StoreCondReq accesses(hits+misses) 402system.cpu.dcache.StoreCondReq_accesses::total 4 # number of StoreCondReq accesses(hits+misses) | 397system.cpu.dcache.WriteReq_accesses::cpu.data 19910 # number of WriteReq accesses(hits+misses) 398system.cpu.dcache.WriteReq_accesses::total 19910 # number of WriteReq accesses(hits+misses) 399system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2 # number of LoadLockedReq accesses(hits+misses) 400system.cpu.dcache.LoadLockedReq_accesses::total 2 # number of LoadLockedReq accesses(hits+misses) 401system.cpu.dcache.StoreCondReq_accesses::cpu.data 4 # number of StoreCondReq accesses(hits+misses) 402system.cpu.dcache.StoreCondReq_accesses::total 4 # number of StoreCondReq accesses(hits+misses) |
| 403system.cpu.dcache.demand_accesses::cpu.data 44519 # number of demand (read+write) accesses 404system.cpu.dcache.demand_accesses::total 44519 # number of demand (read+write) accesses 405system.cpu.dcache.overall_accesses::cpu.data 44519 # number of overall (read+write) accesses 406system.cpu.dcache.overall_accesses::total 44519 # number of overall (read+write) accesses | 403system.cpu.dcache.demand_accesses::cpu.data 44516 # number of demand (read+write) accesses 404system.cpu.dcache.demand_accesses::total 44516 # number of demand (read+write) accesses 405system.cpu.dcache.overall_accesses::cpu.data 44516 # number of overall (read+write) accesses 406system.cpu.dcache.overall_accesses::total 44516 # number of overall (read+write) accesses |
| 407system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003048 # miss rate for ReadReq accesses 408system.cpu.dcache.ReadReq_miss_rate::total 0.003048 # miss rate for ReadReq accesses 409system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019287 # miss rate for WriteReq accesses 410system.cpu.dcache.WriteReq_miss_rate::total 0.019287 # miss rate for WriteReq accesses | 407system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003048 # miss rate for ReadReq accesses 408system.cpu.dcache.ReadReq_miss_rate::total 0.003048 # miss rate for ReadReq accesses 409system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019287 # miss rate for WriteReq accesses 410system.cpu.dcache.WriteReq_miss_rate::total 0.019287 # miss rate for WriteReq accesses |
| 411system.cpu.dcache.demand_miss_rate::cpu.data 0.010310 # miss rate for demand accesses 412system.cpu.dcache.demand_miss_rate::total 0.010310 # miss rate for demand accesses 413system.cpu.dcache.overall_miss_rate::cpu.data 0.010310 # miss rate for overall accesses 414system.cpu.dcache.overall_miss_rate::total 0.010310 # miss rate for overall accesses 415system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115093.333333 # average ReadReq miss latency 416system.cpu.dcache.ReadReq_avg_miss_latency::total 115093.333333 # average ReadReq miss latency | 411system.cpu.dcache.demand_miss_rate::cpu.data 0.010311 # miss rate for demand accesses 412system.cpu.dcache.demand_miss_rate::total 0.010311 # miss rate for demand accesses 413system.cpu.dcache.overall_miss_rate::cpu.data 0.010311 # miss rate for overall accesses 414system.cpu.dcache.overall_miss_rate::total 0.010311 # miss rate for overall accesses 415system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115100 # average ReadReq miss latency 416system.cpu.dcache.ReadReq_avg_miss_latency::total 115100 # average ReadReq miss latency |
| 417system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80044.270833 # average WriteReq miss latency 418system.cpu.dcache.WriteReq_avg_miss_latency::total 80044.270833 # average WriteReq miss latency | 417system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80044.270833 # average WriteReq miss latency 418system.cpu.dcache.WriteReq_avg_miss_latency::total 80044.270833 # average WriteReq miss latency |
| 419system.cpu.dcache.demand_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency 420system.cpu.dcache.demand_avg_miss_latency::total 85771.241830 # average overall miss latency 421system.cpu.dcache.overall_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency 422system.cpu.dcache.overall_avg_miss_latency::total 85771.241830 # average overall miss latency | 419system.cpu.dcache.demand_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency 420system.cpu.dcache.demand_avg_miss_latency::total 85772.331155 # average overall miss latency 421system.cpu.dcache.overall_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency 422system.cpu.dcache.overall_avg_miss_latency::total 85772.331155 # average overall miss latency |
| 423system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 424system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 425system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 426system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 427system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 428system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 429system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 430system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits --- 6 unchanged lines hidden (view full) --- 437system.cpu.dcache.ReadReq_mshr_misses::cpu.data 69 # number of ReadReq MSHR misses 438system.cpu.dcache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses 439system.cpu.dcache.WriteReq_mshr_misses::cpu.data 199 # number of WriteReq MSHR misses 440system.cpu.dcache.WriteReq_mshr_misses::total 199 # number of WriteReq MSHR misses 441system.cpu.dcache.demand_mshr_misses::cpu.data 268 # number of demand (read+write) MSHR misses 442system.cpu.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses 443system.cpu.dcache.overall_mshr_misses::cpu.data 268 # number of overall MSHR misses 444system.cpu.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses | 423system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 424system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 425system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 426system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 427system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 428system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 429system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 430system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits --- 6 unchanged lines hidden (view full) --- 437system.cpu.dcache.ReadReq_mshr_misses::cpu.data 69 # number of ReadReq MSHR misses 438system.cpu.dcache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses 439system.cpu.dcache.WriteReq_mshr_misses::cpu.data 199 # number of WriteReq MSHR misses 440system.cpu.dcache.WriteReq_mshr_misses::total 199 # number of WriteReq MSHR misses 441system.cpu.dcache.demand_mshr_misses::cpu.data 268 # number of demand (read+write) MSHR misses 442system.cpu.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses 443system.cpu.dcache.overall_mshr_misses::cpu.data 268 # number of overall MSHR misses 444system.cpu.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses |
| 445system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963000 # number of ReadReq MSHR miss cycles 446system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963000 # number of ReadReq MSHR miss cycles | 445system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963500 # number of ReadReq MSHR miss cycles 446system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963500 # number of ReadReq MSHR miss cycles |
| 447system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15953500 # number of WriteReq MSHR miss cycles 448system.cpu.dcache.WriteReq_mshr_miss_latency::total 15953500 # number of WriteReq MSHR miss cycles | 447system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15953500 # number of WriteReq MSHR miss cycles 448system.cpu.dcache.WriteReq_mshr_miss_latency::total 15953500 # number of WriteReq MSHR miss cycles |
| 449system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23916500 # number of demand (read+write) MSHR miss cycles 450system.cpu.dcache.demand_mshr_miss_latency::total 23916500 # number of demand (read+write) MSHR miss cycles 451system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23916500 # number of overall MSHR miss cycles 452system.cpu.dcache.overall_mshr_miss_latency::total 23916500 # number of overall MSHR miss cycles | 449system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23917000 # number of demand (read+write) MSHR miss cycles 450system.cpu.dcache.demand_mshr_miss_latency::total 23917000 # number of demand (read+write) MSHR miss cycles 451system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23917000 # number of overall MSHR miss cycles 452system.cpu.dcache.overall_mshr_miss_latency::total 23917000 # number of overall MSHR miss cycles |
| 453system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002804 # mshr miss rate for ReadReq accesses 454system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002804 # mshr miss rate for ReadReq accesses 455system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009995 # mshr miss rate for WriteReq accesses 456system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009995 # mshr miss rate for WriteReq accesses 457system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for demand accesses 458system.cpu.dcache.demand_mshr_miss_rate::total 0.006020 # mshr miss rate for demand accesses 459system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for overall accesses 460system.cpu.dcache.overall_mshr_miss_rate::total 0.006020 # mshr miss rate for overall accesses | 453system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002804 # mshr miss rate for ReadReq accesses 454system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002804 # mshr miss rate for ReadReq accesses 455system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009995 # mshr miss rate for WriteReq accesses 456system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009995 # mshr miss rate for WriteReq accesses 457system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for demand accesses 458system.cpu.dcache.demand_mshr_miss_rate::total 0.006020 # mshr miss rate for demand accesses 459system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for overall accesses 460system.cpu.dcache.overall_mshr_miss_rate::total 0.006020 # mshr miss rate for overall accesses |
| 461system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115405.797101 # average ReadReq mshr miss latency 462system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115405.797101 # average ReadReq mshr miss latency | 461system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115413.043478 # average ReadReq mshr miss latency 462system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115413.043478 # average ReadReq mshr miss latency |
| 463system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80168.341709 # average WriteReq mshr miss latency 464system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80168.341709 # average WriteReq mshr miss latency | 463system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80168.341709 # average WriteReq mshr miss latency 464system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80168.341709 # average WriteReq mshr miss latency |
| 465system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency 466system.cpu.dcache.demand_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency 467system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency 468system.cpu.dcache.overall_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency 469system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states | 465system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency 466system.cpu.dcache.demand_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency 467system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency 468system.cpu.dcache.overall_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency 469system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states |
| 470system.cpu.icache.tags.replacements 18 # number of replacements | 470system.cpu.icache.tags.replacements 18 # number of replacements |
| 471system.cpu.icache.tags.tagsinuse 401.761519 # Cycle average of tags in use 472system.cpu.icache.tags.total_refs 49677 # Total number of references to valid blocks. | 471system.cpu.icache.tags.tagsinuse 401.741743 # Cycle average of tags in use 472system.cpu.icache.tags.total_refs 49660 # Total number of references to valid blocks. |
| 473system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks. | 473system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks. |
| 474system.cpu.icache.tags.avg_refs 60.360875 # Average number of references to valid blocks. | 474system.cpu.icache.tags.avg_refs 60.340219 # Average number of references to valid blocks. |
| 475system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 475system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 476system.cpu.icache.tags.occ_blocks::cpu.inst 401.761519 # Average occupied blocks per requestor 477system.cpu.icache.tags.occ_percent::cpu.inst 0.196173 # Average percentage of cache occupancy 478system.cpu.icache.tags.occ_percent::total 0.196173 # Average percentage of cache occupancy | 476system.cpu.icache.tags.occ_blocks::cpu.inst 401.741743 # Average occupied blocks per requestor 477system.cpu.icache.tags.occ_percent::cpu.inst 0.196163 # Average percentage of cache occupancy 478system.cpu.icache.tags.occ_percent::total 0.196163 # Average percentage of cache occupancy |
| 479system.cpu.icache.tags.occ_task_id_blocks::1024 805 # Occupied blocks per task id 480system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 481system.cpu.icache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id 482system.cpu.icache.tags.age_task_id_blocks_1024::2 240 # Occupied blocks per task id 483system.cpu.icache.tags.occ_task_id_percent::1024 0.393066 # Percentage of cache occupancy per task id | 479system.cpu.icache.tags.occ_task_id_blocks::1024 805 # Occupied blocks per task id 480system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 481system.cpu.icache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id 482system.cpu.icache.tags.age_task_id_blocks_1024::2 240 # Occupied blocks per task id 483system.cpu.icache.tags.occ_task_id_percent::1024 0.393066 # Percentage of cache occupancy per task id |
| 484system.cpu.icache.tags.tag_accesses 101823 # Number of tag accesses 485system.cpu.icache.tags.data_accesses 101823 # Number of data accesses 486system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states 487system.cpu.icache.ReadReq_hits::cpu.inst 49677 # number of ReadReq hits 488system.cpu.icache.ReadReq_hits::total 49677 # number of ReadReq hits 489system.cpu.icache.demand_hits::cpu.inst 49677 # number of demand (read+write) hits 490system.cpu.icache.demand_hits::total 49677 # number of demand (read+write) hits 491system.cpu.icache.overall_hits::cpu.inst 49677 # number of overall hits 492system.cpu.icache.overall_hits::total 49677 # number of overall hits | 484system.cpu.icache.tags.tag_accesses 101789 # Number of tag accesses 485system.cpu.icache.tags.data_accesses 101789 # Number of data accesses 486system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states 487system.cpu.icache.ReadReq_hits::cpu.inst 49660 # number of ReadReq hits 488system.cpu.icache.ReadReq_hits::total 49660 # number of ReadReq hits 489system.cpu.icache.demand_hits::cpu.inst 49660 # number of demand (read+write) hits 490system.cpu.icache.demand_hits::total 49660 # number of demand (read+write) hits 491system.cpu.icache.overall_hits::cpu.inst 49660 # number of overall hits 492system.cpu.icache.overall_hits::total 49660 # number of overall hits |
| 493system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses 494system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses 495system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses 496system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses 497system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses 498system.cpu.icache.overall_misses::total 823 # number of overall misses | 493system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses 494system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses 495system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses 496system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses 497system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses 498system.cpu.icache.overall_misses::total 823 # number of overall misses |
| 499system.cpu.icache.ReadReq_miss_latency::cpu.inst 69966000 # number of ReadReq miss cycles 500system.cpu.icache.ReadReq_miss_latency::total 69966000 # number of ReadReq miss cycles 501system.cpu.icache.demand_miss_latency::cpu.inst 69966000 # number of demand (read+write) miss cycles 502system.cpu.icache.demand_miss_latency::total 69966000 # number of demand (read+write) miss cycles 503system.cpu.icache.overall_miss_latency::cpu.inst 69966000 # number of overall miss cycles 504system.cpu.icache.overall_miss_latency::total 69966000 # number of overall miss cycles 505system.cpu.icache.ReadReq_accesses::cpu.inst 50500 # number of ReadReq accesses(hits+misses) 506system.cpu.icache.ReadReq_accesses::total 50500 # number of ReadReq accesses(hits+misses) 507system.cpu.icache.demand_accesses::cpu.inst 50500 # number of demand (read+write) accesses 508system.cpu.icache.demand_accesses::total 50500 # number of demand (read+write) accesses 509system.cpu.icache.overall_accesses::cpu.inst 50500 # number of overall (read+write) accesses 510system.cpu.icache.overall_accesses::total 50500 # number of overall (read+write) accesses 511system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016297 # miss rate for ReadReq accesses 512system.cpu.icache.ReadReq_miss_rate::total 0.016297 # miss rate for ReadReq accesses 513system.cpu.icache.demand_miss_rate::cpu.inst 0.016297 # miss rate for demand accesses 514system.cpu.icache.demand_miss_rate::total 0.016297 # miss rate for demand accesses 515system.cpu.icache.overall_miss_rate::cpu.inst 0.016297 # miss rate for overall accesses 516system.cpu.icache.overall_miss_rate::total 0.016297 # miss rate for overall accesses 517system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85013.365735 # average ReadReq miss latency 518system.cpu.icache.ReadReq_avg_miss_latency::total 85013.365735 # average ReadReq miss latency 519system.cpu.icache.demand_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency 520system.cpu.icache.demand_avg_miss_latency::total 85013.365735 # average overall miss latency 521system.cpu.icache.overall_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency 522system.cpu.icache.overall_avg_miss_latency::total 85013.365735 # average overall miss latency | 499system.cpu.icache.ReadReq_miss_latency::cpu.inst 69983000 # number of ReadReq miss cycles 500system.cpu.icache.ReadReq_miss_latency::total 69983000 # number of ReadReq miss cycles 501system.cpu.icache.demand_miss_latency::cpu.inst 69983000 # number of demand (read+write) miss cycles 502system.cpu.icache.demand_miss_latency::total 69983000 # number of demand (read+write) miss cycles 503system.cpu.icache.overall_miss_latency::cpu.inst 69983000 # number of overall miss cycles 504system.cpu.icache.overall_miss_latency::total 69983000 # number of overall miss cycles 505system.cpu.icache.ReadReq_accesses::cpu.inst 50483 # number of ReadReq accesses(hits+misses) 506system.cpu.icache.ReadReq_accesses::total 50483 # number of ReadReq accesses(hits+misses) 507system.cpu.icache.demand_accesses::cpu.inst 50483 # number of demand (read+write) accesses 508system.cpu.icache.demand_accesses::total 50483 # number of demand (read+write) accesses 509system.cpu.icache.overall_accesses::cpu.inst 50483 # number of overall (read+write) accesses 510system.cpu.icache.overall_accesses::total 50483 # number of overall (read+write) accesses 511system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016303 # miss rate for ReadReq accesses 512system.cpu.icache.ReadReq_miss_rate::total 0.016303 # miss rate for ReadReq accesses 513system.cpu.icache.demand_miss_rate::cpu.inst 0.016303 # miss rate for demand accesses 514system.cpu.icache.demand_miss_rate::total 0.016303 # miss rate for demand accesses 515system.cpu.icache.overall_miss_rate::cpu.inst 0.016303 # miss rate for overall accesses 516system.cpu.icache.overall_miss_rate::total 0.016303 # miss rate for overall accesses 517system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85034.021871 # average ReadReq miss latency 518system.cpu.icache.ReadReq_avg_miss_latency::total 85034.021871 # average ReadReq miss latency 519system.cpu.icache.demand_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency 520system.cpu.icache.demand_avg_miss_latency::total 85034.021871 # average overall miss latency 521system.cpu.icache.overall_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency 522system.cpu.icache.overall_avg_miss_latency::total 85034.021871 # average overall miss latency |
| 523system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 524system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 525system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 526system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 527system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 528system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 529system.cpu.icache.writebacks::writebacks 18 # number of writebacks 530system.cpu.icache.writebacks::total 18 # number of writebacks 531system.cpu.icache.ReadReq_mshr_misses::cpu.inst 823 # number of ReadReq MSHR misses 532system.cpu.icache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses 533system.cpu.icache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses 534system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses 535system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses 536system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses | 523system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 524system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 525system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 526system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 527system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 528system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 529system.cpu.icache.writebacks::writebacks 18 # number of writebacks 530system.cpu.icache.writebacks::total 18 # number of writebacks 531system.cpu.icache.ReadReq_mshr_misses::cpu.inst 823 # number of ReadReq MSHR misses 532system.cpu.icache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses 533system.cpu.icache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses 534system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses 535system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses 536system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses |
| 537system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69143000 # number of ReadReq MSHR miss cycles 538system.cpu.icache.ReadReq_mshr_miss_latency::total 69143000 # number of ReadReq MSHR miss cycles 539system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69143000 # number of demand (read+write) MSHR miss cycles 540system.cpu.icache.demand_mshr_miss_latency::total 69143000 # number of demand (read+write) MSHR miss cycles 541system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69143000 # number of overall MSHR miss cycles 542system.cpu.icache.overall_mshr_miss_latency::total 69143000 # number of overall MSHR miss cycles 543system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for ReadReq accesses 544system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016297 # mshr miss rate for ReadReq accesses 545system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for demand accesses 546system.cpu.icache.demand_mshr_miss_rate::total 0.016297 # mshr miss rate for demand accesses 547system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for overall accesses 548system.cpu.icache.overall_mshr_miss_rate::total 0.016297 # mshr miss rate for overall accesses 549system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84013.365735 # average ReadReq mshr miss latency 550system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84013.365735 # average ReadReq mshr miss latency 551system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency 552system.cpu.icache.demand_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency 553system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency 554system.cpu.icache.overall_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency 555system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states | 537system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles 538system.cpu.icache.ReadReq_mshr_miss_latency::total 69160000 # number of ReadReq MSHR miss cycles 539system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles 540system.cpu.icache.demand_mshr_miss_latency::total 69160000 # number of demand (read+write) MSHR miss cycles 541system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles 542system.cpu.icache.overall_mshr_miss_latency::total 69160000 # number of overall MSHR miss cycles 543system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for ReadReq accesses 544system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016303 # mshr miss rate for ReadReq accesses 545system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for demand accesses 546system.cpu.icache.demand_mshr_miss_rate::total 0.016303 # mshr miss rate for demand accesses 547system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for overall accesses 548system.cpu.icache.overall_mshr_miss_rate::total 0.016303 # mshr miss rate for overall accesses 549system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84034.021871 # average ReadReq mshr miss latency 550system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84034.021871 # average ReadReq mshr miss latency 551system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency 552system.cpu.icache.demand_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency 553system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency 554system.cpu.icache.overall_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency 555system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states |
| 556system.cpu.l2cache.tags.replacements 0 # number of replacements | 556system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 557system.cpu.l2cache.tags.tagsinuse 622.728504 # Cycle average of tags in use | 557system.cpu.l2cache.tags.tagsinuse 622.705265 # Cycle average of tags in use |
| 558system.cpu.l2cache.tags.total_refs 19 # Total number of references to valid blocks. 559system.cpu.l2cache.tags.sampled_refs 1090 # Sample count of references to valid blocks. 560system.cpu.l2cache.tags.avg_refs 0.017431 # Average number of references to valid blocks. 561system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 558system.cpu.l2cache.tags.total_refs 19 # Total number of references to valid blocks. 559system.cpu.l2cache.tags.sampled_refs 1090 # Sample count of references to valid blocks. 560system.cpu.l2cache.tags.avg_refs 0.017431 # Average number of references to valid blocks. 561system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 562system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.968080 # Average occupied blocks per requestor 563system.cpu.l2cache.tags.occ_blocks::cpu.data 214.760424 # Average occupied blocks per requestor | 562system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.947689 # Average occupied blocks per requestor 563system.cpu.l2cache.tags.occ_blocks::cpu.data 214.757576 # Average occupied blocks per requestor |
| 564system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012450 # Average percentage of cache occupancy 565system.cpu.l2cache.tags.occ_percent::cpu.data 0.006554 # Average percentage of cache occupancy | 564system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012450 # Average percentage of cache occupancy 565system.cpu.l2cache.tags.occ_percent::cpu.data 0.006554 # Average percentage of cache occupancy |
| 566system.cpu.l2cache.tags.occ_percent::total 0.019004 # Average percentage of cache occupancy | 566system.cpu.l2cache.tags.occ_percent::total 0.019003 # Average percentage of cache occupancy |
| 567system.cpu.l2cache.tags.occ_task_id_blocks::1024 1090 # Occupied blocks per task id 568system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 569system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id 570system.cpu.l2cache.tags.age_task_id_blocks_1024::2 454 # Occupied blocks per task id 571system.cpu.l2cache.tags.occ_task_id_percent::1024 0.033264 # Percentage of cache occupancy per task id 572system.cpu.l2cache.tags.tag_accesses 9962 # Number of tag accesses 573system.cpu.l2cache.tags.data_accesses 9962 # Number of data accesses | 567system.cpu.l2cache.tags.occ_task_id_blocks::1024 1090 # Occupied blocks per task id 568system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 569system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id 570system.cpu.l2cache.tags.age_task_id_blocks_1024::2 454 # Occupied blocks per task id 571system.cpu.l2cache.tags.occ_task_id_percent::1024 0.033264 # Percentage of cache occupancy per task id 572system.cpu.l2cache.tags.tag_accesses 9962 # Number of tag accesses 573system.cpu.l2cache.tags.data_accesses 9962 # Number of data accesses |
| 574system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states | 574system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states |
| 575system.cpu.l2cache.WritebackClean_hits::writebacks 18 # number of WritebackClean hits 576system.cpu.l2cache.WritebackClean_hits::total 18 # number of WritebackClean hits 577system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 578system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits 579system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 580system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 581system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 582system.cpu.l2cache.overall_hits::total 1 # number of overall hits --- 6 unchanged lines hidden (view full) --- 589system.cpu.l2cache.demand_misses::cpu.inst 823 # number of demand (read+write) misses 590system.cpu.l2cache.demand_misses::cpu.data 267 # number of demand (read+write) misses 591system.cpu.l2cache.demand_misses::total 1090 # number of demand (read+write) misses 592system.cpu.l2cache.overall_misses::cpu.inst 823 # number of overall misses 593system.cpu.l2cache.overall_misses::cpu.data 267 # number of overall misses 594system.cpu.l2cache.overall_misses::total 1090 # number of overall misses 595system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15654000 # number of ReadExReq miss cycles 596system.cpu.l2cache.ReadExReq_miss_latency::total 15654000 # number of ReadExReq miss cycles | 575system.cpu.l2cache.WritebackClean_hits::writebacks 18 # number of WritebackClean hits 576system.cpu.l2cache.WritebackClean_hits::total 18 # number of WritebackClean hits 577system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 578system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits 579system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 580system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 581system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 582system.cpu.l2cache.overall_hits::total 1 # number of overall hits --- 6 unchanged lines hidden (view full) --- 589system.cpu.l2cache.demand_misses::cpu.inst 823 # number of demand (read+write) misses 590system.cpu.l2cache.demand_misses::cpu.data 267 # number of demand (read+write) misses 591system.cpu.l2cache.demand_misses::total 1090 # number of demand (read+write) misses 592system.cpu.l2cache.overall_misses::cpu.inst 823 # number of overall misses 593system.cpu.l2cache.overall_misses::cpu.data 267 # number of overall misses 594system.cpu.l2cache.overall_misses::total 1090 # number of overall misses 595system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15654000 # number of ReadExReq miss cycles 596system.cpu.l2cache.ReadExReq_miss_latency::total 15654000 # number of ReadExReq miss cycles |
| 597system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67908500 # number of ReadCleanReq miss cycles 598system.cpu.l2cache.ReadCleanReq_miss_latency::total 67908500 # number of ReadCleanReq miss cycles 599system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847000 # number of ReadSharedReq miss cycles 600system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847000 # number of ReadSharedReq miss cycles 601system.cpu.l2cache.demand_miss_latency::cpu.inst 67908500 # number of demand (read+write) miss cycles 602system.cpu.l2cache.demand_miss_latency::cpu.data 23501000 # number of demand (read+write) miss cycles 603system.cpu.l2cache.demand_miss_latency::total 91409500 # number of demand (read+write) miss cycles 604system.cpu.l2cache.overall_miss_latency::cpu.inst 67908500 # number of overall miss cycles 605system.cpu.l2cache.overall_miss_latency::cpu.data 23501000 # number of overall miss cycles 606system.cpu.l2cache.overall_miss_latency::total 91409500 # number of overall miss cycles | 597system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67925500 # number of ReadCleanReq miss cycles 598system.cpu.l2cache.ReadCleanReq_miss_latency::total 67925500 # number of ReadCleanReq miss cycles 599system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847500 # number of ReadSharedReq miss cycles 600system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847500 # number of ReadSharedReq miss cycles 601system.cpu.l2cache.demand_miss_latency::cpu.inst 67925500 # number of demand (read+write) miss cycles 602system.cpu.l2cache.demand_miss_latency::cpu.data 23501500 # number of demand (read+write) miss cycles 603system.cpu.l2cache.demand_miss_latency::total 91427000 # number of demand (read+write) miss cycles 604system.cpu.l2cache.overall_miss_latency::cpu.inst 67925500 # number of overall miss cycles 605system.cpu.l2cache.overall_miss_latency::cpu.data 23501500 # number of overall miss cycles 606system.cpu.l2cache.overall_miss_latency::total 91427000 # number of overall miss cycles |
| 607system.cpu.l2cache.WritebackClean_accesses::writebacks 18 # number of WritebackClean accesses(hits+misses) 608system.cpu.l2cache.WritebackClean_accesses::total 18 # number of WritebackClean accesses(hits+misses) 609system.cpu.l2cache.ReadExReq_accesses::cpu.data 199 # number of ReadExReq accesses(hits+misses) 610system.cpu.l2cache.ReadExReq_accesses::total 199 # number of ReadExReq accesses(hits+misses) 611system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 823 # number of ReadCleanReq accesses(hits+misses) 612system.cpu.l2cache.ReadCleanReq_accesses::total 823 # number of ReadCleanReq accesses(hits+misses) 613system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 69 # number of ReadSharedReq accesses(hits+misses) 614system.cpu.l2cache.ReadSharedReq_accesses::total 69 # number of ReadSharedReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 627system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses 628system.cpu.l2cache.demand_miss_rate::cpu.data 0.996269 # miss rate for demand accesses 629system.cpu.l2cache.demand_miss_rate::total 0.999083 # miss rate for demand accesses 630system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses 631system.cpu.l2cache.overall_miss_rate::cpu.data 0.996269 # miss rate for overall accesses 632system.cpu.l2cache.overall_miss_rate::total 0.999083 # miss rate for overall accesses 633system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78663.316583 # average ReadExReq miss latency 634system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78663.316583 # average ReadExReq miss latency | 607system.cpu.l2cache.WritebackClean_accesses::writebacks 18 # number of WritebackClean accesses(hits+misses) 608system.cpu.l2cache.WritebackClean_accesses::total 18 # number of WritebackClean accesses(hits+misses) 609system.cpu.l2cache.ReadExReq_accesses::cpu.data 199 # number of ReadExReq accesses(hits+misses) 610system.cpu.l2cache.ReadExReq_accesses::total 199 # number of ReadExReq accesses(hits+misses) 611system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 823 # number of ReadCleanReq accesses(hits+misses) 612system.cpu.l2cache.ReadCleanReq_accesses::total 823 # number of ReadCleanReq accesses(hits+misses) 613system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 69 # number of ReadSharedReq accesses(hits+misses) 614system.cpu.l2cache.ReadSharedReq_accesses::total 69 # number of ReadSharedReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 627system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses 628system.cpu.l2cache.demand_miss_rate::cpu.data 0.996269 # miss rate for demand accesses 629system.cpu.l2cache.demand_miss_rate::total 0.999083 # miss rate for demand accesses 630system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses 631system.cpu.l2cache.overall_miss_rate::cpu.data 0.996269 # miss rate for overall accesses 632system.cpu.l2cache.overall_miss_rate::total 0.999083 # miss rate for overall accesses 633system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78663.316583 # average ReadExReq miss latency 634system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78663.316583 # average ReadExReq miss latency |
| 635system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82513.365735 # average ReadCleanReq miss latency 636system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82513.365735 # average ReadCleanReq miss latency 637system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115397.058824 # average ReadSharedReq miss latency 638system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115397.058824 # average ReadSharedReq miss latency 639system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency 640system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency 641system.cpu.l2cache.demand_avg_miss_latency::total 83861.926606 # average overall miss latency 642system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency 643system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency 644system.cpu.l2cache.overall_avg_miss_latency::total 83861.926606 # average overall miss latency | 635system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82534.021871 # average ReadCleanReq miss latency 636system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82534.021871 # average ReadCleanReq miss latency 637system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115404.411765 # average ReadSharedReq miss latency 638system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115404.411765 # average ReadSharedReq miss latency 639system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency 640system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency 641system.cpu.l2cache.demand_avg_miss_latency::total 83877.981651 # average overall miss latency 642system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency 643system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency 644system.cpu.l2cache.overall_avg_miss_latency::total 83877.981651 # average overall miss latency |
| 645system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 646system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 647system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 648system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 649system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 650system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 651system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 199 # number of ReadExReq MSHR misses 652system.cpu.l2cache.ReadExReq_mshr_misses::total 199 # number of ReadExReq MSHR misses --- 4 unchanged lines hidden (view full) --- 657system.cpu.l2cache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses 658system.cpu.l2cache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses 659system.cpu.l2cache.demand_mshr_misses::total 1090 # number of demand (read+write) MSHR misses 660system.cpu.l2cache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses 661system.cpu.l2cache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses 662system.cpu.l2cache.overall_mshr_misses::total 1090 # number of overall MSHR misses 663system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13664000 # number of ReadExReq MSHR miss cycles 664system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13664000 # number of ReadExReq MSHR miss cycles | 645system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 646system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 647system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 648system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 649system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 650system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 651system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 199 # number of ReadExReq MSHR misses 652system.cpu.l2cache.ReadExReq_mshr_misses::total 199 # number of ReadExReq MSHR misses --- 4 unchanged lines hidden (view full) --- 657system.cpu.l2cache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses 658system.cpu.l2cache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses 659system.cpu.l2cache.demand_mshr_misses::total 1090 # number of demand (read+write) MSHR misses 660system.cpu.l2cache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses 661system.cpu.l2cache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses 662system.cpu.l2cache.overall_mshr_misses::total 1090 # number of overall MSHR misses 663system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13664000 # number of ReadExReq MSHR miss cycles 664system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13664000 # number of ReadExReq MSHR miss cycles |
| 665system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59678500 # number of ReadCleanReq MSHR miss cycles 666system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59678500 # number of ReadCleanReq MSHR miss cycles 667system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167000 # number of ReadSharedReq MSHR miss cycles 668system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167000 # number of ReadSharedReq MSHR miss cycles 669system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59678500 # number of demand (read+write) MSHR miss cycles 670system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831000 # number of demand (read+write) MSHR miss cycles 671system.cpu.l2cache.demand_mshr_miss_latency::total 80509500 # number of demand (read+write) MSHR miss cycles 672system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59678500 # number of overall MSHR miss cycles 673system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831000 # number of overall MSHR miss cycles 674system.cpu.l2cache.overall_mshr_miss_latency::total 80509500 # number of overall MSHR miss cycles | 665system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59695500 # number of ReadCleanReq MSHR miss cycles 666system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59695500 # number of ReadCleanReq MSHR miss cycles 667system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167500 # number of ReadSharedReq MSHR miss cycles 668system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167500 # number of ReadSharedReq MSHR miss cycles 669system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59695500 # number of demand (read+write) MSHR miss cycles 670system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831500 # number of demand (read+write) MSHR miss cycles 671system.cpu.l2cache.demand_mshr_miss_latency::total 80527000 # number of demand (read+write) MSHR miss cycles 672system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59695500 # number of overall MSHR miss cycles 673system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831500 # number of overall MSHR miss cycles 674system.cpu.l2cache.overall_mshr_miss_latency::total 80527000 # number of overall MSHR miss cycles |
| 675system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 676system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 677system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses 678system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses 679system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.985507 # mshr miss rate for ReadSharedReq accesses 680system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.985507 # mshr miss rate for ReadSharedReq accesses 681system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 682system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996269 # mshr miss rate for demand accesses 683system.cpu.l2cache.demand_mshr_miss_rate::total 0.999083 # mshr miss rate for demand accesses 684system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses 685system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996269 # mshr miss rate for overall accesses 686system.cpu.l2cache.overall_mshr_miss_rate::total 0.999083 # mshr miss rate for overall accesses 687system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68663.316583 # average ReadExReq mshr miss latency 688system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68663.316583 # average ReadExReq mshr miss latency | 675system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 676system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 677system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses 678system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses 679system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.985507 # mshr miss rate for ReadSharedReq accesses 680system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.985507 # mshr miss rate for ReadSharedReq accesses 681system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 682system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996269 # mshr miss rate for demand accesses 683system.cpu.l2cache.demand_mshr_miss_rate::total 0.999083 # mshr miss rate for demand accesses 684system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses 685system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996269 # mshr miss rate for overall accesses 686system.cpu.l2cache.overall_mshr_miss_rate::total 0.999083 # mshr miss rate for overall accesses 687system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68663.316583 # average ReadExReq mshr miss latency 688system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68663.316583 # average ReadExReq mshr miss latency |
| 689system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72513.365735 # average ReadCleanReq mshr miss latency 690system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72513.365735 # average ReadCleanReq mshr miss latency 691system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105397.058824 # average ReadSharedReq mshr miss latency 692system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105397.058824 # average ReadSharedReq mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency 694system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency 695system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency 697system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency 698system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency | 689system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72534.021871 # average ReadCleanReq mshr miss latency 690system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72534.021871 # average ReadCleanReq mshr miss latency 691system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105404.411765 # average ReadSharedReq mshr miss latency 692system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105404.411765 # average ReadSharedReq mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency 694system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency 695system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency 697system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency 698system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency |
| 699system.cpu.toL2Bus.snoop_filter.tot_requests 1109 # Total number of requests made to the snoop filter. 700system.cpu.toL2Bus.snoop_filter.hit_single_requests 19 # Number of requests hitting in the snoop filter with a single holder of the requested data. 701system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 702system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 703system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 704system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 699system.cpu.toL2Bus.snoop_filter.tot_requests 1109 # Total number of requests made to the snoop filter. 700system.cpu.toL2Bus.snoop_filter.hit_single_requests 19 # Number of requests hitting in the snoop filter with a single holder of the requested data. 701system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 702system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 703system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 704system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 705system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states | 705system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states |
| 706system.cpu.toL2Bus.trans_dist::ReadResp 892 # Transaction distribution 707system.cpu.toL2Bus.trans_dist::WritebackClean 18 # Transaction distribution 708system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution 709system.cpu.toL2Bus.trans_dist::ReadExResp 199 # Transaction distribution 710system.cpu.toL2Bus.trans_dist::ReadCleanReq 823 # Transaction distribution 711system.cpu.toL2Bus.trans_dist::ReadSharedReq 69 # Transaction distribution 712system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1664 # Packet count per connected master and slave (bytes) 713system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 536 # Packet count per connected master and slave (bytes) --- 21 unchanged lines hidden (view full) --- 735system.cpu.toL2Bus.respLayer1.occupancy 402000 # Layer occupancy (ticks) 736system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 737system.membus.snoop_filter.tot_requests 1090 # Total number of requests made to the snoop filter. 738system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 739system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 740system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 741system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 742system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 706system.cpu.toL2Bus.trans_dist::ReadResp 892 # Transaction distribution 707system.cpu.toL2Bus.trans_dist::WritebackClean 18 # Transaction distribution 708system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution 709system.cpu.toL2Bus.trans_dist::ReadExResp 199 # Transaction distribution 710system.cpu.toL2Bus.trans_dist::ReadCleanReq 823 # Transaction distribution 711system.cpu.toL2Bus.trans_dist::ReadSharedReq 69 # Transaction distribution 712system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1664 # Packet count per connected master and slave (bytes) 713system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 536 # Packet count per connected master and slave (bytes) --- 21 unchanged lines hidden (view full) --- 735system.cpu.toL2Bus.respLayer1.occupancy 402000 # Layer occupancy (ticks) 736system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 737system.membus.snoop_filter.tot_requests 1090 # Total number of requests made to the snoop filter. 738system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 739system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 740system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 741system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 742system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 743system.membus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states | 743system.membus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states |
| 744system.membus.trans_dist::ReadResp 891 # Transaction distribution 745system.membus.trans_dist::ReadExReq 199 # Transaction distribution 746system.membus.trans_dist::ReadExResp 199 # Transaction distribution 747system.membus.trans_dist::ReadSharedReq 891 # Transaction distribution 748system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2180 # Packet count per connected master and slave (bytes) 749system.membus.pkt_count::total 2180 # Packet count per connected master and slave (bytes) 750system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 69760 # Cumulative packet size per connected master and slave (bytes) 751system.membus.pkt_size::total 69760 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 756system.membus.snoop_fanout::stdev 0 # Request fanout histogram 757system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 758system.membus.snoop_fanout::0 1090 100.00% 100.00% # Request fanout histogram 759system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 760system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 761system.membus.snoop_fanout::min_value 0 # Request fanout histogram 762system.membus.snoop_fanout::max_value 0 # Request fanout histogram 763system.membus.snoop_fanout::total 1090 # Request fanout histogram | 744system.membus.trans_dist::ReadResp 891 # Transaction distribution 745system.membus.trans_dist::ReadExReq 199 # Transaction distribution 746system.membus.trans_dist::ReadExResp 199 # Transaction distribution 747system.membus.trans_dist::ReadSharedReq 891 # Transaction distribution 748system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2180 # Packet count per connected master and slave (bytes) 749system.membus.pkt_count::total 2180 # Packet count per connected master and slave (bytes) 750system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 69760 # Cumulative packet size per connected master and slave (bytes) 751system.membus.pkt_size::total 69760 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 756system.membus.snoop_fanout::stdev 0 # Request fanout histogram 757system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 758system.membus.snoop_fanout::0 1090 100.00% 100.00% # Request fanout histogram 759system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 760system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 761system.membus.snoop_fanout::min_value 0 # Request fanout histogram 762system.membus.snoop_fanout::max_value 0 # Request fanout histogram 763system.membus.snoop_fanout::total 1090 # Request fanout histogram |
| 764system.membus.reqLayer0.occupancy 1226500 # Layer occupancy (ticks) | 764system.membus.reqLayer0.occupancy 1229000 # Layer occupancy (ticks) |
| 765system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) 766system.membus.respLayer1.occupancy 5789000 # Layer occupancy (ticks) 767system.membus.respLayer1.utilization 3.5 # Layer utilization (%) 768 769---------- End Simulation Statistics ---------- | 765system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) 766system.membus.respLayer1.occupancy 5789000 # Layer occupancy (ticks) 767system.membus.respLayer1.utilization 3.5 # Layer utilization (%) 768 769---------- End Simulation Statistics ---------- |