4,5c4,5
< sim_ticks 167328500 # Number of ticks simulated
< final_tick 167328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 167318000 # Number of ticks simulated
> final_tick 167318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 54302 # Simulator instruction rate (inst/s)
< host_op_rate 54316 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 79708249 # Simulator tick rate (ticks/s)
< host_mem_usage 244184 # Number of bytes of host memory used
< host_seconds 2.10 # Real time elapsed on the host
---
> host_inst_rate 259842 # Simulator instruction rate (inst/s)
> host_op_rate 259907 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 381385356 # Simulator tick rate (ticks/s)
> host_mem_usage 261864 # Number of bytes of host memory used
> host_seconds 0.44 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 314782001 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 102122472 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 416904472 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 314782001 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 314782001 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 314782001 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 102122472 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 416904472 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 314801755 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 102128880 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 416930635 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 314801755 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 314801755 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 314801755 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 102128880 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 416930635 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 166995000 # Total gap between requests
---
> system.physmem.totGap 166987000 # Total gap between requests
204,205c204,205
< system.physmem.totQLat 15434500 # Total ticks spent queuing
< system.physmem.totMemAccLat 35872000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 15449500 # Total ticks spent queuing
> system.physmem.totMemAccLat 35887000 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 14160.09 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 14173.85 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 32910.09 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 416.90 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 32923.85 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 416.93 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 416.90 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 416.93 # Average system read bandwidth in MiByte/s
224c224
< system.physmem.avgGap 153206.42 # Average gap between requests
---
> system.physmem.avgGap 153199.08 # Average gap between requests
231,234c231,234
< system.physmem_0.actBackEnergy 9305250 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 493440 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 55143510 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 7150560 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_0.actBackEnergy 9302400 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 492960 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 55152630 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 7141920 # Energy for precharge power-down per rank (pJ)
236,238c236,238
< system.physmem_0.totalEnergy 92951370 # Total energy per rank (pJ)
< system.physmem_0.averagePower 555.501490 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 145131750 # Total Idle time Per DRAM Rank
---
> system.physmem_0.totalEnergy 92948520 # Total energy per rank (pJ)
> system.physmem_0.averagePower 555.517657 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 145123750 # Total Idle time Per DRAM Rank
242c242
< system.physmem_0.memoryStateTime::PRE_PDN 18616750 # Time in different power states
---
> system.physmem_0.memoryStateTime::PRE_PDN 18593750 # Time in different power states
244c244
< system.physmem_0.memoryStateTime::ACT_PDN 120922250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT_PDN 120934750 # Time in different power states
250,257c250,257
< system.physmem_1.actBackEnergy 9798300 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 485280 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 44769510 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 12438720 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 4465980 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 90204585 # Total energy per rank (pJ)
< system.physmem_1.averagePower 539.085991 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 144266000 # Total Idle time Per DRAM Rank
---
> system.physmem_1.actBackEnergy 9796590 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 484800 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 44771220 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 12438240 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 4464180 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 90201825 # Total energy per rank (pJ)
> system.physmem_1.averagePower 539.101715 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 144258000 # Total Idle time Per DRAM Rank
260,261c260,261
< system.physmem_1.memoryStateTime::SREF 14006250 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 32390000 # Time in different power states
---
> system.physmem_1.memoryStateTime::SREF 13998250 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 32388000 # Time in different power states
263,269c263,269
< system.physmem_1.memoryStateTime::ACT_PDN 98166500 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 31621 # Number of BP lookups
< system.cpu.branchPred.condPredicted 20020 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 2186 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 28229 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 15507 # Number of BTB hits
---
> system.physmem_1.memoryStateTime::ACT_PDN 98166000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 31578 # Number of BP lookups
> system.cpu.branchPred.condPredicted 20002 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 2179 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 27728 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 15512 # Number of BTB hits
271c271
< system.cpu.branchPred.BTBHitPct 54.932870 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 55.943451 # BTB Hit Percentage
274,276c274,276
< system.cpu.branchPred.indirectLookups 5663 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 3671 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 1992 # Number of indirect misses.
---
> system.cpu.branchPred.indirectLookups 5649 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 3670 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 1979 # Number of indirect misses.
298,299c298,299
< system.cpu.pwrStateResidencyTicks::ON 167328500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 334657 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 167318000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 334636 # number of cpu cycles simulated
304c304
< system.cpu.discardedOps 5904 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 5891 # Number of ops (including micro ops) which were discarded before commit
306,307c306,307
< system.cpu.cpi 2.935819 # CPI: cycles per instruction
< system.cpu.ipc 0.340620 # IPC: instructions per cycle
---
> system.cpu.cpi 2.935635 # CPI: cycles per instruction
> system.cpu.ipc 0.340642 # IPC: instructions per cycle
347,349c347,349
< system.cpu.tickCycles 171660 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 162997 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 171594 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 163042 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
351,352c351,352
< system.cpu.dcache.tags.tagsinuse 215.204481 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 44066 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 215.201598 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 44063 # Total number of references to valid blocks.
354c354
< system.cpu.dcache.tags.avg_refs 164.425373 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 164.414179 # Average number of references to valid blocks.
356,358c356,358
< system.cpu.dcache.tags.occ_blocks::cpu.data 215.204481 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.052540 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.052540 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 215.201598 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.052539 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.052539 # Average percentage of cache occupancy
364,368c364,368
< system.cpu.dcache.tags.tag_accesses 89318 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 89318 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 24534 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 24534 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 89312 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 89312 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 24531 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 24531 # number of ReadReq hits
375,378c375,378
< system.cpu.dcache.demand_hits::cpu.data 44060 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 44060 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 44060 # number of overall hits
< system.cpu.dcache.overall_hits::total 44060 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 44057 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 44057 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 44057 # number of overall hits
> system.cpu.dcache.overall_hits::total 44057 # number of overall hits
387,388c387,388
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8632000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8632500 # number of ReadReq miss cycles
391,396c391,396
< system.cpu.dcache.demand_miss_latency::cpu.data 39369000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 39369000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 39369000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 39369000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 39369500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 39369500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 39369500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 39369500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 24606 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 24606 # number of ReadReq accesses(hits+misses)
403,406c403,406
< system.cpu.dcache.demand_accesses::cpu.data 44519 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 44519 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 44519 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 44519 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 44516 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 44516 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 44516 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 44516 # number of overall (read+write) accesses
411,416c411,416
< system.cpu.dcache.demand_miss_rate::cpu.data 0.010310 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.010310 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.010310 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.010310 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115093.333333 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 115093.333333 # average ReadReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.010311 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.010311 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.010311 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.010311 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115100 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 115100 # average ReadReq miss latency
419,422c419,422
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 85771.241830 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 85771.241830 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 85772.331155 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 85772.331155 # average overall miss latency
445,446c445,446
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963500 # number of ReadReq MSHR miss cycles
449,452c449,452
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23916500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 23916500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23916500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 23916500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23917000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 23917000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23917000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 23917000 # number of overall MSHR miss cycles
461,462c461,462
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115405.797101 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115405.797101 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115413.043478 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115413.043478 # average ReadReq mshr miss latency
465,469c465,469
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
471,472c471,472
< system.cpu.icache.tags.tagsinuse 401.761519 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 49677 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 401.741743 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 49660 # Total number of references to valid blocks.
474c474
< system.cpu.icache.tags.avg_refs 60.360875 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 60.340219 # Average number of references to valid blocks.
476,478c476,478
< system.cpu.icache.tags.occ_blocks::cpu.inst 401.761519 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.196173 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.196173 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 401.741743 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.196163 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.196163 # Average percentage of cache occupancy
484,492c484,492
< system.cpu.icache.tags.tag_accesses 101823 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 101823 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 49677 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 49677 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 49677 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 49677 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 49677 # number of overall hits
< system.cpu.icache.overall_hits::total 49677 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 101789 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 101789 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 49660 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 49660 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 49660 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 49660 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 49660 # number of overall hits
> system.cpu.icache.overall_hits::total 49660 # number of overall hits
499,522c499,522
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 69966000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 69966000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 69966000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 69966000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 69966000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 69966000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 50500 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 50500 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 50500 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 50500 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 50500 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 50500 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016297 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.016297 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.016297 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.016297 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.016297 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.016297 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85013.365735 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 85013.365735 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 85013.365735 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 85013.365735 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 69983000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 69983000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 69983000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 69983000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 69983000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 69983000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 50483 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 50483 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 50483 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 50483 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 50483 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 50483 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016303 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.016303 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.016303 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.016303 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.016303 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.016303 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85034.021871 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 85034.021871 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 85034.021871 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 85034.021871 # average overall miss latency
537,555c537,555
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69143000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 69143000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69143000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 69143000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69143000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 69143000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016297 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.016297 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.016297 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84013.365735 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84013.365735 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 69160000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 69160000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 69160000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016303 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.016303 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.016303 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84034.021871 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84034.021871 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
557c557
< system.cpu.l2cache.tags.tagsinuse 622.728504 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 622.705265 # Cycle average of tags in use
562,563c562,563
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.968080 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 214.760424 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.947689 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 214.757576 # Average occupied blocks per requestor
566c566
< system.cpu.l2cache.tags.occ_percent::total 0.019004 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.019003 # Average percentage of cache occupancy
574c574
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
597,606c597,606
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67908500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 67908500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 67908500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 23501000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 91409500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 67908500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 23501000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 91409500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67925500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 67925500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 67925500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 23501500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 91427000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 67925500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 23501500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 91427000 # number of overall miss cycles
635,644c635,644
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82513.365735 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82513.365735 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115397.058824 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115397.058824 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 83861.926606 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 83861.926606 # average overall miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82534.021871 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82534.021871 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115404.411765 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115404.411765 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 83877.981651 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 83877.981651 # average overall miss latency
665,674c665,674
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59678500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59678500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59678500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 80509500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59678500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 80509500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59695500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59695500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59695500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 80527000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59695500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 80527000 # number of overall MSHR miss cycles
689,698c689,698
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72513.365735 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72513.365735 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105397.058824 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105397.058824 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72534.021871 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72534.021871 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105404.411765 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105404.411765 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency
705c705
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
743c743
< system.membus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
764c764
< system.membus.reqLayer0.occupancy 1226500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 1229000 # Layer occupancy (ticks)
< sim_ticks 167328500 # Number of ticks simulated
< final_tick 167328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 167318000 # Number of ticks simulated
> final_tick 167318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 54302 # Simulator instruction rate (inst/s)
< host_op_rate 54316 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 79708249 # Simulator tick rate (ticks/s)
< host_mem_usage 244184 # Number of bytes of host memory used
< host_seconds 2.10 # Real time elapsed on the host
---
> host_inst_rate 259842 # Simulator instruction rate (inst/s)
> host_op_rate 259907 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 381385356 # Simulator tick rate (ticks/s)
> host_mem_usage 261864 # Number of bytes of host memory used
> host_seconds 0.44 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 314782001 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 102122472 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 416904472 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 314782001 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 314782001 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 314782001 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 102122472 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 416904472 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 314801755 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 102128880 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 416930635 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 314801755 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 314801755 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 314801755 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 102128880 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 416930635 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 166995000 # Total gap between requests
---
> system.physmem.totGap 166987000 # Total gap between requests
204,205c204,205
< system.physmem.totQLat 15434500 # Total ticks spent queuing
< system.physmem.totMemAccLat 35872000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 15449500 # Total ticks spent queuing
> system.physmem.totMemAccLat 35887000 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 14160.09 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 14173.85 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 32910.09 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 416.90 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 32923.85 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 416.93 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 416.90 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 416.93 # Average system read bandwidth in MiByte/s
224c224
< system.physmem.avgGap 153206.42 # Average gap between requests
---
> system.physmem.avgGap 153199.08 # Average gap between requests
231,234c231,234
< system.physmem_0.actBackEnergy 9305250 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 493440 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 55143510 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 7150560 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_0.actBackEnergy 9302400 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 492960 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 55152630 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 7141920 # Energy for precharge power-down per rank (pJ)
236,238c236,238
< system.physmem_0.totalEnergy 92951370 # Total energy per rank (pJ)
< system.physmem_0.averagePower 555.501490 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 145131750 # Total Idle time Per DRAM Rank
---
> system.physmem_0.totalEnergy 92948520 # Total energy per rank (pJ)
> system.physmem_0.averagePower 555.517657 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 145123750 # Total Idle time Per DRAM Rank
242c242
< system.physmem_0.memoryStateTime::PRE_PDN 18616750 # Time in different power states
---
> system.physmem_0.memoryStateTime::PRE_PDN 18593750 # Time in different power states
244c244
< system.physmem_0.memoryStateTime::ACT_PDN 120922250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT_PDN 120934750 # Time in different power states
250,257c250,257
< system.physmem_1.actBackEnergy 9798300 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 485280 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 44769510 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 12438720 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 4465980 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 90204585 # Total energy per rank (pJ)
< system.physmem_1.averagePower 539.085991 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 144266000 # Total Idle time Per DRAM Rank
---
> system.physmem_1.actBackEnergy 9796590 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 484800 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 44771220 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 12438240 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 4464180 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 90201825 # Total energy per rank (pJ)
> system.physmem_1.averagePower 539.101715 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 144258000 # Total Idle time Per DRAM Rank
260,261c260,261
< system.physmem_1.memoryStateTime::SREF 14006250 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 32390000 # Time in different power states
---
> system.physmem_1.memoryStateTime::SREF 13998250 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 32388000 # Time in different power states
263,269c263,269
< system.physmem_1.memoryStateTime::ACT_PDN 98166500 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 31621 # Number of BP lookups
< system.cpu.branchPred.condPredicted 20020 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 2186 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 28229 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 15507 # Number of BTB hits
---
> system.physmem_1.memoryStateTime::ACT_PDN 98166000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 31578 # Number of BP lookups
> system.cpu.branchPred.condPredicted 20002 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 2179 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 27728 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 15512 # Number of BTB hits
271c271
< system.cpu.branchPred.BTBHitPct 54.932870 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 55.943451 # BTB Hit Percentage
274,276c274,276
< system.cpu.branchPred.indirectLookups 5663 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 3671 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 1992 # Number of indirect misses.
---
> system.cpu.branchPred.indirectLookups 5649 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 3670 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 1979 # Number of indirect misses.
298,299c298,299
< system.cpu.pwrStateResidencyTicks::ON 167328500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 334657 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 167318000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 334636 # number of cpu cycles simulated
304c304
< system.cpu.discardedOps 5904 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 5891 # Number of ops (including micro ops) which were discarded before commit
306,307c306,307
< system.cpu.cpi 2.935819 # CPI: cycles per instruction
< system.cpu.ipc 0.340620 # IPC: instructions per cycle
---
> system.cpu.cpi 2.935635 # CPI: cycles per instruction
> system.cpu.ipc 0.340642 # IPC: instructions per cycle
347,349c347,349
< system.cpu.tickCycles 171660 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 162997 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 171594 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 163042 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
351,352c351,352
< system.cpu.dcache.tags.tagsinuse 215.204481 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 44066 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 215.201598 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 44063 # Total number of references to valid blocks.
354c354
< system.cpu.dcache.tags.avg_refs 164.425373 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 164.414179 # Average number of references to valid blocks.
356,358c356,358
< system.cpu.dcache.tags.occ_blocks::cpu.data 215.204481 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.052540 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.052540 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 215.201598 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.052539 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.052539 # Average percentage of cache occupancy
364,368c364,368
< system.cpu.dcache.tags.tag_accesses 89318 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 89318 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 24534 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 24534 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 89312 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 89312 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 24531 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 24531 # number of ReadReq hits
375,378c375,378
< system.cpu.dcache.demand_hits::cpu.data 44060 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 44060 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 44060 # number of overall hits
< system.cpu.dcache.overall_hits::total 44060 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 44057 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 44057 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 44057 # number of overall hits
> system.cpu.dcache.overall_hits::total 44057 # number of overall hits
387,388c387,388
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8632000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8632500 # number of ReadReq miss cycles
391,396c391,396
< system.cpu.dcache.demand_miss_latency::cpu.data 39369000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 39369000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 39369000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 39369000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 39369500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 39369500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 39369500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 39369500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 24606 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 24606 # number of ReadReq accesses(hits+misses)
403,406c403,406
< system.cpu.dcache.demand_accesses::cpu.data 44519 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 44519 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 44519 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 44519 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 44516 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 44516 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 44516 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 44516 # number of overall (read+write) accesses
411,416c411,416
< system.cpu.dcache.demand_miss_rate::cpu.data 0.010310 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.010310 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.010310 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.010310 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115093.333333 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 115093.333333 # average ReadReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.010311 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.010311 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.010311 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.010311 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115100 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 115100 # average ReadReq miss latency
419,422c419,422
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 85771.241830 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 85771.241830 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 85772.331155 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 85772.331155 # average overall miss latency
445,446c445,446
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963500 # number of ReadReq MSHR miss cycles
449,452c449,452
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23916500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 23916500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23916500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 23916500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23917000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 23917000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23917000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 23917000 # number of overall MSHR miss cycles
461,462c461,462
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115405.797101 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115405.797101 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115413.043478 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115413.043478 # average ReadReq mshr miss latency
465,469c465,469
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
471,472c471,472
< system.cpu.icache.tags.tagsinuse 401.761519 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 49677 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 401.741743 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 49660 # Total number of references to valid blocks.
474c474
< system.cpu.icache.tags.avg_refs 60.360875 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 60.340219 # Average number of references to valid blocks.
476,478c476,478
< system.cpu.icache.tags.occ_blocks::cpu.inst 401.761519 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.196173 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.196173 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 401.741743 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.196163 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.196163 # Average percentage of cache occupancy
484,492c484,492
< system.cpu.icache.tags.tag_accesses 101823 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 101823 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 49677 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 49677 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 49677 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 49677 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 49677 # number of overall hits
< system.cpu.icache.overall_hits::total 49677 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 101789 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 101789 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 49660 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 49660 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 49660 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 49660 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 49660 # number of overall hits
> system.cpu.icache.overall_hits::total 49660 # number of overall hits
499,522c499,522
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 69966000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 69966000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 69966000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 69966000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 69966000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 69966000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 50500 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 50500 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 50500 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 50500 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 50500 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 50500 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016297 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.016297 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.016297 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.016297 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.016297 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.016297 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85013.365735 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 85013.365735 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 85013.365735 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 85013.365735 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 69983000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 69983000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 69983000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 69983000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 69983000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 69983000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 50483 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 50483 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 50483 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 50483 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 50483 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 50483 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016303 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.016303 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.016303 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.016303 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.016303 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.016303 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85034.021871 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 85034.021871 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 85034.021871 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 85034.021871 # average overall miss latency
537,555c537,555
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69143000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 69143000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69143000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 69143000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69143000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 69143000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016297 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.016297 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.016297 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84013.365735 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84013.365735 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 69160000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 69160000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 69160000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016303 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.016303 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.016303 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84034.021871 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84034.021871 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
557c557
< system.cpu.l2cache.tags.tagsinuse 622.728504 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 622.705265 # Cycle average of tags in use
562,563c562,563
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.968080 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 214.760424 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.947689 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 214.757576 # Average occupied blocks per requestor
566c566
< system.cpu.l2cache.tags.occ_percent::total 0.019004 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.019003 # Average percentage of cache occupancy
574c574
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
597,606c597,606
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67908500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 67908500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 67908500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 23501000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 91409500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 67908500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 23501000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 91409500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67925500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 67925500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 67925500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 23501500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 91427000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 67925500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 23501500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 91427000 # number of overall miss cycles
635,644c635,644
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82513.365735 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82513.365735 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115397.058824 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115397.058824 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 83861.926606 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 83861.926606 # average overall miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82534.021871 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82534.021871 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115404.411765 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115404.411765 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 83877.981651 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 83877.981651 # average overall miss latency
665,674c665,674
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59678500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59678500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59678500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 80509500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59678500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 80509500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59695500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59695500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59695500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 80527000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59695500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 80527000 # number of overall MSHR miss cycles
689,698c689,698
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72513.365735 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72513.365735 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105397.058824 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105397.058824 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72534.021871 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72534.021871 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105404.411765 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105404.411765 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency
705c705
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
743c743
< system.membus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
764c764
< system.membus.reqLayer0.occupancy 1226500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 1229000 # Layer occupancy (ticks)