| stats.txt (9702:094d0280e481) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 28358000 # Number of ticks simulated 5final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 90736 # Simulator instruction rate (inst/s) 8host_op_rate 164316 # Simulator op (including micro ops) rate (op/s) --- 13 unchanged lines hidden (view full) --- 22system.physmem.bw_read::cpu.inst 512306933 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 302419070 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 814726003 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 512306933 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 512306933 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s) | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 28358000 # Number of ticks simulated 5final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 90736 # Simulator instruction rate (inst/s) 8host_op_rate 164316 # Simulator op (including micro ops) rate (op/s) --- 13 unchanged lines hidden (view full) --- 22system.physmem.bw_read::cpu.inst 512306933 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 302419070 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 814726003 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 512306933 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 512306933 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s) |
| 30system.membus.throughput 814726003 # Throughput (bytes/s) 31system.membus.trans_dist::ReadReq 282 # Transaction distribution 32system.membus.trans_dist::ReadResp 282 # Transaction distribution 33system.membus.trans_dist::ReadExReq 79 # Transaction distribution 34system.membus.trans_dist::ReadExResp 79 # Transaction distribution 35system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) 36system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) 37system.membus.pkt_count::system.physmem.port 722 # Packet count per connected master and slave (bytes) 38system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) 39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) 40system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) 41system.membus.tot_pkt_size::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) 42system.membus.tot_pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) 43system.membus.data_through_bus 23104 # Total data (bytes) 44system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 45system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks) 46system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) 47system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks) 48system.membus.respLayer1.utilization 11.5 # Layer utilization (%) |
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| 30system.cpu.workload.num_syscalls 11 # Number of system calls 31system.cpu.numCycles 56716 # number of cpu cycles simulated 32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 34system.cpu.committedInsts 5381 # Number of instructions committed 35system.cpu.committedOps 9748 # Number of ops (including micro ops) committed 36system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses 37system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses --- 308 unchanged lines hidden (view full) --- 346system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 348system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 349system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 350system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 351system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 352system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 353system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 49system.cpu.workload.num_syscalls 11 # Number of system calls 50system.cpu.numCycles 56716 # number of cpu cycles simulated 51system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 52system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 53system.cpu.committedInsts 5381 # Number of instructions committed 54system.cpu.committedOps 9748 # Number of ops (including micro ops) committed 55system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses 56system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses --- 308 unchanged lines hidden (view full) --- 365system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 366system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 367system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 368system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 369system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 370system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 371system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 372system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 373system.cpu.toL2Bus.throughput 816982862 # Throughput (bytes/s) 374system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution 375system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution 376system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution 377system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution 378system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 456 # Packet count per connected master and slave (bytes) 379system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 268 # Packet count per connected master and slave (bytes) 380system.cpu.toL2Bus.pkt_count 724 # Packet count per connected master and slave (bytes) 381system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 14592 # Cumulative packet size per connected master and slave (bytes) 382system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8576 # Cumulative packet size per connected master and slave (bytes) 383system.cpu.toL2Bus.tot_pkt_size 23168 # Cumulative packet size per connected master and slave (bytes) 384system.cpu.toL2Bus.data_through_bus 23168 # Total data (bytes) 385system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 386system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) 387system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 388system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) 389system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) 390system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) 391system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) |
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| 354 355---------- End Simulation Statistics ---------- | 392 393---------- End Simulation Statistics ---------- |