| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated |
| 4sim_ticks 30886500 # Number of ticks simulated 5final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 31247500 # Number of ticks simulated 5final_tick 31247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 211795 # Simulator instruction rate (inst/s) 8host_op_rate 383429 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1214135841 # Simulator tick rate (ticks/s) 10host_mem_usage 263924 # Number of bytes of host memory used 11host_seconds 0.03 # Real time elapsed on the host | 7host_inst_rate 85405 # Simulator instruction rate (inst/s) 8host_op_rate 154687 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 495766938 # Simulator tick rate (ticks/s) 10host_mem_usage 269328 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host |
| 12sim_insts 5381 # Number of instructions simulated 13sim_ops 9748 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 5381 # Number of instructions simulated 13sim_ops 9748 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 19system.physmem.bytes_read::total 23104 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 361 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 19system.physmem.bytes_read::total 23104 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 361 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 470367313 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 277661762 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 748029074 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 470367313 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 470367313 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 470367313 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 277661762 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 748029074 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states | 25system.physmem.bw_read::cpu.inst 464933195 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 274453956 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 739387151 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 464933195 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 464933195 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 464933195 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 274453956 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 739387151 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states |
| 34system.cpu_clk_domain.clock 500 # Clock period in ticks | 34system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 35system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states | 35system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states |
| 36system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 36system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 37system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states 38system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states | 37system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 38system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states |
| 39system.cpu.workload.num_syscalls 11 # Number of system calls | 39system.cpu.workload.num_syscalls 11 # Number of system calls |
| 40system.cpu.pwrStateResidencyTicks::ON 30886500 # Cumulative time (in ticks) in various power states 41system.cpu.numCycles 61773 # number of cpu cycles simulated | 40system.cpu.pwrStateResidencyTicks::ON 31247500 # Cumulative time (in ticks) in various power states 41system.cpu.numCycles 62495 # number of cpu cycles simulated |
| 42system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 44system.cpu.committedInsts 5381 # Number of instructions committed 45system.cpu.committedOps 9748 # Number of ops (including micro ops) committed 46system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses 47system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 48system.cpu.num_func_calls 209 # number of times a function call or return occured 49system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 54system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 55system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 56system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read 57system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written 58system.cpu.num_mem_refs 1988 # number of memory refs 59system.cpu.num_load_insts 1053 # Number of load instructions 60system.cpu.num_store_insts 935 # Number of store instructions 61system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 42system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 44system.cpu.committedInsts 5381 # Number of instructions committed 45system.cpu.committedOps 9748 # Number of ops (including micro ops) committed 46system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses 47system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 48system.cpu.num_func_calls 209 # number of times a function call or return occured 49system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 54system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 55system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 56system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read 57system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written 58system.cpu.num_mem_refs 1988 # number of memory refs 59system.cpu.num_load_insts 1053 # Number of load instructions 60system.cpu.num_store_insts 935 # Number of store instructions 61system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 62system.cpu.num_busy_cycles 61772.998000 # Number of busy cycles | 62system.cpu.num_busy_cycles 62494.998000 # Number of busy cycles |
| 63system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 64system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 65system.cpu.Branches 1208 # Number of branches fetched 66system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 67system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction 68system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction 69system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction 70system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 93system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction 94system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction 95system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction 96system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction 97system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction 98system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 99system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::total 9748 # Class of executed instruction | 63system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 64system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 65system.cpu.Branches 1208 # Number of branches fetched 66system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 67system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction 68system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction 69system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction 70system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 93system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction 94system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction 95system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction 96system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction 97system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction 98system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 99system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::total 9748 # Class of executed instruction |
| 101system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states | 101system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states |
| 102system.cpu.dcache.tags.replacements 0 # number of replacements | 102system.cpu.dcache.tags.replacements 0 # number of replacements |
| 103system.cpu.dcache.tags.tagsinuse 80.558239 # Cycle average of tags in use | 103system.cpu.dcache.tags.tagsinuse 80.527852 # Cycle average of tags in use |
| 104system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 104system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 108system.cpu.dcache.tags.occ_blocks::cpu.data 80.558239 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.019668 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.019668 # Average percentage of cache occupancy | 108system.cpu.dcache.tags.occ_blocks::cpu.data 80.527852 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.019660 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.019660 # Average percentage of cache occupancy |
| 111system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 114system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id 115system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses 116system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses | 111system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 114system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id 115system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses 116system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses |
| 117system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states | 117system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states |
| 118system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits 119system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits 120system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits 121system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits 122system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits 123system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits 124system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits 125system.cpu.dcache.overall_hits::total 1854 # number of overall hits 126system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses 127system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses 128system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses 129system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses 130system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses 131system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses 132system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses 133system.cpu.dcache.overall_misses::total 134 # number of overall misses | 118system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits 119system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits 120system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits 121system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits 122system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits 123system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits 124system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits 125system.cpu.dcache.overall_hits::total 1854 # number of overall hits 126system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses 127system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses 128system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses 129system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses 130system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses 131system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses 132system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses 133system.cpu.dcache.overall_misses::total 134 # number of overall misses |
| 134system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles 135system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles 136system.cpu.dcache.WriteReq_miss_latency::cpu.data 4898000 # number of WriteReq miss cycles 137system.cpu.dcache.WriteReq_miss_latency::total 4898000 # number of WriteReq miss cycles 138system.cpu.dcache.demand_miss_latency::cpu.data 8308000 # number of demand (read+write) miss cycles 139system.cpu.dcache.demand_miss_latency::total 8308000 # number of demand (read+write) miss cycles 140system.cpu.dcache.overall_miss_latency::cpu.data 8308000 # number of overall miss cycles 141system.cpu.dcache.overall_miss_latency::total 8308000 # number of overall miss cycles | 134system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles 135system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles 136system.cpu.dcache.WriteReq_miss_latency::cpu.data 4977000 # number of WriteReq miss cycles 137system.cpu.dcache.WriteReq_miss_latency::total 4977000 # number of WriteReq miss cycles 138system.cpu.dcache.demand_miss_latency::cpu.data 8442000 # number of demand (read+write) miss cycles 139system.cpu.dcache.demand_miss_latency::total 8442000 # number of demand (read+write) miss cycles 140system.cpu.dcache.overall_miss_latency::cpu.data 8442000 # number of overall miss cycles 141system.cpu.dcache.overall_miss_latency::total 8442000 # number of overall miss cycles |
| 142system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) 143system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) 144system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 145system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) 146system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses 147system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses 148system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses 149system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses 150system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses 151system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses 152system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses 153system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses 154system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses 155system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses 156system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses 157system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses | 142system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) 143system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) 144system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 145system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) 146system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses 147system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses 148system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses 149system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses 150system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses 151system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses 152system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses 153system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses 154system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses 155system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses 156system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses 157system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses |
| 158system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency 159system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency 160system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency 161system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency 162system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency 163system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency 164system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency 165system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency | 158system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency 159system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency 160system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency 161system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency 162system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency 163system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency 164system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency 165system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency |
| 166system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 167system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 168system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 169system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 170system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 171system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 172system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 173system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 174system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses 175system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses 176system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 177system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses 178system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 179system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses | 166system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 167system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 168system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 169system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 170system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 171system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 172system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 173system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 174system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses 175system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses 176system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 177system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses 178system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 179system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses |
| 180system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles 181system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles 182system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4819000 # number of WriteReq MSHR miss cycles 183system.cpu.dcache.WriteReq_mshr_miss_latency::total 4819000 # number of WriteReq MSHR miss cycles 184system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8174000 # number of demand (read+write) MSHR miss cycles 185system.cpu.dcache.demand_mshr_miss_latency::total 8174000 # number of demand (read+write) MSHR miss cycles 186system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8174000 # number of overall MSHR miss cycles 187system.cpu.dcache.overall_mshr_miss_latency::total 8174000 # number of overall MSHR miss cycles | 180system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles 181system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles 182system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4898000 # number of WriteReq MSHR miss cycles 183system.cpu.dcache.WriteReq_mshr_miss_latency::total 4898000 # number of WriteReq MSHR miss cycles 184system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8308000 # number of demand (read+write) MSHR miss cycles 185system.cpu.dcache.demand_mshr_miss_latency::total 8308000 # number of demand (read+write) MSHR miss cycles 186system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8308000 # number of overall MSHR miss cycles 187system.cpu.dcache.overall_mshr_miss_latency::total 8308000 # number of overall MSHR miss cycles |
| 188system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses 189system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses 190system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses 191system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses 192system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses 193system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses 194system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses 195system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses | 188system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses 189system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses 190system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses 191system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses 192system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses 193system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses 194system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses 195system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses |
| 196system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 197system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 198system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 199system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 200system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 201system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 202system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 203system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 204system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states | 196system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency 197system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency 198system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency 199system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency 200system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency 201system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency 202system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency 203system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency 204system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states |
| 205system.cpu.icache.tags.replacements 0 # number of replacements | 205system.cpu.icache.tags.replacements 0 # number of replacements |
| 206system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use | 206system.cpu.icache.tags.tagsinuse 105.231814 # Cycle average of tags in use |
| 207system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. 208system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. 209system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. 210system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 207system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. 208system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. 209system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. 210system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 211system.cpu.icache.tags.occ_blocks::cpu.inst 105.267613 # Average occupied blocks per requestor 212system.cpu.icache.tags.occ_percent::cpu.inst 0.051400 # Average percentage of cache occupancy 213system.cpu.icache.tags.occ_percent::total 0.051400 # Average percentage of cache occupancy | 211system.cpu.icache.tags.occ_blocks::cpu.inst 105.231814 # Average occupied blocks per requestor 212system.cpu.icache.tags.occ_percent::cpu.inst 0.051383 # Average percentage of cache occupancy 213system.cpu.icache.tags.occ_percent::total 0.051383 # Average percentage of cache occupancy |
| 214system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id | 214system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id |
| 215system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id 216system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id | 215system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id 216system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id |
| 217system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id 218system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses 219system.cpu.icache.tags.data_accesses 13956 # Number of data accesses | 217system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id 218system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses 219system.cpu.icache.tags.data_accesses 13956 # Number of data accesses |
| 220system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states | 220system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states |
| 221system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits 222system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits 223system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits 224system.cpu.icache.demand_hits::total 6636 # number of demand (read+write) hits 225system.cpu.icache.overall_hits::cpu.inst 6636 # number of overall hits 226system.cpu.icache.overall_hits::total 6636 # number of overall hits 227system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses 228system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses 229system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses 230system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses 231system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses 232system.cpu.icache.overall_misses::total 228 # number of overall misses | 221system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits 222system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits 223system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits 224system.cpu.icache.demand_hits::total 6636 # number of demand (read+write) hits 225system.cpu.icache.overall_hits::cpu.inst 6636 # number of overall hits 226system.cpu.icache.overall_hits::total 6636 # number of overall hits 227system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses 228system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses 229system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses 230system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses 231system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses 232system.cpu.icache.overall_misses::total 228 # number of overall misses |
| 233system.cpu.icache.ReadReq_miss_latency::cpu.inst 14088500 # number of ReadReq miss cycles 234system.cpu.icache.ReadReq_miss_latency::total 14088500 # number of ReadReq miss cycles 235system.cpu.icache.demand_miss_latency::cpu.inst 14088500 # number of demand (read+write) miss cycles 236system.cpu.icache.demand_miss_latency::total 14088500 # number of demand (read+write) miss cycles 237system.cpu.icache.overall_miss_latency::cpu.inst 14088500 # number of overall miss cycles 238system.cpu.icache.overall_miss_latency::total 14088500 # number of overall miss cycles | 233system.cpu.icache.ReadReq_miss_latency::cpu.inst 14315500 # number of ReadReq miss cycles 234system.cpu.icache.ReadReq_miss_latency::total 14315500 # number of ReadReq miss cycles 235system.cpu.icache.demand_miss_latency::cpu.inst 14315500 # number of demand (read+write) miss cycles 236system.cpu.icache.demand_miss_latency::total 14315500 # number of demand (read+write) miss cycles 237system.cpu.icache.overall_miss_latency::cpu.inst 14315500 # number of overall miss cycles 238system.cpu.icache.overall_miss_latency::total 14315500 # number of overall miss cycles |
| 239system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) 240system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) 241system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses 242system.cpu.icache.demand_accesses::total 6864 # number of demand (read+write) accesses 243system.cpu.icache.overall_accesses::cpu.inst 6864 # number of overall (read+write) accesses 244system.cpu.icache.overall_accesses::total 6864 # number of overall (read+write) accesses 245system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033217 # miss rate for ReadReq accesses 246system.cpu.icache.ReadReq_miss_rate::total 0.033217 # miss rate for ReadReq accesses 247system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 # miss rate for demand accesses 248system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses 249system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses 250system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses | 239system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) 240system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) 241system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses 242system.cpu.icache.demand_accesses::total 6864 # number of demand (read+write) accesses 243system.cpu.icache.overall_accesses::cpu.inst 6864 # number of overall (read+write) accesses 244system.cpu.icache.overall_accesses::total 6864 # number of overall (read+write) accesses 245system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033217 # miss rate for ReadReq accesses 246system.cpu.icache.ReadReq_miss_rate::total 0.033217 # miss rate for ReadReq accesses 247system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 # miss rate for demand accesses 248system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses 249system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses 250system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses |
| 251system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61791.666667 # average ReadReq miss latency 252system.cpu.icache.ReadReq_avg_miss_latency::total 61791.666667 # average ReadReq miss latency 253system.cpu.icache.demand_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency 254system.cpu.icache.demand_avg_miss_latency::total 61791.666667 # average overall miss latency 255system.cpu.icache.overall_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency 256system.cpu.icache.overall_avg_miss_latency::total 61791.666667 # average overall miss latency | 251system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62787.280702 # average ReadReq miss latency 252system.cpu.icache.ReadReq_avg_miss_latency::total 62787.280702 # average ReadReq miss latency 253system.cpu.icache.demand_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency 254system.cpu.icache.demand_avg_miss_latency::total 62787.280702 # average overall miss latency 255system.cpu.icache.overall_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency 256system.cpu.icache.overall_avg_miss_latency::total 62787.280702 # average overall miss latency |
| 257system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 258system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 259system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 260system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 261system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 262system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 263system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses 264system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses 265system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses 266system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses 267system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses 268system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses | 257system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 258system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 259system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 260system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 261system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 262system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 263system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses 264system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses 265system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses 266system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses 267system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses 268system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses |
| 269system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13860500 # number of ReadReq MSHR miss cycles 270system.cpu.icache.ReadReq_mshr_miss_latency::total 13860500 # number of ReadReq MSHR miss cycles 271system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13860500 # number of demand (read+write) MSHR miss cycles 272system.cpu.icache.demand_mshr_miss_latency::total 13860500 # number of demand (read+write) MSHR miss cycles 273system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13860500 # number of overall MSHR miss cycles 274system.cpu.icache.overall_mshr_miss_latency::total 13860500 # number of overall MSHR miss cycles | 269system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14087500 # number of ReadReq MSHR miss cycles 270system.cpu.icache.ReadReq_mshr_miss_latency::total 14087500 # number of ReadReq MSHR miss cycles 271system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14087500 # number of demand (read+write) MSHR miss cycles 272system.cpu.icache.demand_mshr_miss_latency::total 14087500 # number of demand (read+write) MSHR miss cycles 273system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14087500 # number of overall MSHR miss cycles 274system.cpu.icache.overall_mshr_miss_latency::total 14087500 # number of overall MSHR miss cycles |
| 275system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses 276system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses 277system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses 278system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses 279system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses 280system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses | 275system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses 276system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses 277system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses 278system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses 279system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses 280system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses |
| 281system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60791.666667 # average ReadReq mshr miss latency 282system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60791.666667 # average ReadReq mshr miss latency 283system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency 284system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency 285system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency 286system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency 287system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states | 281system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61787.280702 # average ReadReq mshr miss latency 282system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61787.280702 # average ReadReq mshr miss latency 283system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency 284system.cpu.icache.demand_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency 285system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency 286system.cpu.icache.overall_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency 287system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states |
| 288system.cpu.l2cache.tags.replacements 0 # number of replacements | 288system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 289system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use | 289system.cpu.l2cache.tags.tagsinuse 185.792229 # Cycle average of tags in use |
| 290system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. | 290system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. |
| 291system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. 292system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. | 291system.cpu.l2cache.tags.sampled_refs 361 # Sample count of references to valid blocks. 292system.cpu.l2cache.tags.avg_refs 0.002770 # Average number of references to valid blocks. |
| 293system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 293system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 294system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.256135 # Average occupied blocks per requestor 295system.cpu.l2cache.tags.occ_blocks::cpu.data 28.415959 # Average occupied blocks per requestor 296system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003212 # Average percentage of cache occupancy 297system.cpu.l2cache.tags.occ_percent::cpu.data 0.000867 # Average percentage of cache occupancy 298system.cpu.l2cache.tags.occ_percent::total 0.004079 # Average percentage of cache occupancy 299system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id 300system.cpu.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 301system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id 302system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id | 294system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.219349 # Average occupied blocks per requestor 295system.cpu.l2cache.tags.occ_blocks::cpu.data 80.572880 # Average occupied blocks per requestor 296system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003211 # Average percentage of cache occupancy 297system.cpu.l2cache.tags.occ_percent::cpu.data 0.002459 # Average percentage of cache occupancy 298system.cpu.l2cache.tags.occ_percent::total 0.005670 # Average percentage of cache occupancy 299system.cpu.l2cache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id 300system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 301system.cpu.l2cache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id 302system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011017 # Percentage of cache occupancy per task id |
| 303system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses 304system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses | 303system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses 304system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses |
| 305system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states | 305system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states |
| 306system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 307system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 308system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 309system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 310system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 311system.cpu.l2cache.overall_hits::total 1 # number of overall hits 312system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses 313system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses 314system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 227 # number of ReadCleanReq misses 315system.cpu.l2cache.ReadCleanReq_misses::total 227 # number of ReadCleanReq misses 316system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses 317system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses 318system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses 319system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses 320system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses 321system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses 322system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses 323system.cpu.l2cache.overall_misses::total 361 # number of overall misses | 306system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 307system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 308system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 309system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 310system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 311system.cpu.l2cache.overall_hits::total 1 # number of overall hits 312system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses 313system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses 314system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 227 # number of ReadCleanReq misses 315system.cpu.l2cache.ReadCleanReq_misses::total 227 # number of ReadCleanReq misses 316system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses 317system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses 318system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses 319system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses 320system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses 321system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses 322system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses 323system.cpu.l2cache.overall_misses::total 361 # number of overall misses |
| 324system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4700500 # number of ReadExReq miss cycles 325system.cpu.l2cache.ReadExReq_miss_latency::total 4700500 # number of ReadExReq miss cycles 326system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13507000 # number of ReadCleanReq miss cycles 327system.cpu.l2cache.ReadCleanReq_miss_latency::total 13507000 # number of ReadCleanReq miss cycles 328system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles 329system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles 330system.cpu.l2cache.demand_miss_latency::cpu.inst 13507000 # number of demand (read+write) miss cycles 331system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles 332system.cpu.l2cache.demand_miss_latency::total 21480000 # number of demand (read+write) miss cycles 333system.cpu.l2cache.overall_miss_latency::cpu.inst 13507000 # number of overall miss cycles 334system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles 335system.cpu.l2cache.overall_miss_latency::total 21480000 # number of overall miss cycles | 324system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4779500 # number of ReadExReq miss cycles 325system.cpu.l2cache.ReadExReq_miss_latency::total 4779500 # number of ReadExReq miss cycles 326system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13734000 # number of ReadCleanReq miss cycles 327system.cpu.l2cache.ReadCleanReq_miss_latency::total 13734000 # number of ReadCleanReq miss cycles 328system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles 329system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles 330system.cpu.l2cache.demand_miss_latency::cpu.inst 13734000 # number of demand (read+write) miss cycles 331system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles 332system.cpu.l2cache.demand_miss_latency::total 21841000 # number of demand (read+write) miss cycles 333system.cpu.l2cache.overall_miss_latency::cpu.inst 13734000 # number of overall miss cycles 334system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles 335system.cpu.l2cache.overall_miss_latency::total 21841000 # number of overall miss cycles |
| 336system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) 337system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) 338system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses) 339system.cpu.l2cache.ReadCleanReq_accesses::total 228 # number of ReadCleanReq accesses(hits+misses) 340system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) 341system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) 342system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses 343system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 352system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 353system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 354system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses 355system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 356system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses 357system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses 358system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 359system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses | 336system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) 337system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) 338system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses) 339system.cpu.l2cache.ReadCleanReq_accesses::total 228 # number of ReadCleanReq accesses(hits+misses) 340system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) 341system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) 342system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses 343system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 352system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 353system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 354system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses 355system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 356system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses 357system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses 358system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 359system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses |
| 360system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency 361system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency 362system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59502.202643 # average ReadCleanReq miss latency 363system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59502.202643 # average ReadCleanReq miss latency 364system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency 365system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency 366system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency 367system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency 368system.cpu.l2cache.demand_avg_miss_latency::total 59501.385042 # average overall miss latency 369system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency 370system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 371system.cpu.l2cache.overall_avg_miss_latency::total 59501.385042 # average overall miss latency | 360system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency 361system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency 362system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.202643 # average ReadCleanReq miss latency 363system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.202643 # average ReadCleanReq miss latency 364system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency 365system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency 366system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency 367system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency 368system.cpu.l2cache.demand_avg_miss_latency::total 60501.385042 # average overall miss latency 369system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency 370system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency 371system.cpu.l2cache.overall_avg_miss_latency::total 60501.385042 # average overall miss latency |
| 372system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 373system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 374system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 375system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 376system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 377system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 378system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses 379system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses 380system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 227 # number of ReadCleanReq MSHR misses 381system.cpu.l2cache.ReadCleanReq_mshr_misses::total 227 # number of ReadCleanReq MSHR misses 382system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 383system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses 384system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses 385system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 386system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses 387system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses 388system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 389system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses | 372system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 373system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 374system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 375system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 376system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 377system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 378system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses 379system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses 380system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 227 # number of ReadCleanReq MSHR misses 381system.cpu.l2cache.ReadCleanReq_mshr_misses::total 227 # number of ReadCleanReq MSHR misses 382system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 383system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses 384system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses 385system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 386system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses 387system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses 388system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 389system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses |
| 390system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3910500 # number of ReadExReq MSHR miss cycles 391system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3910500 # number of ReadExReq MSHR miss cycles 392system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11237000 # number of ReadCleanReq MSHR miss cycles 393system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11237000 # number of ReadCleanReq MSHR miss cycles 394system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles 395system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles 396system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11237000 # number of demand (read+write) MSHR miss cycles 397system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles 398system.cpu.l2cache.demand_mshr_miss_latency::total 17870000 # number of demand (read+write) MSHR miss cycles 399system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11237000 # number of overall MSHR miss cycles 400system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles 401system.cpu.l2cache.overall_mshr_miss_latency::total 17870000 # number of overall MSHR miss cycles | 390system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3989500 # number of ReadExReq MSHR miss cycles 391system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3989500 # number of ReadExReq MSHR miss cycles 392system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11464000 # number of ReadCleanReq MSHR miss cycles 393system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11464000 # number of ReadCleanReq MSHR miss cycles 394system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2777500 # number of ReadSharedReq MSHR miss cycles 395system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2777500 # number of ReadSharedReq MSHR miss cycles 396system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11464000 # number of demand (read+write) MSHR miss cycles 397system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles 398system.cpu.l2cache.demand_mshr_miss_latency::total 18231000 # number of demand (read+write) MSHR miss cycles 399system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11464000 # number of overall MSHR miss cycles 400system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles 401system.cpu.l2cache.overall_mshr_miss_latency::total 18231000 # number of overall MSHR miss cycles |
| 402system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 403system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 404system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses 405system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995614 # mshr miss rate for ReadCleanReq accesses 406system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 407system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 408system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses 409system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 410system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses 411system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses 412system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 413system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses | 402system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 403system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 404system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses 405system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995614 # mshr miss rate for ReadCleanReq accesses 406system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 407system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 408system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses 409system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 410system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses 411system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses 412system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 413system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses |
| 414system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency 415system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency 416system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49502.202643 # average ReadCleanReq mshr miss latency 417system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49502.202643 # average ReadCleanReq mshr miss latency 418system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 419system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 420system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency 421system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 422system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency 423system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency 424system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 425system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency | 414system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency 415system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency 416system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.202643 # average ReadCleanReq mshr miss latency 417system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.202643 # average ReadCleanReq mshr miss latency 418system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency 419system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency 420system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency 421system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 422system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency 423system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency 424system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 425system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency |
| 426system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. 427system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 428system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 429system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 430system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 431system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 426system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. 427system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 428system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 429system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 430system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 431system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 432system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states | 432system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states |
| 433system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution 435system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution 436system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 # Transaction distribution 437system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution 438system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) 439system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) 440system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 454system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 455system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 456system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram 457system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) 458system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 459system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) 460system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%) 461system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) | 433system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution 435system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution 436system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 # Transaction distribution 437system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution 438system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) 439system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) 440system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 454system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 455system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 456system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram 457system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) 458system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 459system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) 460system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%) 461system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) |
| 462system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 463system.membus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states | 462system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) 463system.membus.snoop_filter.tot_requests 361 # Total number of requests made to the snoop filter. 464system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 465system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 466system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 467system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 468system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 469system.membus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states |
| 464system.membus.trans_dist::ReadResp 282 # Transaction distribution 465system.membus.trans_dist::ReadExReq 79 # Transaction distribution 466system.membus.trans_dist::ReadExResp 79 # Transaction distribution 467system.membus.trans_dist::ReadSharedReq 282 # Transaction distribution 468system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) 469system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) 470system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) 471system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) --- 20 unchanged lines hidden --- | 470system.membus.trans_dist::ReadResp 282 # Transaction distribution 471system.membus.trans_dist::ReadExReq 79 # Transaction distribution 472system.membus.trans_dist::ReadExResp 79 # Transaction distribution 473system.membus.trans_dist::ReadSharedReq 282 # Transaction distribution 474system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) 475system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) 476system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) 477system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) --- 20 unchanged lines hidden --- |