| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated 4sim_ticks 30886500 # Number of ticks simulated 5final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated 4sim_ticks 30886500 # Number of ticks simulated 5final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 324268 # Simulator instruction rate (inst/s) 8host_op_rate 586988 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1858658321 # Simulator tick rate (ticks/s) 10host_mem_usage 262968 # Number of bytes of host memory used | 7host_inst_rate 223066 # Simulator instruction rate (inst/s) 8host_op_rate 403939 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1279464733 # Simulator tick rate (ticks/s) 10host_mem_usage 309460 # Number of bytes of host memory used |
| 11host_seconds 0.02 # Real time elapsed on the host 12sim_insts 5381 # Number of instructions simulated 13sim_ops 9748 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.02 # Real time elapsed on the host 12sim_insts 5381 # Number of instructions simulated 13sim_ops 9748 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 18system.physmem.bytes_read::total 23104 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 361 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 470367313 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 277661762 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 748029074 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 470367313 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 470367313 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 470367313 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 277661762 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 748029074 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 19system.physmem.bytes_read::total 23104 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 361 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 470367313 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 277661762 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 748029074 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 470367313 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 470367313 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 470367313 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 277661762 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 748029074 # Total bandwidth to/from this memory (bytes/s) |
| 33system.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states |
|
| 32system.cpu_clk_domain.clock 500 # Clock period in ticks | 34system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 35system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states |
|
| 33system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 36system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 37system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states 38system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states |
|
| 34system.cpu.workload.num_syscalls 11 # Number of system calls | 39system.cpu.workload.num_syscalls 11 # Number of system calls |
| 40system.cpu.pwrStateResidencyTicks::ON 30886500 # Cumulative time (in ticks) in various power states |
|
| 35system.cpu.numCycles 61773 # number of cpu cycles simulated 36system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 37system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 38system.cpu.committedInsts 5381 # Number of instructions committed 39system.cpu.committedOps 9748 # Number of ops (including micro ops) committed 40system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses 41system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 42system.cpu.num_func_calls 209 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 87system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction 90system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction 91system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 9748 # Class of executed instruction | 41system.cpu.numCycles 61773 # number of cpu cycles simulated 42system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 44system.cpu.committedInsts 5381 # Number of instructions committed 45system.cpu.committedOps 9748 # Number of ops (including micro ops) committed 46system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses 47system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 48system.cpu.num_func_calls 209 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 93system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction 94system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction 95system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction 96system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction 97system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction 98system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 99system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::total 9748 # Class of executed instruction |
| 101system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states |
|
| 95system.cpu.dcache.tags.replacements 0 # number of replacements 96system.cpu.dcache.tags.tagsinuse 80.558239 # Cycle average of tags in use 97system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. 98system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. 99system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. 100system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 101system.cpu.dcache.tags.occ_blocks::cpu.data 80.558239 # Average occupied blocks per requestor 102system.cpu.dcache.tags.occ_percent::cpu.data 0.019668 # Average percentage of cache occupancy 103system.cpu.dcache.tags.occ_percent::total 0.019668 # Average percentage of cache occupancy 104system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 107system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id 108system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses 109system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses | 102system.cpu.dcache.tags.replacements 0 # number of replacements 103system.cpu.dcache.tags.tagsinuse 80.558239 # Cycle average of tags in use 104system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 108system.cpu.dcache.tags.occ_blocks::cpu.data 80.558239 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.019668 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.019668 # Average percentage of cache occupancy 111system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 114system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id 115system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses 116system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses |
| 117system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states |
|
| 110system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits 111system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits 112system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits 113system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits 114system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits 115system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits 116system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits 117system.cpu.dcache.overall_hits::total 1854 # number of overall hits --- 70 unchanged lines hidden (view full) --- 188system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 189system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 190system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 191system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 192system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 193system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 194system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 195system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency | 118system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits 119system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits 120system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits 121system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits 122system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits 123system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits 124system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits 125system.cpu.dcache.overall_hits::total 1854 # number of overall hits --- 70 unchanged lines hidden (view full) --- 196system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 197system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 198system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 199system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 200system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 201system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 202system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 203system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency |
| 204system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states |
|
| 196system.cpu.icache.tags.replacements 0 # number of replacements 197system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use 198system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. 199system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. 200system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. 201system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 202system.cpu.icache.tags.occ_blocks::cpu.inst 105.267613 # Average occupied blocks per requestor 203system.cpu.icache.tags.occ_percent::cpu.inst 0.051400 # Average percentage of cache occupancy 204system.cpu.icache.tags.occ_percent::total 0.051400 # Average percentage of cache occupancy 205system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id 206system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id 207system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id 208system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id 209system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses 210system.cpu.icache.tags.data_accesses 13956 # Number of data accesses | 205system.cpu.icache.tags.replacements 0 # number of replacements 206system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use 207system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. 208system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. 209system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. 210system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 211system.cpu.icache.tags.occ_blocks::cpu.inst 105.267613 # Average occupied blocks per requestor 212system.cpu.icache.tags.occ_percent::cpu.inst 0.051400 # Average percentage of cache occupancy 213system.cpu.icache.tags.occ_percent::total 0.051400 # Average percentage of cache occupancy 214system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id 215system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id 216system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id 217system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id 218system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses 219system.cpu.icache.tags.data_accesses 13956 # Number of data accesses |
| 220system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states |
|
| 211system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits 212system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits 213system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits 214system.cpu.icache.demand_hits::total 6636 # number of demand (read+write) hits 215system.cpu.icache.overall_hits::cpu.inst 6636 # number of overall hits 216system.cpu.icache.overall_hits::total 6636 # number of overall hits 217system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses 218system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses --- 50 unchanged lines hidden (view full) --- 269system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses 270system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses 271system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60791.666667 # average ReadReq mshr miss latency 272system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60791.666667 # average ReadReq mshr miss latency 273system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency 274system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency 275system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency 276system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency | 221system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits 222system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits 223system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits 224system.cpu.icache.demand_hits::total 6636 # number of demand (read+write) hits 225system.cpu.icache.overall_hits::cpu.inst 6636 # number of overall hits 226system.cpu.icache.overall_hits::total 6636 # number of overall hits 227system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses 228system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses --- 50 unchanged lines hidden (view full) --- 279system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses 280system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses 281system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60791.666667 # average ReadReq mshr miss latency 282system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60791.666667 # average ReadReq mshr miss latency 283system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency 284system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency 285system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency 286system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency |
| 287system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states |
|
| 277system.cpu.l2cache.tags.replacements 0 # number of replacements 278system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use 279system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 280system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. 281system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. 282system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 283system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.256135 # Average occupied blocks per requestor 284system.cpu.l2cache.tags.occ_blocks::cpu.data 28.415959 # Average occupied blocks per requestor 285system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003212 # Average percentage of cache occupancy 286system.cpu.l2cache.tags.occ_percent::cpu.data 0.000867 # Average percentage of cache occupancy 287system.cpu.l2cache.tags.occ_percent::total 0.004079 # Average percentage of cache occupancy 288system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id 289system.cpu.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 290system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id 291system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id 292system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses 293system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses | 288system.cpu.l2cache.tags.replacements 0 # number of replacements 289system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use 290system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 291system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. 292system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. 293system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 294system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.256135 # Average occupied blocks per requestor 295system.cpu.l2cache.tags.occ_blocks::cpu.data 28.415959 # Average occupied blocks per requestor 296system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003212 # Average percentage of cache occupancy 297system.cpu.l2cache.tags.occ_percent::cpu.data 0.000867 # Average percentage of cache occupancy 298system.cpu.l2cache.tags.occ_percent::total 0.004079 # Average percentage of cache occupancy 299system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id 300system.cpu.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 301system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id 302system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id 303system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses 304system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses |
| 305system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states |
|
| 294system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 295system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 296system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 297system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 298system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 299system.cpu.l2cache.overall_hits::total 1 # number of overall hits 300system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses 301system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses --- 110 unchanged lines hidden (view full) --- 412system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 413system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency 414system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. 415system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 416system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 417system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 418system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 419system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 306system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 307system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 308system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 309system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 310system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 311system.cpu.l2cache.overall_hits::total 1 # number of overall hits 312system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses 313system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses --- 110 unchanged lines hidden (view full) --- 424system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 425system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency 426system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. 427system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 428system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 429system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 430system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 431system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 432system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states |
|
| 420system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution 421system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution 422system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution 423system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 # Transaction distribution 424system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution 425system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) 426system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) 427system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 441system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 442system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram 443system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) 444system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 445system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) 446system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%) 447system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) 448system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) | 433system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution 435system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution 436system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 # Transaction distribution 437system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution 438system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) 439system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) 440system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 454system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 455system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram 456system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) 457system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 458system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) 459system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%) 460system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) 461system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) |
| 462system.membus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states |
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| 449system.membus.trans_dist::ReadResp 282 # Transaction distribution 450system.membus.trans_dist::ReadExReq 79 # Transaction distribution 451system.membus.trans_dist::ReadExResp 79 # Transaction distribution 452system.membus.trans_dist::ReadSharedReq 282 # Transaction distribution 453system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) 454system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) 455system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) 456system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) --- 19 unchanged lines hidden --- | 463system.membus.trans_dist::ReadResp 282 # Transaction distribution 464system.membus.trans_dist::ReadExReq 79 # Transaction distribution 465system.membus.trans_dist::ReadExResp 79 # Transaction distribution 466system.membus.trans_dist::ReadSharedReq 282 # Transaction distribution 467system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) 468system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) 469system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) 470system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) --- 19 unchanged lines hidden --- |