| stats.txt (11312:3d7a85d71bd1) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated 4sim_ticks 30886500 # Number of ticks simulated 5final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated 4sim_ticks 30886500 # Number of ticks simulated 5final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 79759 # Simulator instruction rate (inst/s) 8host_op_rate 144442 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 457524996 # Simulator tick rate (ticks/s) 10host_mem_usage 247116 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host | 7host_inst_rate 235920 # Simulator instruction rate (inst/s) 8host_op_rate 427054 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1352150005 # Simulator tick rate (ticks/s) 10host_mem_usage 266824 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host |
| 12sim_insts 5381 # Number of instructions simulated 13sim_ops 9748 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 18system.physmem.bytes_read::total 23104 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory --- 136 unchanged lines hidden (view full) --- 156system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency 157system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency 158system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 159system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 160system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 161system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 162system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 163system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 5381 # Number of instructions simulated 13sim_ops 9748 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 18system.physmem.bytes_read::total 23104 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory --- 136 unchanged lines hidden (view full) --- 156system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency 157system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency 158system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 159system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 160system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 161system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 162system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 163system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 164system.cpu.dcache.fast_writes 0 # number of fast writes performed 165system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 166system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 167system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 168system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses 169system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses 170system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 171system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses 172system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 173system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses --- 16 unchanged lines hidden (view full) --- 190system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 191system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 192system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 194system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 195system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 196system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 197system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency | 164system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 165system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 166system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses 167system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses 168system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 169system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses 170system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 171system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses --- 16 unchanged lines hidden (view full) --- 188system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 189system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 190system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 191system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 192system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 193system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 194system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 195system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency |
| 198system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 199system.cpu.icache.tags.replacements 0 # number of replacements 200system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use 201system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. 202system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. 203system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. 204system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 205system.cpu.icache.tags.occ_blocks::cpu.inst 105.267613 # Average occupied blocks per requestor 206system.cpu.icache.tags.occ_percent::cpu.inst 0.051400 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 248system.cpu.icache.overall_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency 249system.cpu.icache.overall_avg_miss_latency::total 61791.666667 # average overall miss latency 250system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 251system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 252system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 253system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 254system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 255system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 196system.cpu.icache.tags.replacements 0 # number of replacements 197system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use 198system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. 199system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. 200system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. 201system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 202system.cpu.icache.tags.occ_blocks::cpu.inst 105.267613 # Average occupied blocks per requestor 203system.cpu.icache.tags.occ_percent::cpu.inst 0.051400 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 245system.cpu.icache.overall_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency 246system.cpu.icache.overall_avg_miss_latency::total 61791.666667 # average overall miss latency 247system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 248system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 249system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 250system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 251system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 252system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 256system.cpu.icache.fast_writes 0 # number of fast writes performed 257system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 258system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses 259system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses 260system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses 261system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses 262system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses 263system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses 264system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13860500 # number of ReadReq MSHR miss cycles 265system.cpu.icache.ReadReq_mshr_miss_latency::total 13860500 # number of ReadReq MSHR miss cycles --- 8 unchanged lines hidden (view full) --- 274system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses 275system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses 276system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60791.666667 # average ReadReq mshr miss latency 277system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60791.666667 # average ReadReq mshr miss latency 278system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency 279system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency 280system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency 281system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency | 253system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses 254system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses 255system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses 256system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses 257system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses 258system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses 259system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13860500 # number of ReadReq MSHR miss cycles 260system.cpu.icache.ReadReq_mshr_miss_latency::total 13860500 # number of ReadReq MSHR miss cycles --- 8 unchanged lines hidden (view full) --- 269system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses 270system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses 271system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60791.666667 # average ReadReq mshr miss latency 272system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60791.666667 # average ReadReq mshr miss latency 273system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency 274system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency 275system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency 276system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency |
| 282system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 283system.cpu.l2cache.tags.replacements 0 # number of replacements 284system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use 285system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 286system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. 287system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. 288system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 289system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.256135 # Average occupied blocks per requestor 290system.cpu.l2cache.tags.occ_blocks::cpu.data 28.415959 # Average occupied blocks per requestor --- 73 unchanged lines hidden (view full) --- 364system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 365system.cpu.l2cache.overall_avg_miss_latency::total 59501.385042 # average overall miss latency 366system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 367system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 368system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 369system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 370system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 371system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 277system.cpu.l2cache.tags.replacements 0 # number of replacements 278system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use 279system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 280system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. 281system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. 282system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 283system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.256135 # Average occupied blocks per requestor 284system.cpu.l2cache.tags.occ_blocks::cpu.data 28.415959 # Average occupied blocks per requestor --- 73 unchanged lines hidden (view full) --- 358system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 359system.cpu.l2cache.overall_avg_miss_latency::total 59501.385042 # average overall miss latency 360system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 361system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 362system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 363system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 364system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 365system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 372system.cpu.l2cache.fast_writes 0 # number of fast writes performed 373system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 374system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses 375system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses 376system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 227 # number of ReadCleanReq MSHR misses 377system.cpu.l2cache.ReadCleanReq_mshr_misses::total 227 # number of ReadCleanReq MSHR misses 378system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 379system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses 380system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses 381system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 414system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 415system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 416system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency 417system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 418system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency 419system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency 420system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 421system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency | 366system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses 367system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses 368system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 227 # number of ReadCleanReq MSHR misses 369system.cpu.l2cache.ReadCleanReq_mshr_misses::total 227 # number of ReadCleanReq MSHR misses 370system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 371system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses 372system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses 373system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 406system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 407system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 408system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency 409system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 410system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency 411system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency 412system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 413system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency |
| 422system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 423system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. 424system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 425system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 426system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 427system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 428system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 429system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution 430system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution --- 54 unchanged lines hidden --- | 414system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. 415system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 416system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 417system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 418system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 419system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 420system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution 421system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution --- 54 unchanged lines hidden --- |