| stats.txt (10892:bd37e25fb3b7) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated |
| 4sim_ticks 28358500 # Number of ticks simulated 5final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 28359500 # Number of ticks simulated 5final_tick 28359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 304372 # Simulator instruction rate (inst/s) 8host_op_rate 550952 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1601632215 # Simulator tick rate (ticks/s) 10host_mem_usage 308112 # Number of bytes of host memory used | 7host_inst_rate 279983 # Simulator instruction rate (inst/s) 8host_op_rate 506758 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1473373857 # Simulator tick rate (ticks/s) 10host_mem_usage 311136 # Number of bytes of host memory used |
| 11host_seconds 0.02 # Real time elapsed on the host 12sim_insts 5381 # Number of instructions simulated 13sim_ops 9748 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 18system.physmem.bytes_read::total 23104 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 361 # Number of read requests responded to by this memory | 11host_seconds 0.02 # Real time elapsed on the host 12sim_insts 5381 # Number of instructions simulated 13sim_ops 9748 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 18system.physmem.bytes_read::total 23104 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 361 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 512297900 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 302413738 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 814711638 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 512297900 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 512297900 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 512297900 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 302413738 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 814711638 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 512279836 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 302403075 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 814682910 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 512279836 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 512279836 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 512279836 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 302403075 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 814682910 # Total bandwidth to/from this memory (bytes/s) |
| 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 34system.cpu.workload.num_syscalls 11 # Number of system calls | 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 34system.cpu.workload.num_syscalls 11 # Number of system calls |
| 35system.cpu.numCycles 56717 # number of cpu cycles simulated | 35system.cpu.numCycles 56719 # number of cpu cycles simulated |
| 36system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 37system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 38system.cpu.committedInsts 5381 # Number of instructions committed 39system.cpu.committedOps 9748 # Number of ops (including micro ops) committed 40system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses 41system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 42system.cpu.num_func_calls 209 # number of times a function call or return occured 43system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 48system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 49system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 50system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read 51system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written 52system.cpu.num_mem_refs 1988 # number of memory refs 53system.cpu.num_load_insts 1053 # Number of load instructions 54system.cpu.num_store_insts 935 # Number of store instructions 55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 36system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 37system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 38system.cpu.committedInsts 5381 # Number of instructions committed 39system.cpu.committedOps 9748 # Number of ops (including micro ops) committed 40system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses 41system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 42system.cpu.num_func_calls 209 # number of times a function call or return occured 43system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 48system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 49system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 50system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read 51system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written 52system.cpu.num_mem_refs 1988 # number of memory refs 53system.cpu.num_load_insts 1053 # Number of load instructions 54system.cpu.num_store_insts 935 # Number of store instructions 55system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 56system.cpu.num_busy_cycles 56716.998000 # Number of busy cycles | 56system.cpu.num_busy_cycles 56718.998000 # Number of busy cycles |
| 57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 59system.cpu.Branches 1208 # Number of branches fetched 60system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 61system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction 62system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction 63system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction 64system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction 90system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction 91system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 9748 # Class of executed instruction 95system.cpu.dcache.tags.replacements 0 # number of replacements | 57system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 58system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 59system.cpu.Branches 1208 # Number of branches fetched 60system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 61system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction 62system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction 63system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction 64system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 88system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction 89system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction 90system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction 91system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction 92system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 93system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 94system.cpu.op_class::total 9748 # Class of executed instruction 95system.cpu.dcache.tags.replacements 0 # number of replacements |
| 96system.cpu.dcache.tags.tagsinuse 80.791087 # Cycle average of tags in use | 96system.cpu.dcache.tags.tagsinuse 80.792611 # Cycle average of tags in use |
| 97system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. 98system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. 99system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. 100system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 97system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. 98system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. 99system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. 100system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 101system.cpu.dcache.tags.occ_blocks::cpu.data 80.791087 # Average occupied blocks per requestor 102system.cpu.dcache.tags.occ_percent::cpu.data 0.019724 # Average percentage of cache occupancy 103system.cpu.dcache.tags.occ_percent::total 0.019724 # Average percentage of cache occupancy | 101system.cpu.dcache.tags.occ_blocks::cpu.data 80.792611 # Average occupied blocks per requestor 102system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy 103system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy |
| 104system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id 107system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id 108system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses 109system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses 110system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits 111system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits --- 80 unchanged lines hidden (view full) --- 192system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency 193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency 194system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 195system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 196system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 197system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 198system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 199system.cpu.icache.tags.replacements 0 # number of replacements | 104system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id 105system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 106system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id 107system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id 108system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses 109system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses 110system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits 111system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits --- 80 unchanged lines hidden (view full) --- 192system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency 193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency 194system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 195system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 196system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 197system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 198system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 199system.cpu.icache.tags.replacements 0 # number of replacements |
| 200system.cpu.icache.tags.tagsinuse 105.540319 # Cycle average of tags in use | 200system.cpu.icache.tags.tagsinuse 105.543720 # Cycle average of tags in use |
| 201system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. 202system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. 203system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. 204system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 201system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. 202system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. 203system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. 204system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 205system.cpu.icache.tags.occ_blocks::cpu.inst 105.540319 # Average occupied blocks per requestor 206system.cpu.icache.tags.occ_percent::cpu.inst 0.051533 # Average percentage of cache occupancy 207system.cpu.icache.tags.occ_percent::total 0.051533 # Average percentage of cache occupancy | 205system.cpu.icache.tags.occ_blocks::cpu.inst 105.543720 # Average occupied blocks per requestor 206system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy 207system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy |
| 208system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id 209system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 210system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id 211system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id 212system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses 213system.cpu.icache.tags.data_accesses 13956 # Number of data accesses 214system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits 215system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits 216system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits 217system.cpu.icache.demand_hits::total 6636 # number of demand (read+write) hits 218system.cpu.icache.overall_hits::cpu.inst 6636 # number of overall hits 219system.cpu.icache.overall_hits::total 6636 # number of overall hits 220system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses 221system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses 222system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses 223system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses 224system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses 225system.cpu.icache.overall_misses::total 228 # number of overall misses | 208system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id 209system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 210system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id 211system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id 212system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses 213system.cpu.icache.tags.data_accesses 13956 # Number of data accesses 214system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits 215system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits 216system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits 217system.cpu.icache.demand_hits::total 6636 # number of demand (read+write) hits 218system.cpu.icache.overall_hits::cpu.inst 6636 # number of overall hits 219system.cpu.icache.overall_hits::total 6636 # number of overall hits 220system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses 221system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses 222system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses 223system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses 224system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses 225system.cpu.icache.overall_misses::total 228 # number of overall misses |
| 226system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498500 # number of ReadReq miss cycles 227system.cpu.icache.ReadReq_miss_latency::total 12498500 # number of ReadReq miss cycles 228system.cpu.icache.demand_miss_latency::cpu.inst 12498500 # number of demand (read+write) miss cycles 229system.cpu.icache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles 230system.cpu.icache.overall_miss_latency::cpu.inst 12498500 # number of overall miss cycles 231system.cpu.icache.overall_miss_latency::total 12498500 # number of overall miss cycles | 226system.cpu.icache.ReadReq_miss_latency::cpu.inst 12499500 # number of ReadReq miss cycles 227system.cpu.icache.ReadReq_miss_latency::total 12499500 # number of ReadReq miss cycles 228system.cpu.icache.demand_miss_latency::cpu.inst 12499500 # number of demand (read+write) miss cycles 229system.cpu.icache.demand_miss_latency::total 12499500 # number of demand (read+write) miss cycles 230system.cpu.icache.overall_miss_latency::cpu.inst 12499500 # number of overall miss cycles 231system.cpu.icache.overall_miss_latency::total 12499500 # number of overall miss cycles |
| 232system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) 233system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) 234system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses 235system.cpu.icache.demand_accesses::total 6864 # number of demand (read+write) accesses 236system.cpu.icache.overall_accesses::cpu.inst 6864 # number of overall (read+write) accesses 237system.cpu.icache.overall_accesses::total 6864 # number of overall (read+write) accesses 238system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033217 # miss rate for ReadReq accesses 239system.cpu.icache.ReadReq_miss_rate::total 0.033217 # miss rate for ReadReq accesses 240system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 # miss rate for demand accesses 241system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses 242system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses 243system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses | 232system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) 233system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) 234system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses 235system.cpu.icache.demand_accesses::total 6864 # number of demand (read+write) accesses 236system.cpu.icache.overall_accesses::cpu.inst 6864 # number of overall (read+write) accesses 237system.cpu.icache.overall_accesses::total 6864 # number of overall (read+write) accesses 238system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033217 # miss rate for ReadReq accesses 239system.cpu.icache.ReadReq_miss_rate::total 0.033217 # miss rate for ReadReq accesses 240system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 # miss rate for demand accesses 241system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses 242system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses 243system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses |
| 244system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54817.982456 # average ReadReq miss latency 245system.cpu.icache.ReadReq_avg_miss_latency::total 54817.982456 # average ReadReq miss latency 246system.cpu.icache.demand_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency 247system.cpu.icache.demand_avg_miss_latency::total 54817.982456 # average overall miss latency 248system.cpu.icache.overall_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency 249system.cpu.icache.overall_avg_miss_latency::total 54817.982456 # average overall miss latency | 244system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54822.368421 # average ReadReq miss latency 245system.cpu.icache.ReadReq_avg_miss_latency::total 54822.368421 # average ReadReq miss latency 246system.cpu.icache.demand_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency 247system.cpu.icache.demand_avg_miss_latency::total 54822.368421 # average overall miss latency 248system.cpu.icache.overall_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency 249system.cpu.icache.overall_avg_miss_latency::total 54822.368421 # average overall miss latency |
| 250system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 251system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 252system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 253system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 254system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 255system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 256system.cpu.icache.fast_writes 0 # number of fast writes performed 257system.cpu.icache.cache_copies 0 # number of cache copies performed 258system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses 259system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses 260system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses 261system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses 262system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses 263system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses | 250system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 251system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 252system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 253system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 254system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 255system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 256system.cpu.icache.fast_writes 0 # number of fast writes performed 257system.cpu.icache.cache_copies 0 # number of cache copies performed 258system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses 259system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses 260system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses 261system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses 262system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses 263system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses |
| 264system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12270500 # number of ReadReq MSHR miss cycles 265system.cpu.icache.ReadReq_mshr_miss_latency::total 12270500 # number of ReadReq MSHR miss cycles 266system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12270500 # number of demand (read+write) MSHR miss cycles 267system.cpu.icache.demand_mshr_miss_latency::total 12270500 # number of demand (read+write) MSHR miss cycles 268system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12270500 # number of overall MSHR miss cycles 269system.cpu.icache.overall_mshr_miss_latency::total 12270500 # number of overall MSHR miss cycles | 264system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12271500 # number of ReadReq MSHR miss cycles 265system.cpu.icache.ReadReq_mshr_miss_latency::total 12271500 # number of ReadReq MSHR miss cycles 266system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12271500 # number of demand (read+write) MSHR miss cycles 267system.cpu.icache.demand_mshr_miss_latency::total 12271500 # number of demand (read+write) MSHR miss cycles 268system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12271500 # number of overall MSHR miss cycles 269system.cpu.icache.overall_mshr_miss_latency::total 12271500 # number of overall MSHR miss cycles |
| 270system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses 271system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses 272system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses 273system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses 274system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses 275system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses | 270system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses 271system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses 272system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses 273system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses 274system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses 275system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses |
| 276system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53817.982456 # average ReadReq mshr miss latency 277system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53817.982456 # average ReadReq mshr miss latency 278system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53817.982456 # average overall mshr miss latency 279system.cpu.icache.demand_avg_mshr_miss_latency::total 53817.982456 # average overall mshr miss latency 280system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53817.982456 # average overall mshr miss latency 281system.cpu.icache.overall_avg_mshr_miss_latency::total 53817.982456 # average overall mshr miss latency | 276system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53822.368421 # average ReadReq mshr miss latency 277system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53822.368421 # average ReadReq mshr miss latency 278system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency 279system.cpu.icache.demand_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency 280system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency 281system.cpu.icache.overall_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency |
| 282system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 283system.cpu.l2cache.tags.replacements 0 # number of replacements | 282system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 283system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 284system.cpu.l2cache.tags.tagsinuse 134.006917 # Cycle average of tags in use | 284system.cpu.l2cache.tags.tagsinuse 134.010901 # Cycle average of tags in use |
| 285system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 286system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. 287system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. 288system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 285system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 286system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. 287system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. 288system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 289system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.536457 # Average occupied blocks per requestor 290system.cpu.l2cache.tags.occ_blocks::cpu.data 28.470460 # Average occupied blocks per requestor | 289system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.539859 # Average occupied blocks per requestor 290system.cpu.l2cache.tags.occ_blocks::cpu.data 28.471042 # Average occupied blocks per requestor |
| 291system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy 292system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy 293system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy 294system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id 295system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id 296system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id 297system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id 298system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses --- 116 unchanged lines hidden (view full) --- 415system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 416system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.202643 # average overall mshr miss latency 417system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 418system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency 419system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.202643 # average overall mshr miss latency 420system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 421system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency 422system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 291system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy 292system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy 293system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy 294system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id 295system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id 296system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id 297system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id 298system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses --- 116 unchanged lines hidden (view full) --- 415system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 416system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.202643 # average overall mshr miss latency 417system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 418system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency 419system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.202643 # average overall mshr miss latency 420system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 421system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency 422system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 423system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. 424system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 425system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 426system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 427system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 428system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 423system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution 424system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution 425system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution 426system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 # Transaction distribution 427system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution 428system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) 429system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) 430system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) 431system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes) 432system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes) 433system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) 434system.cpu.toL2Bus.snoops 0 # Total snoops (count) 435system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram | 429system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution 430system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution 431system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution 432system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 # Transaction distribution 433system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution 434system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) 435system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) 436system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) 437system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes) 438system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes) 439system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) 440system.cpu.toL2Bus.snoops 0 # Total snoops (count) 441system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram |
| 436system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 437system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 442system.cpu.toL2Bus.snoop_fanout::mean 0.002762 # Request fanout histogram 443system.cpu.toL2Bus.snoop_fanout::stdev 0.052559 # Request fanout histogram |
| 438system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 444system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 439system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 440system.cpu.toL2Bus.snoop_fanout::1 362 100.00% 100.00% # Request fanout histogram | 445system.cpu.toL2Bus.snoop_fanout::0 361 99.72% 99.72% # Request fanout histogram 446system.cpu.toL2Bus.snoop_fanout::1 1 0.28% 100.00% # Request fanout histogram |
| 441system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 442system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 447system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 448system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 443system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 449system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 444system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 445system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram 446system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) 447system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 448system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) 449system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) 450system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) 451system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) --- 27 unchanged lines hidden --- | 450system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 451system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram 452system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) 453system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 454system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) 455system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) 456system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) 457system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) --- 27 unchanged lines hidden --- |