4,5c4,5
< sim_ticks 30886500 # Number of ticks simulated
< final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 31247500 # Number of ticks simulated
> final_tick 31247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 211795 # Simulator instruction rate (inst/s)
< host_op_rate 383429 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1214135841 # Simulator tick rate (ticks/s)
< host_mem_usage 263924 # Number of bytes of host memory used
< host_seconds 0.03 # Real time elapsed on the host
---
> host_inst_rate 85405 # Simulator instruction rate (inst/s)
> host_op_rate 154687 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 495766938 # Simulator tick rate (ticks/s)
> host_mem_usage 269328 # Number of bytes of host memory used
> host_seconds 0.06 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 470367313 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 277661762 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 748029074 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 470367313 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 470367313 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 470367313 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 277661762 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 748029074 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 464933195 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 274453956 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 739387151 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 464933195 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 464933195 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 464933195 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 274453956 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 739387151 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
35c35
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
37,38c37,38
< system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
40,41c40,41
< system.cpu.pwrStateResidencyTicks::ON 30886500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 61773 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 31247500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 62495 # number of cpu cycles simulated
62c62
< system.cpu.num_busy_cycles 61772.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 62494.998000 # Number of busy cycles
101c101
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
103c103
< system.cpu.dcache.tags.tagsinuse 80.558239 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 80.527852 # Cycle average of tags in use
108,110c108,110
< system.cpu.dcache.tags.occ_blocks::cpu.data 80.558239 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.019668 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.019668 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 80.527852 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.019660 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.019660 # Average percentage of cache occupancy
117c117
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
134,141c134,141
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4898000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4898000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 8308000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 8308000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 8308000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 8308000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4977000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4977000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 8442000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 8442000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 8442000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 8442000 # number of overall miss cycles
158,165c158,165
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
180,187c180,187
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4819000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4819000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8174000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8174000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8174000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8174000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4898000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4898000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8308000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8308000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8308000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8308000 # number of overall MSHR miss cycles
196,204c196,204
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
206c206
< system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 105.231814 # Cycle average of tags in use
211,213c211,213
< system.cpu.icache.tags.occ_blocks::cpu.inst 105.267613 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.051400 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.051400 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 105.231814 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.051383 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.051383 # Average percentage of cache occupancy
215,216c215,216
< system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
220c220
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
233,238c233,238
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 14088500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 14088500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 14088500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 14088500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 14088500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 14088500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 14315500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 14315500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 14315500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 14315500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 14315500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 14315500 # number of overall miss cycles
251,256c251,256
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61791.666667 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 61791.666667 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 61791.666667 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 61791.666667 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62787.280702 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 62787.280702 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 62787.280702 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 62787.280702 # average overall miss latency
269,274c269,274
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13860500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 13860500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13860500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 13860500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13860500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 13860500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14087500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 14087500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14087500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 14087500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14087500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 14087500 # number of overall MSHR miss cycles
281,287c281,287
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60791.666667 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60791.666667 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61787.280702 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61787.280702 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
289c289
< system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 185.792229 # Cycle average of tags in use
291,292c291,292
< system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 361 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.002770 # Average number of references to valid blocks.
294,302c294,302
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.256135 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 28.415959 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003212 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.000867 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.004079 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.219349 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 80.572880 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003211 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002459 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.005670 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011017 # Percentage of cache occupancy per task id
305c305
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
324,335c324,335
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4700500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4700500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13507000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 13507000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 13507000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 21480000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 13507000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 21480000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4779500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4779500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13734000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 13734000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 13734000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 21841000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 13734000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 21841000 # number of overall miss cycles
360,371c360,371
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59502.202643 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59502.202643 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59501.385042 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59501.385042 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.202643 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.202643 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60501.385042 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60501.385042 # average overall miss latency
390,401c390,401
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3910500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3910500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11237000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11237000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11237000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 17870000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11237000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 17870000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3989500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3989500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11464000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11464000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2777500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2777500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11464000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 18231000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11464000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 18231000 # number of overall MSHR miss cycles
414,425c414,425
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49502.202643 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49502.202643 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.202643 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.202643 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency
432c432
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
462,463c462,469
< system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
< system.membus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
> system.membus.snoop_filter.tot_requests 361 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
< sim_ticks 30886500 # Number of ticks simulated
< final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 31247500 # Number of ticks simulated
> final_tick 31247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 211795 # Simulator instruction rate (inst/s)
< host_op_rate 383429 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1214135841 # Simulator tick rate (ticks/s)
< host_mem_usage 263924 # Number of bytes of host memory used
< host_seconds 0.03 # Real time elapsed on the host
---
> host_inst_rate 85405 # Simulator instruction rate (inst/s)
> host_op_rate 154687 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 495766938 # Simulator tick rate (ticks/s)
> host_mem_usage 269328 # Number of bytes of host memory used
> host_seconds 0.06 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 470367313 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 277661762 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 748029074 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 470367313 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 470367313 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 470367313 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 277661762 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 748029074 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 464933195 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 274453956 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 739387151 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 464933195 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 464933195 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 464933195 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 274453956 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 739387151 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
35c35
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
37,38c37,38
< system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
40,41c40,41
< system.cpu.pwrStateResidencyTicks::ON 30886500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 61773 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 31247500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 62495 # number of cpu cycles simulated
62c62
< system.cpu.num_busy_cycles 61772.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 62494.998000 # Number of busy cycles
101c101
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
103c103
< system.cpu.dcache.tags.tagsinuse 80.558239 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 80.527852 # Cycle average of tags in use
108,110c108,110
< system.cpu.dcache.tags.occ_blocks::cpu.data 80.558239 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.019668 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.019668 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 80.527852 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.019660 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.019660 # Average percentage of cache occupancy
117c117
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
134,141c134,141
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4898000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4898000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 8308000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 8308000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 8308000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 8308000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4977000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4977000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 8442000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 8442000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 8442000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 8442000 # number of overall miss cycles
158,165c158,165
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
180,187c180,187
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4819000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4819000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8174000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8174000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8174000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8174000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4898000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4898000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8308000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8308000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8308000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8308000 # number of overall MSHR miss cycles
196,204c196,204
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
206c206
< system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 105.231814 # Cycle average of tags in use
211,213c211,213
< system.cpu.icache.tags.occ_blocks::cpu.inst 105.267613 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.051400 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.051400 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 105.231814 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.051383 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.051383 # Average percentage of cache occupancy
215,216c215,216
< system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
220c220
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
233,238c233,238
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 14088500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 14088500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 14088500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 14088500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 14088500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 14088500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 14315500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 14315500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 14315500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 14315500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 14315500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 14315500 # number of overall miss cycles
251,256c251,256
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61791.666667 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 61791.666667 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 61791.666667 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 61791.666667 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62787.280702 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 62787.280702 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 62787.280702 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 62787.280702 # average overall miss latency
269,274c269,274
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13860500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 13860500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13860500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 13860500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13860500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 13860500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14087500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 14087500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14087500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 14087500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14087500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 14087500 # number of overall MSHR miss cycles
281,287c281,287
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60791.666667 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60791.666667 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61787.280702 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61787.280702 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
289c289
< system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 185.792229 # Cycle average of tags in use
291,292c291,292
< system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 361 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.002770 # Average number of references to valid blocks.
294,302c294,302
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.256135 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 28.415959 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003212 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.000867 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.004079 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.219349 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 80.572880 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003211 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002459 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.005670 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011017 # Percentage of cache occupancy per task id
305c305
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
324,335c324,335
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4700500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4700500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13507000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 13507000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 13507000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 21480000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 13507000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 21480000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4779500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4779500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13734000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 13734000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 13734000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 21841000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 13734000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 21841000 # number of overall miss cycles
360,371c360,371
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59502.202643 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59502.202643 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59501.385042 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59501.385042 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.202643 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.202643 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60501.385042 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60501.385042 # average overall miss latency
390,401c390,401
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3910500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3910500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11237000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11237000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11237000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 17870000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11237000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 17870000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3989500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3989500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11464000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11464000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2777500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2777500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11464000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 18231000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11464000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 18231000 # number of overall MSHR miss cycles
414,425c414,425
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49502.202643 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49502.202643 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.202643 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.202643 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency
432c432
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states
462,463c462,469
< system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
< system.membus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
> system.membus.snoop_filter.tot_requests 361 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states