4,5c4,5
< sim_ticks 28358000 # Number of ticks simulated
< final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 28358500 # Number of ticks simulated
> final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 307468 # Simulator instruction rate (inst/s)
< host_op_rate 556583 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1618053178 # Simulator tick rate (ticks/s)
< host_mem_usage 302528 # Number of bytes of host memory used
---
> host_inst_rate 312703 # Simulator instruction rate (inst/s)
> host_op_rate 566020 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1645401799 # Simulator tick rate (ticks/s)
> host_mem_usage 307640 # Number of bytes of host memory used
24,56c24,31
< system.physmem.bw_read::cpu.inst 512306933 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 302419070 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 814726003 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 512306933 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 512306933 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s)
< system.membus.trans_dist::ReadReq 282 # Transaction distribution
< system.membus.trans_dist::ReadResp 282 # Transaction distribution
< system.membus.trans_dist::ReadExReq 79 # Transaction distribution
< system.membus.trans_dist::ReadExResp 79 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 361 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 361 # Request fanout histogram
< system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 11.5 # Layer utilization (%)
---
> system.physmem.bw_read::cpu.inst 512297900 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 302413738 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 814711638 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 512297900 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 512297900 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 512297900 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 302413738 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 814711638 # Total bandwidth to/from this memory (bytes/s)
60c35
< system.cpu.numCycles 56716 # number of cpu cycles simulated
---
> system.cpu.numCycles 56717 # number of cpu cycles simulated
81c56
< system.cpu.num_busy_cycles 56715.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 56716.998000 # Number of busy cycles
119a95,198
> system.cpu.dcache.tags.replacements 0 # number of replacements
> system.cpu.dcache.tags.tagsinuse 80.793450 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 80.793450 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits
> system.cpu.dcache.overall_hits::total 1854 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
> system.cpu.dcache.overall_misses::total 134 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4226500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4226500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7169000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7169000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7169000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7169000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
121c200
< system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 105.544338 # Cycle average of tags in use
126,128c205,207
< system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 105.544338 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy
147,152c226,231
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 12498000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 12498000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 12498500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 12498500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 12498500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 12498500 # number of overall miss cycles
165,170c244,249
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 54815.789474 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 54815.789474 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54817.982456 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54817.982456 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54817.982456 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54817.982456 # average overall miss latency
185,190c264,269
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12156500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 12156500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12156500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 12156500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12156500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 12156500 # number of overall MSHR miss cycles
197,202c276,281
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53317.982456 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53317.982456 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53317.982456 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53317.982456 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53317.982456 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53317.982456 # average overall mshr miss latency
205c284
< system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 134.026823 # Cycle average of tags in use
210,211c289,290
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.552484 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 28.474338 # Average occupied blocks per requestor
238,248c317,327
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11918000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 14805500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4147500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4147500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 11918000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 18953000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 11918000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 18953000 # number of overall miss cycles
271,281c350,360
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.202643 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.773050 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52501.385042 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52501.385042 # average overall miss latency
301,311c380,390
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9193500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11421000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3199500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3199500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9193500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 14620500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9193500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 14620500 # number of overall MSHR miss cycles
323,333c402,412
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
335,438d413
< system.cpu.dcache.tags.replacements 0 # number of replacements
< system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits
< system.cpu.dcache.overall_hits::total 1854 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
< system.cpu.dcache.overall_misses::total 134 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
468a444,468
> system.membus.trans_dist::ReadReq 282 # Transaction distribution
> system.membus.trans_dist::ReadResp 282 # Transaction distribution
> system.membus.trans_dist::ReadExReq 79 # Transaction distribution
> system.membus.trans_dist::ReadExResp 79 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 361 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 361 # Request fanout histogram
> system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
> system.membus.respLayer1.occupancy 1805500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 6.4 # Layer utilization (%)
< sim_ticks 28358000 # Number of ticks simulated
< final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 28358500 # Number of ticks simulated
> final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 307468 # Simulator instruction rate (inst/s)
< host_op_rate 556583 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1618053178 # Simulator tick rate (ticks/s)
< host_mem_usage 302528 # Number of bytes of host memory used
---
> host_inst_rate 312703 # Simulator instruction rate (inst/s)
> host_op_rate 566020 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1645401799 # Simulator tick rate (ticks/s)
> host_mem_usage 307640 # Number of bytes of host memory used
24,56c24,31
< system.physmem.bw_read::cpu.inst 512306933 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 302419070 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 814726003 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 512306933 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 512306933 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s)
< system.membus.trans_dist::ReadReq 282 # Transaction distribution
< system.membus.trans_dist::ReadResp 282 # Transaction distribution
< system.membus.trans_dist::ReadExReq 79 # Transaction distribution
< system.membus.trans_dist::ReadExResp 79 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 361 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 361 # Request fanout histogram
< system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 11.5 # Layer utilization (%)
---
> system.physmem.bw_read::cpu.inst 512297900 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 302413738 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 814711638 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 512297900 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 512297900 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 512297900 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 302413738 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 814711638 # Total bandwidth to/from this memory (bytes/s)
60c35
< system.cpu.numCycles 56716 # number of cpu cycles simulated
---
> system.cpu.numCycles 56717 # number of cpu cycles simulated
81c56
< system.cpu.num_busy_cycles 56715.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 56716.998000 # Number of busy cycles
119a95,198
> system.cpu.dcache.tags.replacements 0 # number of replacements
> system.cpu.dcache.tags.tagsinuse 80.793450 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 80.793450 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits
> system.cpu.dcache.overall_hits::total 1854 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
> system.cpu.dcache.overall_misses::total 134 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4226500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4226500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7169000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7169000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7169000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7169000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
121c200
< system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 105.544338 # Cycle average of tags in use
126,128c205,207
< system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 105.544338 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy
147,152c226,231
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 12498000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 12498000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 12498500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 12498500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 12498500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 12498500 # number of overall miss cycles
165,170c244,249
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 54815.789474 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 54815.789474 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54817.982456 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54817.982456 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54817.982456 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54817.982456 # average overall miss latency
185,190c264,269
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12156500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 12156500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12156500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 12156500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12156500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 12156500 # number of overall MSHR miss cycles
197,202c276,281
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53317.982456 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53317.982456 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53317.982456 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53317.982456 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53317.982456 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53317.982456 # average overall mshr miss latency
205c284
< system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 134.026823 # Cycle average of tags in use
210,211c289,290
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.552484 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 28.474338 # Average occupied blocks per requestor
238,248c317,327
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11918000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 14805500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4147500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4147500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 11918000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 18953000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 11918000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 18953000 # number of overall miss cycles
271,281c350,360
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.202643 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.773050 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52501.385042 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52501.385042 # average overall miss latency
301,311c380,390
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9193500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11421000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3199500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3199500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9193500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 14620500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9193500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 14620500 # number of overall MSHR miss cycles
323,333c402,412
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
335,438d413
< system.cpu.dcache.tags.replacements 0 # number of replacements
< system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits
< system.cpu.dcache.overall_hits::total 1854 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
< system.cpu.dcache.overall_misses::total 134 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
468a444,468
> system.membus.trans_dist::ReadReq 282 # Transaction distribution
> system.membus.trans_dist::ReadResp 282 # Transaction distribution
> system.membus.trans_dist::ReadExReq 79 # Transaction distribution
> system.membus.trans_dist::ReadExResp 79 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 361 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 361 # Request fanout histogram
> system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
> system.membus.respLayer1.occupancy 1805500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 6.4 # Layer utilization (%)