1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000030 # Number of seconds simulated
4sim_ticks 29676000 # Number of ticks simulated
5final_tick 29676000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000030 # Number of seconds simulated
4sim_ticks 29676000 # Number of ticks simulated
5final_tick 29676000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 192246 # Simulator instruction rate (inst/s)
8host_op_rate 347982 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1058982197 # Simulator tick rate (ticks/s)
10host_mem_usage 231200 # Number of bytes of host memory used
11host_seconds 0.03 # Real time elapsed on the host
| 7host_inst_rate 72347 # Simulator instruction rate (inst/s)
8host_op_rate 131001 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 398795084 # Simulator tick rate (ticks/s)
10host_mem_usage 269536 # Number of bytes of host memory used
11host_seconds 0.07 # Real time elapsed on the host
|
12sim_insts 5381 # Number of instructions simulated
13sim_ops 9746 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
16system.physmem.bytes_read::total 23104 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 361 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 489553848 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 288987734 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 778541582 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 489553848 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 489553848 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 489553848 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 288987734 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 778541582 # Total bandwidth to/from this memory (bytes/s)
30system.cpu.workload.num_syscalls 11 # Number of system calls
31system.cpu.numCycles 59352 # number of cpu cycles simulated
32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
34system.cpu.committedInsts 5381 # Number of instructions committed
35system.cpu.committedOps 9746 # Number of ops (including micro ops) committed
36system.cpu.num_int_alu_accesses 9651 # Number of integer alu accesses
37system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
38system.cpu.num_func_calls 0 # number of times a function call or return occured
39system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
40system.cpu.num_int_insts 9651 # number of integer instructions
41system.cpu.num_fp_insts 0 # number of float instructions
| 12sim_insts 5381 # Number of instructions simulated
13sim_ops 9746 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
16system.physmem.bytes_read::total 23104 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 361 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 489553848 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 288987734 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 778541582 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 489553848 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 489553848 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 489553848 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 288987734 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 778541582 # Total bandwidth to/from this memory (bytes/s)
30system.cpu.workload.num_syscalls 11 # Number of system calls
31system.cpu.numCycles 59352 # number of cpu cycles simulated
32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
34system.cpu.committedInsts 5381 # Number of instructions committed
35system.cpu.committedOps 9746 # Number of ops (including micro ops) committed
36system.cpu.num_int_alu_accesses 9651 # Number of integer alu accesses
37system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
38system.cpu.num_func_calls 0 # number of times a function call or return occured
39system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
40system.cpu.num_int_insts 9651 # number of integer instructions
41system.cpu.num_fp_insts 0 # number of float instructions
|
42system.cpu.num_int_register_reads 29744 # number of times the integer registers were read
43system.cpu.num_int_register_writes 14595 # number of times the integer registers were written
| 42system.cpu.num_int_register_reads 24812 # number of times the integer registers were read
43system.cpu.num_int_register_writes 11060 # number of times the integer registers were written
|
44system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
45system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
46system.cpu.num_mem_refs 1986 # number of memory refs
47system.cpu.num_load_insts 1052 # Number of load instructions
48system.cpu.num_store_insts 934 # Number of store instructions
49system.cpu.num_idle_cycles 0 # Number of idle cycles
50system.cpu.num_busy_cycles 59352 # Number of busy cycles
51system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
52system.cpu.idle_fraction 0 # Percentage of idle cycles
53system.cpu.icache.replacements 0 # number of replacements
54system.cpu.icache.tagsinuse 105.746399 # Cycle average of tags in use
55system.cpu.icache.total_refs 6637 # Total number of references to valid blocks.
56system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
57system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks.
58system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
59system.cpu.icache.occ_blocks::cpu.inst 105.746399 # Average occupied blocks per requestor
60system.cpu.icache.occ_percent::cpu.inst 0.051634 # Average percentage of cache occupancy
61system.cpu.icache.occ_percent::total 0.051634 # Average percentage of cache occupancy
62system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits
63system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits
64system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits
65system.cpu.icache.demand_hits::total 6637 # number of demand (read+write) hits
66system.cpu.icache.overall_hits::cpu.inst 6637 # number of overall hits
67system.cpu.icache.overall_hits::total 6637 # number of overall hits
68system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses
69system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses
70system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses
71system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses
72system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses
73system.cpu.icache.overall_misses::total 228 # number of overall misses
74system.cpu.icache.ReadReq_miss_latency::cpu.inst 12726000 # number of ReadReq miss cycles
75system.cpu.icache.ReadReq_miss_latency::total 12726000 # number of ReadReq miss cycles
76system.cpu.icache.demand_miss_latency::cpu.inst 12726000 # number of demand (read+write) miss cycles
77system.cpu.icache.demand_miss_latency::total 12726000 # number of demand (read+write) miss cycles
78system.cpu.icache.overall_miss_latency::cpu.inst 12726000 # number of overall miss cycles
79system.cpu.icache.overall_miss_latency::total 12726000 # number of overall miss cycles
80system.cpu.icache.ReadReq_accesses::cpu.inst 6865 # number of ReadReq accesses(hits+misses)
81system.cpu.icache.ReadReq_accesses::total 6865 # number of ReadReq accesses(hits+misses)
82system.cpu.icache.demand_accesses::cpu.inst 6865 # number of demand (read+write) accesses
83system.cpu.icache.demand_accesses::total 6865 # number of demand (read+write) accesses
84system.cpu.icache.overall_accesses::cpu.inst 6865 # number of overall (read+write) accesses
85system.cpu.icache.overall_accesses::total 6865 # number of overall (read+write) accesses
86system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033212 # miss rate for ReadReq accesses
87system.cpu.icache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses
88system.cpu.icache.demand_miss_rate::cpu.inst 0.033212 # miss rate for demand accesses
89system.cpu.icache.demand_miss_rate::total 0.033212 # miss rate for demand accesses
90system.cpu.icache.overall_miss_rate::cpu.inst 0.033212 # miss rate for overall accesses
91system.cpu.icache.overall_miss_rate::total 0.033212 # miss rate for overall accesses
92system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474 # average ReadReq miss latency
93system.cpu.icache.ReadReq_avg_miss_latency::total 55815.789474 # average ReadReq miss latency
94system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency
95system.cpu.icache.demand_avg_miss_latency::total 55815.789474 # average overall miss latency
96system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency
97system.cpu.icache.overall_avg_miss_latency::total 55815.789474 # average overall miss latency
98system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
99system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
100system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
101system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
102system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
103system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
104system.cpu.icache.fast_writes 0 # number of fast writes performed
105system.cpu.icache.cache_copies 0 # number of cache copies performed
106system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses
107system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
108system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses
109system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
110system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses
111system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses
112system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles
113system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles
114system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles
115system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles
116system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles
117system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles
118system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for ReadReq accesses
119system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033212 # mshr miss rate for ReadReq accesses
120system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for demand accesses
121system.cpu.icache.demand_mshr_miss_rate::total 0.033212 # mshr miss rate for demand accesses
122system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for overall accesses
123system.cpu.icache.overall_mshr_miss_rate::total 0.033212 # mshr miss rate for overall accesses
124system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency
125system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency
126system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
127system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
128system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
129system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
130system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
131system.cpu.dcache.replacements 0 # number of replacements
132system.cpu.dcache.tagsinuse 80.866493 # Cycle average of tags in use
133system.cpu.dcache.total_refs 1852 # Total number of references to valid blocks.
134system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
135system.cpu.dcache.avg_refs 13.820896 # Average number of references to valid blocks.
136system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
137system.cpu.dcache.occ_blocks::cpu.data 80.866493 # Average occupied blocks per requestor
138system.cpu.dcache.occ_percent::cpu.data 0.019743 # Average percentage of cache occupancy
139system.cpu.dcache.occ_percent::total 0.019743 # Average percentage of cache occupancy
140system.cpu.dcache.ReadReq_hits::cpu.data 997 # number of ReadReq hits
141system.cpu.dcache.ReadReq_hits::total 997 # number of ReadReq hits
142system.cpu.dcache.WriteReq_hits::cpu.data 855 # number of WriteReq hits
143system.cpu.dcache.WriteReq_hits::total 855 # number of WriteReq hits
144system.cpu.dcache.demand_hits::cpu.data 1852 # number of demand (read+write) hits
145system.cpu.dcache.demand_hits::total 1852 # number of demand (read+write) hits
146system.cpu.dcache.overall_hits::cpu.data 1852 # number of overall hits
147system.cpu.dcache.overall_hits::total 1852 # number of overall hits
148system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
149system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
150system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
151system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
152system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
153system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
154system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
155system.cpu.dcache.overall_misses::total 134 # number of overall misses
156system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles
157system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles
158system.cpu.dcache.WriteReq_miss_latency::cpu.data 4424000 # number of WriteReq miss cycles
159system.cpu.dcache.WriteReq_miss_latency::total 4424000 # number of WriteReq miss cycles
160system.cpu.dcache.demand_miss_latency::cpu.data 7504000 # number of demand (read+write) miss cycles
161system.cpu.dcache.demand_miss_latency::total 7504000 # number of demand (read+write) miss cycles
162system.cpu.dcache.overall_miss_latency::cpu.data 7504000 # number of overall miss cycles
163system.cpu.dcache.overall_miss_latency::total 7504000 # number of overall miss cycles
164system.cpu.dcache.ReadReq_accesses::cpu.data 1052 # number of ReadReq accesses(hits+misses)
165system.cpu.dcache.ReadReq_accesses::total 1052 # number of ReadReq accesses(hits+misses)
166system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
167system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
168system.cpu.dcache.demand_accesses::cpu.data 1986 # number of demand (read+write) accesses
169system.cpu.dcache.demand_accesses::total 1986 # number of demand (read+write) accesses
170system.cpu.dcache.overall_accesses::cpu.data 1986 # number of overall (read+write) accesses
171system.cpu.dcache.overall_accesses::total 1986 # number of overall (read+write) accesses
172system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052281 # miss rate for ReadReq accesses
173system.cpu.dcache.ReadReq_miss_rate::total 0.052281 # miss rate for ReadReq accesses
174system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084582 # miss rate for WriteReq accesses
175system.cpu.dcache.WriteReq_miss_rate::total 0.084582 # miss rate for WriteReq accesses
176system.cpu.dcache.demand_miss_rate::cpu.data 0.067472 # miss rate for demand accesses
177system.cpu.dcache.demand_miss_rate::total 0.067472 # miss rate for demand accesses
178system.cpu.dcache.overall_miss_rate::cpu.data 0.067472 # miss rate for overall accesses
179system.cpu.dcache.overall_miss_rate::total 0.067472 # miss rate for overall accesses
180system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
181system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
182system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
183system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
184system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
185system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
186system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
187system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
188system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
189system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
190system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
191system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
192system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
193system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
194system.cpu.dcache.fast_writes 0 # number of fast writes performed
195system.cpu.dcache.cache_copies 0 # number of cache copies performed
196system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
197system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
198system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
199system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
200system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
201system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
202system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
203system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
204system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
205system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
206system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles
207system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles
208system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles
209system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
210system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
211system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
212system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052281 # mshr miss rate for ReadReq accesses
213system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052281 # mshr miss rate for ReadReq accesses
214system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084582 # mshr miss rate for WriteReq accesses
215system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084582 # mshr miss rate for WriteReq accesses
216system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067472 # mshr miss rate for demand accesses
217system.cpu.dcache.demand_mshr_miss_rate::total 0.067472 # mshr miss rate for demand accesses
218system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067472 # mshr miss rate for overall accesses
219system.cpu.dcache.overall_mshr_miss_rate::total 0.067472 # mshr miss rate for overall accesses
220system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
221system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
222system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
223system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
224system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
225system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
226system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
227system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
228system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
229system.cpu.l2cache.replacements 0 # number of replacements
230system.cpu.l2cache.tagsinuse 134.266314 # Cycle average of tags in use
231system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
232system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
233system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
234system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
235system.cpu.l2cache.occ_blocks::cpu.inst 105.749768 # Average occupied blocks per requestor
236system.cpu.l2cache.occ_blocks::cpu.data 28.516546 # Average occupied blocks per requestor
237system.cpu.l2cache.occ_percent::cpu.inst 0.003227 # Average percentage of cache occupancy
238system.cpu.l2cache.occ_percent::cpu.data 0.000870 # Average percentage of cache occupancy
239system.cpu.l2cache.occ_percent::total 0.004097 # Average percentage of cache occupancy
240system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
241system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
242system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
243system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
244system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
245system.cpu.l2cache.overall_hits::total 1 # number of overall hits
246system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses
247system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
248system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses
249system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses
250system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses
251system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
252system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
253system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses
254system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses
255system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
256system.cpu.l2cache.overall_misses::total 361 # number of overall misses
257system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles
258system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles
259system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles
260system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles
261system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles
262system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles
263system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles
264system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles
265system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles
266system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles
267system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles
268system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses)
269system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
270system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses)
271system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses)
272system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses)
273system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses
274system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses
275system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses
276system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses
277system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses
278system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses
279system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses
280system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
281system.cpu.l2cache.ReadReq_miss_rate::total 0.996466 # miss rate for ReadReq accesses
282system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
283system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
284system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses
285system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
286system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses
287system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses
288system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
289system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses
290system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
291system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
292system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
293system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
294system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
295system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
296system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
297system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
298system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
299system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
300system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
301system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
302system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
303system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
304system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
305system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
306system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
307system.cpu.l2cache.fast_writes 0 # number of fast writes performed
308system.cpu.l2cache.cache_copies 0 # number of cache copies performed
309system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses
310system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
311system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses
312system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses
313system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses
314system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses
315system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
316system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
317system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses
318system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
319system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses
320system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles
321system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
322system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles
323system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles
324system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles
325system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles
326system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
327system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles
328system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles
329system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
330system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles
331system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses
332system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
333system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses
334system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
335system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
336system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses
337system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
338system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses
339system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses
340system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
341system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses
342system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
343system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
344system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
345system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
346system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
347system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
348system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
349system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
350system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
351system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
352system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
353system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
354
355---------- End Simulation Statistics ----------
| 44system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
45system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
46system.cpu.num_mem_refs 1986 # number of memory refs
47system.cpu.num_load_insts 1052 # Number of load instructions
48system.cpu.num_store_insts 934 # Number of store instructions
49system.cpu.num_idle_cycles 0 # Number of idle cycles
50system.cpu.num_busy_cycles 59352 # Number of busy cycles
51system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
52system.cpu.idle_fraction 0 # Percentage of idle cycles
53system.cpu.icache.replacements 0 # number of replacements
54system.cpu.icache.tagsinuse 105.746399 # Cycle average of tags in use
55system.cpu.icache.total_refs 6637 # Total number of references to valid blocks.
56system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
57system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks.
58system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
59system.cpu.icache.occ_blocks::cpu.inst 105.746399 # Average occupied blocks per requestor
60system.cpu.icache.occ_percent::cpu.inst 0.051634 # Average percentage of cache occupancy
61system.cpu.icache.occ_percent::total 0.051634 # Average percentage of cache occupancy
62system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits
63system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits
64system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits
65system.cpu.icache.demand_hits::total 6637 # number of demand (read+write) hits
66system.cpu.icache.overall_hits::cpu.inst 6637 # number of overall hits
67system.cpu.icache.overall_hits::total 6637 # number of overall hits
68system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses
69system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses
70system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses
71system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses
72system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses
73system.cpu.icache.overall_misses::total 228 # number of overall misses
74system.cpu.icache.ReadReq_miss_latency::cpu.inst 12726000 # number of ReadReq miss cycles
75system.cpu.icache.ReadReq_miss_latency::total 12726000 # number of ReadReq miss cycles
76system.cpu.icache.demand_miss_latency::cpu.inst 12726000 # number of demand (read+write) miss cycles
77system.cpu.icache.demand_miss_latency::total 12726000 # number of demand (read+write) miss cycles
78system.cpu.icache.overall_miss_latency::cpu.inst 12726000 # number of overall miss cycles
79system.cpu.icache.overall_miss_latency::total 12726000 # number of overall miss cycles
80system.cpu.icache.ReadReq_accesses::cpu.inst 6865 # number of ReadReq accesses(hits+misses)
81system.cpu.icache.ReadReq_accesses::total 6865 # number of ReadReq accesses(hits+misses)
82system.cpu.icache.demand_accesses::cpu.inst 6865 # number of demand (read+write) accesses
83system.cpu.icache.demand_accesses::total 6865 # number of demand (read+write) accesses
84system.cpu.icache.overall_accesses::cpu.inst 6865 # number of overall (read+write) accesses
85system.cpu.icache.overall_accesses::total 6865 # number of overall (read+write) accesses
86system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033212 # miss rate for ReadReq accesses
87system.cpu.icache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses
88system.cpu.icache.demand_miss_rate::cpu.inst 0.033212 # miss rate for demand accesses
89system.cpu.icache.demand_miss_rate::total 0.033212 # miss rate for demand accesses
90system.cpu.icache.overall_miss_rate::cpu.inst 0.033212 # miss rate for overall accesses
91system.cpu.icache.overall_miss_rate::total 0.033212 # miss rate for overall accesses
92system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474 # average ReadReq miss latency
93system.cpu.icache.ReadReq_avg_miss_latency::total 55815.789474 # average ReadReq miss latency
94system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency
95system.cpu.icache.demand_avg_miss_latency::total 55815.789474 # average overall miss latency
96system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency
97system.cpu.icache.overall_avg_miss_latency::total 55815.789474 # average overall miss latency
98system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
99system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
100system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
101system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
102system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
103system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
104system.cpu.icache.fast_writes 0 # number of fast writes performed
105system.cpu.icache.cache_copies 0 # number of cache copies performed
106system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses
107system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
108system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses
109system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
110system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses
111system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses
112system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles
113system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles
114system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles
115system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles
116system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles
117system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles
118system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for ReadReq accesses
119system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033212 # mshr miss rate for ReadReq accesses
120system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for demand accesses
121system.cpu.icache.demand_mshr_miss_rate::total 0.033212 # mshr miss rate for demand accesses
122system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for overall accesses
123system.cpu.icache.overall_mshr_miss_rate::total 0.033212 # mshr miss rate for overall accesses
124system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency
125system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency
126system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
127system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
128system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
129system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
130system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
131system.cpu.dcache.replacements 0 # number of replacements
132system.cpu.dcache.tagsinuse 80.866493 # Cycle average of tags in use
133system.cpu.dcache.total_refs 1852 # Total number of references to valid blocks.
134system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
135system.cpu.dcache.avg_refs 13.820896 # Average number of references to valid blocks.
136system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
137system.cpu.dcache.occ_blocks::cpu.data 80.866493 # Average occupied blocks per requestor
138system.cpu.dcache.occ_percent::cpu.data 0.019743 # Average percentage of cache occupancy
139system.cpu.dcache.occ_percent::total 0.019743 # Average percentage of cache occupancy
140system.cpu.dcache.ReadReq_hits::cpu.data 997 # number of ReadReq hits
141system.cpu.dcache.ReadReq_hits::total 997 # number of ReadReq hits
142system.cpu.dcache.WriteReq_hits::cpu.data 855 # number of WriteReq hits
143system.cpu.dcache.WriteReq_hits::total 855 # number of WriteReq hits
144system.cpu.dcache.demand_hits::cpu.data 1852 # number of demand (read+write) hits
145system.cpu.dcache.demand_hits::total 1852 # number of demand (read+write) hits
146system.cpu.dcache.overall_hits::cpu.data 1852 # number of overall hits
147system.cpu.dcache.overall_hits::total 1852 # number of overall hits
148system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
149system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
150system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
151system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
152system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
153system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
154system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
155system.cpu.dcache.overall_misses::total 134 # number of overall misses
156system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles
157system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles
158system.cpu.dcache.WriteReq_miss_latency::cpu.data 4424000 # number of WriteReq miss cycles
159system.cpu.dcache.WriteReq_miss_latency::total 4424000 # number of WriteReq miss cycles
160system.cpu.dcache.demand_miss_latency::cpu.data 7504000 # number of demand (read+write) miss cycles
161system.cpu.dcache.demand_miss_latency::total 7504000 # number of demand (read+write) miss cycles
162system.cpu.dcache.overall_miss_latency::cpu.data 7504000 # number of overall miss cycles
163system.cpu.dcache.overall_miss_latency::total 7504000 # number of overall miss cycles
164system.cpu.dcache.ReadReq_accesses::cpu.data 1052 # number of ReadReq accesses(hits+misses)
165system.cpu.dcache.ReadReq_accesses::total 1052 # number of ReadReq accesses(hits+misses)
166system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
167system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
168system.cpu.dcache.demand_accesses::cpu.data 1986 # number of demand (read+write) accesses
169system.cpu.dcache.demand_accesses::total 1986 # number of demand (read+write) accesses
170system.cpu.dcache.overall_accesses::cpu.data 1986 # number of overall (read+write) accesses
171system.cpu.dcache.overall_accesses::total 1986 # number of overall (read+write) accesses
172system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052281 # miss rate for ReadReq accesses
173system.cpu.dcache.ReadReq_miss_rate::total 0.052281 # miss rate for ReadReq accesses
174system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084582 # miss rate for WriteReq accesses
175system.cpu.dcache.WriteReq_miss_rate::total 0.084582 # miss rate for WriteReq accesses
176system.cpu.dcache.demand_miss_rate::cpu.data 0.067472 # miss rate for demand accesses
177system.cpu.dcache.demand_miss_rate::total 0.067472 # miss rate for demand accesses
178system.cpu.dcache.overall_miss_rate::cpu.data 0.067472 # miss rate for overall accesses
179system.cpu.dcache.overall_miss_rate::total 0.067472 # miss rate for overall accesses
180system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
181system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
182system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
183system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
184system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
185system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
186system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
187system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
188system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
189system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
190system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
191system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
192system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
193system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
194system.cpu.dcache.fast_writes 0 # number of fast writes performed
195system.cpu.dcache.cache_copies 0 # number of cache copies performed
196system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
197system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
198system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
199system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
200system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
201system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
202system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
203system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
204system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
205system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
206system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles
207system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles
208system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles
209system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
210system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
211system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
212system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052281 # mshr miss rate for ReadReq accesses
213system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052281 # mshr miss rate for ReadReq accesses
214system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084582 # mshr miss rate for WriteReq accesses
215system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084582 # mshr miss rate for WriteReq accesses
216system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067472 # mshr miss rate for demand accesses
217system.cpu.dcache.demand_mshr_miss_rate::total 0.067472 # mshr miss rate for demand accesses
218system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067472 # mshr miss rate for overall accesses
219system.cpu.dcache.overall_mshr_miss_rate::total 0.067472 # mshr miss rate for overall accesses
220system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
221system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
222system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
223system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
224system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
225system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
226system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
227system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
228system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
229system.cpu.l2cache.replacements 0 # number of replacements
230system.cpu.l2cache.tagsinuse 134.266314 # Cycle average of tags in use
231system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
232system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
233system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
234system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
235system.cpu.l2cache.occ_blocks::cpu.inst 105.749768 # Average occupied blocks per requestor
236system.cpu.l2cache.occ_blocks::cpu.data 28.516546 # Average occupied blocks per requestor
237system.cpu.l2cache.occ_percent::cpu.inst 0.003227 # Average percentage of cache occupancy
238system.cpu.l2cache.occ_percent::cpu.data 0.000870 # Average percentage of cache occupancy
239system.cpu.l2cache.occ_percent::total 0.004097 # Average percentage of cache occupancy
240system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
241system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
242system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
243system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
244system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
245system.cpu.l2cache.overall_hits::total 1 # number of overall hits
246system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses
247system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
248system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses
249system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses
250system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses
251system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
252system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
253system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses
254system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses
255system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
256system.cpu.l2cache.overall_misses::total 361 # number of overall misses
257system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles
258system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles
259system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles
260system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles
261system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles
262system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles
263system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles
264system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles
265system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles
266system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles
267system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles
268system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses)
269system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
270system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses)
271system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses)
272system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses)
273system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses
274system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses
275system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses
276system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses
277system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses
278system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses
279system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses
280system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
281system.cpu.l2cache.ReadReq_miss_rate::total 0.996466 # miss rate for ReadReq accesses
282system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
283system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
284system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses
285system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
286system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses
287system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses
288system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
289system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses
290system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
291system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
292system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
293system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
294system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
295system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
296system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
297system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
298system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
299system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
300system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
301system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
302system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
303system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
304system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
305system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
306system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
307system.cpu.l2cache.fast_writes 0 # number of fast writes performed
308system.cpu.l2cache.cache_copies 0 # number of cache copies performed
309system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses
310system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
311system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses
312system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses
313system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses
314system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses
315system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
316system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
317system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses
318system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
319system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses
320system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles
321system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
322system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles
323system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles
324system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles
325system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles
326system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
327system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles
328system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles
329system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
330system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles
331system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses
332system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
333system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses
334system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
335system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
336system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses
337system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
338system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses
339system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses
340system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
341system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses
342system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
343system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
344system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
345system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
346system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
347system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
348system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
349system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
350system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
351system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
352system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
353system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
354
355---------- End Simulation Statistics ----------
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