1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000029 # Number of seconds simulated
4sim_ticks 28768000 # Number of ticks simulated
5final_tick 28768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000029 # Number of seconds simulated
4sim_ticks 28768000 # Number of ticks simulated
5final_tick 28768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 265683 # Simulator instruction rate (inst/s)
8host_op_rate 480724 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1408532008 # Simulator tick rate (ticks/s)
10host_mem_usage 216996 # Number of bytes of host memory used
11host_seconds 0.02 # Real time elapsed on the host
| 7host_inst_rate 193646 # Simulator instruction rate (inst/s)
8host_op_rate 350298 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1026195488 # Simulator tick rate (ticks/s)
10host_mem_usage 221892 # Number of bytes of host memory used
11host_seconds 0.03 # Real time elapsed on the host
|
12sim_insts 5417 # Number of instructions simulated
13sim_ops 9810 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 23104 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 14528 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 361 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 803114572 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 505005562 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 803114572 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.workload.num_syscalls 11 # Number of system calls
24system.cpu.numCycles 57536 # number of cpu cycles simulated
25system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
26system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
27system.cpu.committedInsts 5417 # Number of instructions committed
28system.cpu.committedOps 9810 # Number of ops (including micro ops) committed
29system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
30system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
31system.cpu.num_func_calls 0 # number of times a function call or return occured
32system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
33system.cpu.num_int_insts 9715 # number of integer instructions
34system.cpu.num_fp_insts 0 # number of float instructions
35system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
36system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
37system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
38system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
39system.cpu.num_mem_refs 1990 # number of memory refs
40system.cpu.num_load_insts 1056 # Number of load instructions
41system.cpu.num_store_insts 934 # Number of store instructions
42system.cpu.num_idle_cycles 0 # Number of idle cycles
43system.cpu.num_busy_cycles 57536 # Number of busy cycles
44system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
45system.cpu.idle_fraction 0 # Percentage of idle cycles
46system.cpu.icache.replacements 0 # number of replacements
47system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use
48system.cpu.icache.total_refs 6683 # Total number of references to valid blocks.
49system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
50system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks.
51system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
52system.cpu.icache.occ_blocks::cpu.inst 105.363985 # Average occupied blocks per requestor
53system.cpu.icache.occ_percent::cpu.inst 0.051447 # Average percentage of cache occupancy
54system.cpu.icache.occ_percent::total 0.051447 # Average percentage of cache occupancy
55system.cpu.icache.ReadReq_hits::cpu.inst 6683 # number of ReadReq hits
56system.cpu.icache.ReadReq_hits::total 6683 # number of ReadReq hits
57system.cpu.icache.demand_hits::cpu.inst 6683 # number of demand (read+write) hits
58system.cpu.icache.demand_hits::total 6683 # number of demand (read+write) hits
59system.cpu.icache.overall_hits::cpu.inst 6683 # number of overall hits
60system.cpu.icache.overall_hits::total 6683 # number of overall hits
61system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses
62system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses
63system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses
64system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses
65system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses
66system.cpu.icache.overall_misses::total 228 # number of overall misses
67system.cpu.icache.ReadReq_miss_latency::cpu.inst 12726000 # number of ReadReq miss cycles
68system.cpu.icache.ReadReq_miss_latency::total 12726000 # number of ReadReq miss cycles
69system.cpu.icache.demand_miss_latency::cpu.inst 12726000 # number of demand (read+write) miss cycles
70system.cpu.icache.demand_miss_latency::total 12726000 # number of demand (read+write) miss cycles
71system.cpu.icache.overall_miss_latency::cpu.inst 12726000 # number of overall miss cycles
72system.cpu.icache.overall_miss_latency::total 12726000 # number of overall miss cycles
73system.cpu.icache.ReadReq_accesses::cpu.inst 6911 # number of ReadReq accesses(hits+misses)
74system.cpu.icache.ReadReq_accesses::total 6911 # number of ReadReq accesses(hits+misses)
75system.cpu.icache.demand_accesses::cpu.inst 6911 # number of demand (read+write) accesses
76system.cpu.icache.demand_accesses::total 6911 # number of demand (read+write) accesses
77system.cpu.icache.overall_accesses::cpu.inst 6911 # number of overall (read+write) accesses
78system.cpu.icache.overall_accesses::total 6911 # number of overall (read+write) accesses
79system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032991 # miss rate for ReadReq accesses
80system.cpu.icache.demand_miss_rate::cpu.inst 0.032991 # miss rate for demand accesses
81system.cpu.icache.overall_miss_rate::cpu.inst 0.032991 # miss rate for overall accesses
82system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474 # average ReadReq miss latency
83system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency
84system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency
85system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
86system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
87system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
88system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
| 12sim_insts 5417 # Number of instructions simulated
13sim_ops 9810 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 23104 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 14528 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 361 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 803114572 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 505005562 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 803114572 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.workload.num_syscalls 11 # Number of system calls
24system.cpu.numCycles 57536 # number of cpu cycles simulated
25system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
26system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
27system.cpu.committedInsts 5417 # Number of instructions committed
28system.cpu.committedOps 9810 # Number of ops (including micro ops) committed
29system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
30system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
31system.cpu.num_func_calls 0 # number of times a function call or return occured
32system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
33system.cpu.num_int_insts 9715 # number of integer instructions
34system.cpu.num_fp_insts 0 # number of float instructions
35system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
36system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
37system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
38system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
39system.cpu.num_mem_refs 1990 # number of memory refs
40system.cpu.num_load_insts 1056 # Number of load instructions
41system.cpu.num_store_insts 934 # Number of store instructions
42system.cpu.num_idle_cycles 0 # Number of idle cycles
43system.cpu.num_busy_cycles 57536 # Number of busy cycles
44system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
45system.cpu.idle_fraction 0 # Percentage of idle cycles
46system.cpu.icache.replacements 0 # number of replacements
47system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use
48system.cpu.icache.total_refs 6683 # Total number of references to valid blocks.
49system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
50system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks.
51system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
52system.cpu.icache.occ_blocks::cpu.inst 105.363985 # Average occupied blocks per requestor
53system.cpu.icache.occ_percent::cpu.inst 0.051447 # Average percentage of cache occupancy
54system.cpu.icache.occ_percent::total 0.051447 # Average percentage of cache occupancy
55system.cpu.icache.ReadReq_hits::cpu.inst 6683 # number of ReadReq hits
56system.cpu.icache.ReadReq_hits::total 6683 # number of ReadReq hits
57system.cpu.icache.demand_hits::cpu.inst 6683 # number of demand (read+write) hits
58system.cpu.icache.demand_hits::total 6683 # number of demand (read+write) hits
59system.cpu.icache.overall_hits::cpu.inst 6683 # number of overall hits
60system.cpu.icache.overall_hits::total 6683 # number of overall hits
61system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses
62system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses
63system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses
64system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses
65system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses
66system.cpu.icache.overall_misses::total 228 # number of overall misses
67system.cpu.icache.ReadReq_miss_latency::cpu.inst 12726000 # number of ReadReq miss cycles
68system.cpu.icache.ReadReq_miss_latency::total 12726000 # number of ReadReq miss cycles
69system.cpu.icache.demand_miss_latency::cpu.inst 12726000 # number of demand (read+write) miss cycles
70system.cpu.icache.demand_miss_latency::total 12726000 # number of demand (read+write) miss cycles
71system.cpu.icache.overall_miss_latency::cpu.inst 12726000 # number of overall miss cycles
72system.cpu.icache.overall_miss_latency::total 12726000 # number of overall miss cycles
73system.cpu.icache.ReadReq_accesses::cpu.inst 6911 # number of ReadReq accesses(hits+misses)
74system.cpu.icache.ReadReq_accesses::total 6911 # number of ReadReq accesses(hits+misses)
75system.cpu.icache.demand_accesses::cpu.inst 6911 # number of demand (read+write) accesses
76system.cpu.icache.demand_accesses::total 6911 # number of demand (read+write) accesses
77system.cpu.icache.overall_accesses::cpu.inst 6911 # number of overall (read+write) accesses
78system.cpu.icache.overall_accesses::total 6911 # number of overall (read+write) accesses
79system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032991 # miss rate for ReadReq accesses
80system.cpu.icache.demand_miss_rate::cpu.inst 0.032991 # miss rate for demand accesses
81system.cpu.icache.overall_miss_rate::cpu.inst 0.032991 # miss rate for overall accesses
82system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474 # average ReadReq miss latency
83system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency
84system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency
85system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
86system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
87system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
88system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
89system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
90system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 89system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
90system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
91system.cpu.icache.fast_writes 0 # number of fast writes performed
92system.cpu.icache.cache_copies 0 # number of cache copies performed
93system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses
94system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
95system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses
96system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
97system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses
98system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses
99system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles
100system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles
101system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles
102system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles
103system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles
104system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles
105system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for ReadReq accesses
106system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for demand accesses
107system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for overall accesses
108system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency
109system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
110system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
111system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
112system.cpu.dcache.replacements 0 # number of replacements
113system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use
114system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks.
115system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
116system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks.
117system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
118system.cpu.dcache.occ_blocks::cpu.data 80.668870 # Average occupied blocks per requestor
119system.cpu.dcache.occ_percent::cpu.data 0.019695 # Average percentage of cache occupancy
120system.cpu.dcache.occ_percent::total 0.019695 # Average percentage of cache occupancy
121system.cpu.dcache.ReadReq_hits::cpu.data 1001 # number of ReadReq hits
122system.cpu.dcache.ReadReq_hits::total 1001 # number of ReadReq hits
123system.cpu.dcache.WriteReq_hits::cpu.data 855 # number of WriteReq hits
124system.cpu.dcache.WriteReq_hits::total 855 # number of WriteReq hits
125system.cpu.dcache.demand_hits::cpu.data 1856 # number of demand (read+write) hits
126system.cpu.dcache.demand_hits::total 1856 # number of demand (read+write) hits
127system.cpu.dcache.overall_hits::cpu.data 1856 # number of overall hits
128system.cpu.dcache.overall_hits::total 1856 # number of overall hits
129system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
130system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
131system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
132system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
133system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
134system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
135system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
136system.cpu.dcache.overall_misses::total 134 # number of overall misses
137system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles
138system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles
139system.cpu.dcache.WriteReq_miss_latency::cpu.data 4424000 # number of WriteReq miss cycles
140system.cpu.dcache.WriteReq_miss_latency::total 4424000 # number of WriteReq miss cycles
141system.cpu.dcache.demand_miss_latency::cpu.data 7504000 # number of demand (read+write) miss cycles
142system.cpu.dcache.demand_miss_latency::total 7504000 # number of demand (read+write) miss cycles
143system.cpu.dcache.overall_miss_latency::cpu.data 7504000 # number of overall miss cycles
144system.cpu.dcache.overall_miss_latency::total 7504000 # number of overall miss cycles
145system.cpu.dcache.ReadReq_accesses::cpu.data 1056 # number of ReadReq accesses(hits+misses)
146system.cpu.dcache.ReadReq_accesses::total 1056 # number of ReadReq accesses(hits+misses)
147system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
148system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
149system.cpu.dcache.demand_accesses::cpu.data 1990 # number of demand (read+write) accesses
150system.cpu.dcache.demand_accesses::total 1990 # number of demand (read+write) accesses
151system.cpu.dcache.overall_accesses::cpu.data 1990 # number of overall (read+write) accesses
152system.cpu.dcache.overall_accesses::total 1990 # number of overall (read+write) accesses
153system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052083 # miss rate for ReadReq accesses
154system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084582 # miss rate for WriteReq accesses
155system.cpu.dcache.demand_miss_rate::cpu.data 0.067337 # miss rate for demand accesses
156system.cpu.dcache.overall_miss_rate::cpu.data 0.067337 # miss rate for overall accesses
157system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
158system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
159system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
160system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
161system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
162system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
163system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
164system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
| 91system.cpu.icache.fast_writes 0 # number of fast writes performed
92system.cpu.icache.cache_copies 0 # number of cache copies performed
93system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses
94system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
95system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses
96system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
97system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses
98system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses
99system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles
100system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles
101system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles
102system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles
103system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles
104system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles
105system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for ReadReq accesses
106system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for demand accesses
107system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for overall accesses
108system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency
109system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
110system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
111system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
112system.cpu.dcache.replacements 0 # number of replacements
113system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use
114system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks.
115system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
116system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks.
117system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
118system.cpu.dcache.occ_blocks::cpu.data 80.668870 # Average occupied blocks per requestor
119system.cpu.dcache.occ_percent::cpu.data 0.019695 # Average percentage of cache occupancy
120system.cpu.dcache.occ_percent::total 0.019695 # Average percentage of cache occupancy
121system.cpu.dcache.ReadReq_hits::cpu.data 1001 # number of ReadReq hits
122system.cpu.dcache.ReadReq_hits::total 1001 # number of ReadReq hits
123system.cpu.dcache.WriteReq_hits::cpu.data 855 # number of WriteReq hits
124system.cpu.dcache.WriteReq_hits::total 855 # number of WriteReq hits
125system.cpu.dcache.demand_hits::cpu.data 1856 # number of demand (read+write) hits
126system.cpu.dcache.demand_hits::total 1856 # number of demand (read+write) hits
127system.cpu.dcache.overall_hits::cpu.data 1856 # number of overall hits
128system.cpu.dcache.overall_hits::total 1856 # number of overall hits
129system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
130system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
131system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
132system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
133system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
134system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
135system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
136system.cpu.dcache.overall_misses::total 134 # number of overall misses
137system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles
138system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles
139system.cpu.dcache.WriteReq_miss_latency::cpu.data 4424000 # number of WriteReq miss cycles
140system.cpu.dcache.WriteReq_miss_latency::total 4424000 # number of WriteReq miss cycles
141system.cpu.dcache.demand_miss_latency::cpu.data 7504000 # number of demand (read+write) miss cycles
142system.cpu.dcache.demand_miss_latency::total 7504000 # number of demand (read+write) miss cycles
143system.cpu.dcache.overall_miss_latency::cpu.data 7504000 # number of overall miss cycles
144system.cpu.dcache.overall_miss_latency::total 7504000 # number of overall miss cycles
145system.cpu.dcache.ReadReq_accesses::cpu.data 1056 # number of ReadReq accesses(hits+misses)
146system.cpu.dcache.ReadReq_accesses::total 1056 # number of ReadReq accesses(hits+misses)
147system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
148system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
149system.cpu.dcache.demand_accesses::cpu.data 1990 # number of demand (read+write) accesses
150system.cpu.dcache.demand_accesses::total 1990 # number of demand (read+write) accesses
151system.cpu.dcache.overall_accesses::cpu.data 1990 # number of overall (read+write) accesses
152system.cpu.dcache.overall_accesses::total 1990 # number of overall (read+write) accesses
153system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052083 # miss rate for ReadReq accesses
154system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084582 # miss rate for WriteReq accesses
155system.cpu.dcache.demand_miss_rate::cpu.data 0.067337 # miss rate for demand accesses
156system.cpu.dcache.overall_miss_rate::cpu.data 0.067337 # miss rate for overall accesses
157system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
158system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
159system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
160system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
161system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
162system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
163system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
164system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
165system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
166system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 165system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
166system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
167system.cpu.dcache.fast_writes 0 # number of fast writes performed
168system.cpu.dcache.cache_copies 0 # number of cache copies performed
169system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
170system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
171system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
172system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
173system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
174system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
175system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
176system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
177system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
178system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
179system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles
180system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles
181system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles
182system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
183system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
184system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
185system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052083 # mshr miss rate for ReadReq accesses
186system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084582 # mshr miss rate for WriteReq accesses
187system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for demand accesses
188system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for overall accesses
189system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
190system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
191system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
192system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
193system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
194system.cpu.l2cache.replacements 0 # number of replacements
195system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use
196system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
197system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
198system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
199system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
200system.cpu.l2cache.occ_blocks::cpu.inst 105.370729 # Average occupied blocks per requestor
201system.cpu.l2cache.occ_blocks::cpu.data 28.438613 # Average occupied blocks per requestor
202system.cpu.l2cache.occ_percent::cpu.inst 0.003216 # Average percentage of cache occupancy
203system.cpu.l2cache.occ_percent::cpu.data 0.000868 # Average percentage of cache occupancy
204system.cpu.l2cache.occ_percent::total 0.004084 # Average percentage of cache occupancy
205system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
206system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
207system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
208system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
209system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
210system.cpu.l2cache.overall_hits::total 1 # number of overall hits
211system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses
212system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
213system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses
214system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses
215system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses
216system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
217system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
218system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses
219system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses
220system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
221system.cpu.l2cache.overall_misses::total 361 # number of overall misses
222system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles
223system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles
224system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles
225system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles
226system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles
227system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles
228system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles
229system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles
230system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles
231system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles
232system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles
233system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses)
234system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
235system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses)
236system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses)
237system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses)
238system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses
239system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses
240system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses
241system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses
242system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses
243system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses
244system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses
245system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
246system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
247system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses
248system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
249system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses
250system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
251system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
252system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
253system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
254system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
255system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
256system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
257system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
258system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
259system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
260system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
261system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
| 167system.cpu.dcache.fast_writes 0 # number of fast writes performed
168system.cpu.dcache.cache_copies 0 # number of cache copies performed
169system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
170system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
171system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
172system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
173system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
174system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
175system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
176system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
177system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
178system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
179system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles
180system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles
181system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles
182system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
183system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
184system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
185system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052083 # mshr miss rate for ReadReq accesses
186system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084582 # mshr miss rate for WriteReq accesses
187system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for demand accesses
188system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for overall accesses
189system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
190system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
191system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
192system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
193system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
194system.cpu.l2cache.replacements 0 # number of replacements
195system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use
196system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
197system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
198system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
199system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
200system.cpu.l2cache.occ_blocks::cpu.inst 105.370729 # Average occupied blocks per requestor
201system.cpu.l2cache.occ_blocks::cpu.data 28.438613 # Average occupied blocks per requestor
202system.cpu.l2cache.occ_percent::cpu.inst 0.003216 # Average percentage of cache occupancy
203system.cpu.l2cache.occ_percent::cpu.data 0.000868 # Average percentage of cache occupancy
204system.cpu.l2cache.occ_percent::total 0.004084 # Average percentage of cache occupancy
205system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
206system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
207system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
208system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
209system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
210system.cpu.l2cache.overall_hits::total 1 # number of overall hits
211system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses
212system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
213system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses
214system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses
215system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses
216system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
217system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
218system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses
219system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses
220system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
221system.cpu.l2cache.overall_misses::total 361 # number of overall misses
222system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles
223system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles
224system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles
225system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles
226system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles
227system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles
228system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles
229system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles
230system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles
231system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles
232system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles
233system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses)
234system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
235system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses)
236system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses)
237system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses)
238system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses
239system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses
240system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses
241system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses
242system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses
243system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses
244system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses
245system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
246system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
247system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses
248system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
249system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses
250system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
251system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
252system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
253system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
254system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
255system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
256system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
257system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
258system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
259system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
260system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
261system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
262system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
263system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 262system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
263system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
264system.cpu.l2cache.fast_writes 0 # number of fast writes performed
265system.cpu.l2cache.cache_copies 0 # number of cache copies performed
266system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses
267system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
268system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses
269system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses
270system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses
271system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses
272system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
273system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
274system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses
275system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
276system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses
277system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles
278system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
279system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles
280system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles
281system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles
282system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles
283system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
284system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles
285system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles
286system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
287system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles
288system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses
289system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
290system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
291system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses
292system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
293system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses
294system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
295system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
296system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
297system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
298system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
299system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
300system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
301system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
302system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
303
304---------- End Simulation Statistics ----------
| 264system.cpu.l2cache.fast_writes 0 # number of fast writes performed
265system.cpu.l2cache.cache_copies 0 # number of cache copies performed
266system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses
267system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
268system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses
269system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses
270system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses
271system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses
272system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
273system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
274system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses
275system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
276system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses
277system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles
278system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
279system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles
280system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles
281system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles
282system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles
283system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
284system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles
285system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles
286system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
287system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles
288system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses
289system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
290system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
291system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses
292system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
293system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses
294system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
295system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
296system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
297system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
298system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
299system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
300system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
301system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
302system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
303
304---------- End Simulation Statistics ----------
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