Cross Reference: /gem5/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt

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stats.txt (11606:6b749761c398)	stats.txt (11687:b3d5f0e9e258)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated 4sim_ticks 31247500 # Number of ticks simulated 5final_tick 31247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated 4sim_ticks 31247500 # Number of ticks simulated 5final_tick 31247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 85405 # Simulator instruction rate (inst/s) 8host_op_rate 154687 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 495766938 # Simulator tick rate (ticks/s) 10host_mem_usage 269328 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host	7host_inst_rate 377585 # Simulator instruction rate (inst/s) 8host_op_rate 682900 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2185869298 # Simulator tick rate (ticks/s) 10host_mem_usage 268708 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 5381 # Number of instructions simulated 13sim_ops 9748 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 19system.physmem.bytes_read::total 23104 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 361 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 464933195 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 274453956 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 739387151 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 464933195 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 464933195 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 464933195 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 274453956 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 739387151 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 36system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 37system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 38system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 39system.cpu.workload.num_syscalls 11 # Number of system calls 40system.cpu.pwrStateResidencyTicks::ON 31247500 # Cumulative time (in ticks) in various power states 41system.cpu.numCycles 62495 # number of cpu cycles simulated 42system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 44system.cpu.committedInsts 5381 # Number of instructions committed 45system.cpu.committedOps 9748 # Number of ops (including micro ops) committed 46system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses 47system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 48system.cpu.num_func_calls 209 # number of times a function call or return occured 49system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls 50system.cpu.num_int_insts 9654 # number of integer instructions 51system.cpu.num_fp_insts 0 # number of float instructions 52system.cpu.num_int_register_reads 18335 # number of times the integer registers were read 53system.cpu.num_int_register_writes 7527 # number of times the integer registers were written 54system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 55system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 56system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read 57system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written 58system.cpu.num_mem_refs 1988 # number of memory refs 59system.cpu.num_load_insts 1053 # Number of load instructions 60system.cpu.num_store_insts 935 # Number of store instructions 61system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 62system.cpu.num_busy_cycles 62494.998000 # Number of busy cycles 63system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 64system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 65system.cpu.Branches 1208 # Number of branches fetched 66system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 67system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction 68system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction 69system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction 70system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction 71system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction 72system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction 73system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction	12sim_insts 5381 # Number of instructions simulated 13sim_ops 9748 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 19system.physmem.bytes_read::total 23104 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 361 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 464933195 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 274453956 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 739387151 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 464933195 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 464933195 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 464933195 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 274453956 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 739387151 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 36system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 37system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 38system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 39system.cpu.workload.num_syscalls 11 # Number of system calls 40system.cpu.pwrStateResidencyTicks::ON 31247500 # Cumulative time (in ticks) in various power states 41system.cpu.numCycles 62495 # number of cpu cycles simulated 42system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 44system.cpu.committedInsts 5381 # Number of instructions committed 45system.cpu.committedOps 9748 # Number of ops (including micro ops) committed 46system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses 47system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 48system.cpu.num_func_calls 209 # number of times a function call or return occured 49system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls 50system.cpu.num_int_insts 9654 # number of integer instructions 51system.cpu.num_fp_insts 0 # number of float instructions 52system.cpu.num_int_register_reads 18335 # number of times the integer registers were read 53system.cpu.num_int_register_writes 7527 # number of times the integer registers were written 54system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 55system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 56system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read 57system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written 58system.cpu.num_mem_refs 1988 # number of memory refs 59system.cpu.num_load_insts 1053 # Number of load instructions 60system.cpu.num_store_insts 935 # Number of store instructions 61system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 62system.cpu.num_busy_cycles 62494.998000 # Number of busy cycles 63system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 64system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 65system.cpu.Branches 1208 # Number of branches fetched 66system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 67system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction 68system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction 69system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction 70system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction 71system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction 72system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction 73system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction
	74system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% # Class of executed instruction
74system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction	75system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction
	76system.cpu.op_class::FloatMisc 0 0.00% 79.61% # Class of executed instruction
75system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction 76system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction 77system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction 78system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction 79system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction 80system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction 81system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction 82system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction 83system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction 84system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction 85system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction 86system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction 87system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction 88system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction 89system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction 90system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction 91system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction 92system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction 93system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction 94system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction 95system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction 96system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction 97system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction	77system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction 78system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction 79system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction 80system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction 81system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction 82system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction 83system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction 84system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction 85system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction 86system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction 87system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction 88system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction 89system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction 90system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction 91system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction 92system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction 93system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction 94system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction 95system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction 96system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction 97system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction 98system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction 99system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction
	100system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 101system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
98system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 99system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::total 9748 # Class of executed instruction 101system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 102system.cpu.dcache.tags.replacements 0 # number of replacements 103system.cpu.dcache.tags.tagsinuse 80.527852 # Cycle average of tags in use 104system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 108system.cpu.dcache.tags.occ_blocks::cpu.data 80.527852 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.019660 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.019660 # Average percentage of cache occupancy 111system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 114system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id 115system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses 116system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses 117system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 118system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits 119system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits 120system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits 121system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits 122system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits 123system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits 124system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits 125system.cpu.dcache.overall_hits::total 1854 # number of overall hits 126system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses 127system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses 128system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses 129system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses 130system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses 131system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses 132system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses 133system.cpu.dcache.overall_misses::total 134 # number of overall misses 134system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles 135system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles 136system.cpu.dcache.WriteReq_miss_latency::cpu.data 4977000 # number of WriteReq miss cycles 137system.cpu.dcache.WriteReq_miss_latency::total 4977000 # number of WriteReq miss cycles 138system.cpu.dcache.demand_miss_latency::cpu.data 8442000 # number of demand (read+write) miss cycles 139system.cpu.dcache.demand_miss_latency::total 8442000 # number of demand (read+write) miss cycles 140system.cpu.dcache.overall_miss_latency::cpu.data 8442000 # number of overall miss cycles 141system.cpu.dcache.overall_miss_latency::total 8442000 # number of overall miss cycles 142system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) 143system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) 144system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 145system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) 146system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses 147system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses 148system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses 149system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses 150system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses 151system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses 152system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses 153system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses 154system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses 155system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses 156system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses 157system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses 158system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency 159system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency 160system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency 161system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency 162system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency 163system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency 164system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency 165system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency 166system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 167system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 168system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 169system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 170system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 171system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 172system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 173system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 174system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses 175system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses 176system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 177system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses 178system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 179system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses 180system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles 181system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles 182system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4898000 # number of WriteReq MSHR miss cycles 183system.cpu.dcache.WriteReq_mshr_miss_latency::total 4898000 # number of WriteReq MSHR miss cycles 184system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8308000 # number of demand (read+write) MSHR miss cycles 185system.cpu.dcache.demand_mshr_miss_latency::total 8308000 # number of demand (read+write) MSHR miss cycles 186system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8308000 # number of overall MSHR miss cycles 187system.cpu.dcache.overall_mshr_miss_latency::total 8308000 # number of overall MSHR miss cycles 188system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses 189system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses 190system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses 191system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses 192system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses 193system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses 194system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses 195system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses 196system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency 197system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency 198system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency 199system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency 200system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency 201system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency 202system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency 203system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency 204system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 205system.cpu.icache.tags.replacements 0 # number of replacements 206system.cpu.icache.tags.tagsinuse 105.231814 # Cycle average of tags in use 207system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. 208system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. 209system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. 210system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 211system.cpu.icache.tags.occ_blocks::cpu.inst 105.231814 # Average occupied blocks per requestor 212system.cpu.icache.tags.occ_percent::cpu.inst 0.051383 # Average percentage of cache occupancy 213system.cpu.icache.tags.occ_percent::total 0.051383 # Average percentage of cache occupancy 214system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id 215system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id 216system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id 217system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id 218system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses 219system.cpu.icache.tags.data_accesses 13956 # Number of data accesses 220system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 221system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits 222system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits 223system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits 224system.cpu.icache.demand_hits::total 6636 # number of demand (read+write) hits 225system.cpu.icache.overall_hits::cpu.inst 6636 # number of overall hits 226system.cpu.icache.overall_hits::total 6636 # number of overall hits 227system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses 228system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses 229system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses 230system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses 231system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses 232system.cpu.icache.overall_misses::total 228 # number of overall misses 233system.cpu.icache.ReadReq_miss_latency::cpu.inst 14315500 # number of ReadReq miss cycles 234system.cpu.icache.ReadReq_miss_latency::total 14315500 # number of ReadReq miss cycles 235system.cpu.icache.demand_miss_latency::cpu.inst 14315500 # number of demand (read+write) miss cycles 236system.cpu.icache.demand_miss_latency::total 14315500 # number of demand (read+write) miss cycles 237system.cpu.icache.overall_miss_latency::cpu.inst 14315500 # number of overall miss cycles 238system.cpu.icache.overall_miss_latency::total 14315500 # number of overall miss cycles 239system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) 240system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) 241system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses 242system.cpu.icache.demand_accesses::total 6864 # number of demand (read+write) accesses 243system.cpu.icache.overall_accesses::cpu.inst 6864 # number of overall (read+write) accesses 244system.cpu.icache.overall_accesses::total 6864 # number of overall (read+write) accesses 245system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033217 # miss rate for ReadReq accesses 246system.cpu.icache.ReadReq_miss_rate::total 0.033217 # miss rate for ReadReq accesses 247system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 # miss rate for demand accesses 248system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses 249system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses 250system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses 251system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62787.280702 # average ReadReq miss latency 252system.cpu.icache.ReadReq_avg_miss_latency::total 62787.280702 # average ReadReq miss latency 253system.cpu.icache.demand_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency 254system.cpu.icache.demand_avg_miss_latency::total 62787.280702 # average overall miss latency 255system.cpu.icache.overall_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency 256system.cpu.icache.overall_avg_miss_latency::total 62787.280702 # average overall miss latency 257system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 258system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 259system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 260system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 261system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 262system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 263system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses 264system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses 265system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses 266system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses 267system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses 268system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses 269system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14087500 # number of ReadReq MSHR miss cycles 270system.cpu.icache.ReadReq_mshr_miss_latency::total 14087500 # number of ReadReq MSHR miss cycles 271system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14087500 # number of demand (read+write) MSHR miss cycles 272system.cpu.icache.demand_mshr_miss_latency::total 14087500 # number of demand (read+write) MSHR miss cycles 273system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14087500 # number of overall MSHR miss cycles 274system.cpu.icache.overall_mshr_miss_latency::total 14087500 # number of overall MSHR miss cycles 275system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses 276system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses 277system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses 278system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses 279system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses 280system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses 281system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61787.280702 # average ReadReq mshr miss latency 282system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61787.280702 # average ReadReq mshr miss latency 283system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency 284system.cpu.icache.demand_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency 285system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency 286system.cpu.icache.overall_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency 287system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 288system.cpu.l2cache.tags.replacements 0 # number of replacements 289system.cpu.l2cache.tags.tagsinuse 185.792229 # Cycle average of tags in use 290system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 291system.cpu.l2cache.tags.sampled_refs 361 # Sample count of references to valid blocks. 292system.cpu.l2cache.tags.avg_refs 0.002770 # Average number of references to valid blocks. 293system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 294system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.219349 # Average occupied blocks per requestor 295system.cpu.l2cache.tags.occ_blocks::cpu.data 80.572880 # Average occupied blocks per requestor 296system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003211 # Average percentage of cache occupancy 297system.cpu.l2cache.tags.occ_percent::cpu.data 0.002459 # Average percentage of cache occupancy 298system.cpu.l2cache.tags.occ_percent::total 0.005670 # Average percentage of cache occupancy 299system.cpu.l2cache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id 300system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 301system.cpu.l2cache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id 302system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011017 # Percentage of cache occupancy per task id 303system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses 304system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses 305system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 306system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 307system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 308system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 309system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 310system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 311system.cpu.l2cache.overall_hits::total 1 # number of overall hits 312system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses 313system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses 314system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 227 # number of ReadCleanReq misses 315system.cpu.l2cache.ReadCleanReq_misses::total 227 # number of ReadCleanReq misses 316system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses 317system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses 318system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses 319system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses 320system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses 321system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses 322system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses 323system.cpu.l2cache.overall_misses::total 361 # number of overall misses 324system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4779500 # number of ReadExReq miss cycles 325system.cpu.l2cache.ReadExReq_miss_latency::total 4779500 # number of ReadExReq miss cycles 326system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13734000 # number of ReadCleanReq miss cycles 327system.cpu.l2cache.ReadCleanReq_miss_latency::total 13734000 # number of ReadCleanReq miss cycles 328system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles 329system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles 330system.cpu.l2cache.demand_miss_latency::cpu.inst 13734000 # number of demand (read+write) miss cycles 331system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles 332system.cpu.l2cache.demand_miss_latency::total 21841000 # number of demand (read+write) miss cycles 333system.cpu.l2cache.overall_miss_latency::cpu.inst 13734000 # number of overall miss cycles 334system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles 335system.cpu.l2cache.overall_miss_latency::total 21841000 # number of overall miss cycles 336system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) 337system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) 338system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses) 339system.cpu.l2cache.ReadCleanReq_accesses::total 228 # number of ReadCleanReq accesses(hits+misses) 340system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) 341system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) 342system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses 343system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses 344system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses 345system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses 346system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses 347system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses 348system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 349system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 350system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadCleanReq accesses 351system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995614 # miss rate for ReadCleanReq accesses 352system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 353system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 354system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses 355system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 356system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses 357system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses 358system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 359system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses 360system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency 361system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency 362system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.202643 # average ReadCleanReq miss latency 363system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.202643 # average ReadCleanReq miss latency 364system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency 365system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency 366system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency 367system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency 368system.cpu.l2cache.demand_avg_miss_latency::total 60501.385042 # average overall miss latency 369system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency 370system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency 371system.cpu.l2cache.overall_avg_miss_latency::total 60501.385042 # average overall miss latency 372system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 373system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 374system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 375system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 376system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 377system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 378system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses 379system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses 380system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 227 # number of ReadCleanReq MSHR misses 381system.cpu.l2cache.ReadCleanReq_mshr_misses::total 227 # number of ReadCleanReq MSHR misses 382system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 383system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses 384system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses 385system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 386system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses 387system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses 388system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 389system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses 390system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3989500 # number of ReadExReq MSHR miss cycles 391system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3989500 # number of ReadExReq MSHR miss cycles 392system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11464000 # number of ReadCleanReq MSHR miss cycles 393system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11464000 # number of ReadCleanReq MSHR miss cycles 394system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2777500 # number of ReadSharedReq MSHR miss cycles 395system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2777500 # number of ReadSharedReq MSHR miss cycles 396system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11464000 # number of demand (read+write) MSHR miss cycles 397system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles 398system.cpu.l2cache.demand_mshr_miss_latency::total 18231000 # number of demand (read+write) MSHR miss cycles 399system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11464000 # number of overall MSHR miss cycles 400system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles 401system.cpu.l2cache.overall_mshr_miss_latency::total 18231000 # number of overall MSHR miss cycles 402system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 403system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 404system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses 405system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995614 # mshr miss rate for ReadCleanReq accesses 406system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 407system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 408system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses 409system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 410system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses 411system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses 412system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 413system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses 414system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency 415system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency 416system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.202643 # average ReadCleanReq mshr miss latency 417system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.202643 # average ReadCleanReq mshr miss latency 418system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency 419system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency 420system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency 421system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 422system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency 423system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency 424system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 425system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency 426system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. 427system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 428system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 429system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 430system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 431system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 432system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 433system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution 435system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution 436system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 # Transaction distribution 437system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution 438system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) 439system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) 440system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) 441system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes) 442system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes) 443system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) 444system.cpu.toL2Bus.snoops 0 # Total snoops (count) 445system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 446system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram 447system.cpu.toL2Bus.snoop_fanout::mean 0.002762 # Request fanout histogram 448system.cpu.toL2Bus.snoop_fanout::stdev 0.052559 # Request fanout histogram 449system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 450system.cpu.toL2Bus.snoop_fanout::0 361 99.72% 99.72% # Request fanout histogram 451system.cpu.toL2Bus.snoop_fanout::1 1 0.28% 100.00% # Request fanout histogram 452system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 453system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 454system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 455system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 456system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram 457system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) 458system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 459system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) 460system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%) 461system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) 462system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) 463system.membus.snoop_filter.tot_requests 361 # Total number of requests made to the snoop filter. 464system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 465system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 466system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 467system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 468system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 469system.membus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 470system.membus.trans_dist::ReadResp 282 # Transaction distribution 471system.membus.trans_dist::ReadExReq 79 # Transaction distribution 472system.membus.trans_dist::ReadExResp 79 # Transaction distribution 473system.membus.trans_dist::ReadSharedReq 282 # Transaction distribution 474system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) 475system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) 476system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) 477system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) 478system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) 479system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) 480system.membus.snoops 0 # Total snoops (count) 481system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 482system.membus.snoop_fanout::samples 361 # Request fanout histogram 483system.membus.snoop_fanout::mean 0 # Request fanout histogram 484system.membus.snoop_fanout::stdev 0 # Request fanout histogram 485system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 486system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram 487system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 488system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 489system.membus.snoop_fanout::min_value 0 # Request fanout histogram 490system.membus.snoop_fanout::max_value 0 # Request fanout histogram 491system.membus.snoop_fanout::total 361 # Request fanout histogram 492system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks) 493system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) 494system.membus.respLayer1.occupancy 1805000 # Layer occupancy (ticks) 495system.membus.respLayer1.utilization 5.8 # Layer utilization (%) 496 497---------- End Simulation Statistics ----------	102system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 103system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 104system.cpu.op_class::total 9748 # Class of executed instruction 105system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 106system.cpu.dcache.tags.replacements 0 # number of replacements 107system.cpu.dcache.tags.tagsinuse 80.527852 # Cycle average of tags in use 108system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. 109system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. 110system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. 111system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 112system.cpu.dcache.tags.occ_blocks::cpu.data 80.527852 # Average occupied blocks per requestor 113system.cpu.dcache.tags.occ_percent::cpu.data 0.019660 # Average percentage of cache occupancy 114system.cpu.dcache.tags.occ_percent::total 0.019660 # Average percentage of cache occupancy 115system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id 116system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 117system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 118system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id 119system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses 120system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses 121system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 122system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits 123system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits 124system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits 125system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits 126system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits 127system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits 128system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits 129system.cpu.dcache.overall_hits::total 1854 # number of overall hits 130system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses 131system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses 132system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses 133system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses 134system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses 135system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses 136system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses 137system.cpu.dcache.overall_misses::total 134 # number of overall misses 138system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles 139system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles 140system.cpu.dcache.WriteReq_miss_latency::cpu.data 4977000 # number of WriteReq miss cycles 141system.cpu.dcache.WriteReq_miss_latency::total 4977000 # number of WriteReq miss cycles 142system.cpu.dcache.demand_miss_latency::cpu.data 8442000 # number of demand (read+write) miss cycles 143system.cpu.dcache.demand_miss_latency::total 8442000 # number of demand (read+write) miss cycles 144system.cpu.dcache.overall_miss_latency::cpu.data 8442000 # number of overall miss cycles 145system.cpu.dcache.overall_miss_latency::total 8442000 # number of overall miss cycles 146system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) 147system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) 148system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 149system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) 150system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses 151system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses 152system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses 153system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses 154system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses 155system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses 156system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses 157system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses 158system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses 159system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses 160system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses 161system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses 162system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency 163system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency 164system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency 165system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency 166system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency 167system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency 168system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency 169system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency 170system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 171system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 172system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 173system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 174system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 175system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 176system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 177system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 178system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses 179system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses 180system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 181system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses 182system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 183system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses 184system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles 185system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles 186system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4898000 # number of WriteReq MSHR miss cycles 187system.cpu.dcache.WriteReq_mshr_miss_latency::total 4898000 # number of WriteReq MSHR miss cycles 188system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8308000 # number of demand (read+write) MSHR miss cycles 189system.cpu.dcache.demand_mshr_miss_latency::total 8308000 # number of demand (read+write) MSHR miss cycles 190system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8308000 # number of overall MSHR miss cycles 191system.cpu.dcache.overall_mshr_miss_latency::total 8308000 # number of overall MSHR miss cycles 192system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses 193system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses 194system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses 195system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses 196system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses 197system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses 198system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses 199system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses 200system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency 201system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency 202system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency 203system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency 204system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency 205system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency 206system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency 207system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency 208system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 209system.cpu.icache.tags.replacements 0 # number of replacements 210system.cpu.icache.tags.tagsinuse 105.231814 # Cycle average of tags in use 211system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. 212system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. 213system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. 214system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 215system.cpu.icache.tags.occ_blocks::cpu.inst 105.231814 # Average occupied blocks per requestor 216system.cpu.icache.tags.occ_percent::cpu.inst 0.051383 # Average percentage of cache occupancy 217system.cpu.icache.tags.occ_percent::total 0.051383 # Average percentage of cache occupancy 218system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id 219system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id 220system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id 221system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id 222system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses 223system.cpu.icache.tags.data_accesses 13956 # Number of data accesses 224system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 225system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits 226system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits 227system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits 228system.cpu.icache.demand_hits::total 6636 # number of demand (read+write) hits 229system.cpu.icache.overall_hits::cpu.inst 6636 # number of overall hits 230system.cpu.icache.overall_hits::total 6636 # number of overall hits 231system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses 232system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses 233system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses 234system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses 235system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses 236system.cpu.icache.overall_misses::total 228 # number of overall misses 237system.cpu.icache.ReadReq_miss_latency::cpu.inst 14315500 # number of ReadReq miss cycles 238system.cpu.icache.ReadReq_miss_latency::total 14315500 # number of ReadReq miss cycles 239system.cpu.icache.demand_miss_latency::cpu.inst 14315500 # number of demand (read+write) miss cycles 240system.cpu.icache.demand_miss_latency::total 14315500 # number of demand (read+write) miss cycles 241system.cpu.icache.overall_miss_latency::cpu.inst 14315500 # number of overall miss cycles 242system.cpu.icache.overall_miss_latency::total 14315500 # number of overall miss cycles 243system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) 244system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) 245system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses 246system.cpu.icache.demand_accesses::total 6864 # number of demand (read+write) accesses 247system.cpu.icache.overall_accesses::cpu.inst 6864 # number of overall (read+write) accesses 248system.cpu.icache.overall_accesses::total 6864 # number of overall (read+write) accesses 249system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033217 # miss rate for ReadReq accesses 250system.cpu.icache.ReadReq_miss_rate::total 0.033217 # miss rate for ReadReq accesses 251system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 # miss rate for demand accesses 252system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses 253system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses 254system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses 255system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62787.280702 # average ReadReq miss latency 256system.cpu.icache.ReadReq_avg_miss_latency::total 62787.280702 # average ReadReq miss latency 257system.cpu.icache.demand_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency 258system.cpu.icache.demand_avg_miss_latency::total 62787.280702 # average overall miss latency 259system.cpu.icache.overall_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency 260system.cpu.icache.overall_avg_miss_latency::total 62787.280702 # average overall miss latency 261system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 262system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 263system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 264system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 265system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 266system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 267system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses 268system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses 269system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses 270system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses 271system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses 272system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses 273system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14087500 # number of ReadReq MSHR miss cycles 274system.cpu.icache.ReadReq_mshr_miss_latency::total 14087500 # number of ReadReq MSHR miss cycles 275system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14087500 # number of demand (read+write) MSHR miss cycles 276system.cpu.icache.demand_mshr_miss_latency::total 14087500 # number of demand (read+write) MSHR miss cycles 277system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14087500 # number of overall MSHR miss cycles 278system.cpu.icache.overall_mshr_miss_latency::total 14087500 # number of overall MSHR miss cycles 279system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses 280system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses 281system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses 282system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses 283system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses 284system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses 285system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61787.280702 # average ReadReq mshr miss latency 286system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61787.280702 # average ReadReq mshr miss latency 287system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency 288system.cpu.icache.demand_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency 289system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency 290system.cpu.icache.overall_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency 291system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 292system.cpu.l2cache.tags.replacements 0 # number of replacements 293system.cpu.l2cache.tags.tagsinuse 185.792229 # Cycle average of tags in use 294system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 295system.cpu.l2cache.tags.sampled_refs 361 # Sample count of references to valid blocks. 296system.cpu.l2cache.tags.avg_refs 0.002770 # Average number of references to valid blocks. 297system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 298system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.219349 # Average occupied blocks per requestor 299system.cpu.l2cache.tags.occ_blocks::cpu.data 80.572880 # Average occupied blocks per requestor 300system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003211 # Average percentage of cache occupancy 301system.cpu.l2cache.tags.occ_percent::cpu.data 0.002459 # Average percentage of cache occupancy 302system.cpu.l2cache.tags.occ_percent::total 0.005670 # Average percentage of cache occupancy 303system.cpu.l2cache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id 304system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 305system.cpu.l2cache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id 306system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011017 # Percentage of cache occupancy per task id 307system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses 308system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses 309system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 310system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 311system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 312system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 313system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 314system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 315system.cpu.l2cache.overall_hits::total 1 # number of overall hits 316system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses 317system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses 318system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 227 # number of ReadCleanReq misses 319system.cpu.l2cache.ReadCleanReq_misses::total 227 # number of ReadCleanReq misses 320system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses 321system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses 322system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses 323system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses 324system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses 325system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses 326system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses 327system.cpu.l2cache.overall_misses::total 361 # number of overall misses 328system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4779500 # number of ReadExReq miss cycles 329system.cpu.l2cache.ReadExReq_miss_latency::total 4779500 # number of ReadExReq miss cycles 330system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13734000 # number of ReadCleanReq miss cycles 331system.cpu.l2cache.ReadCleanReq_miss_latency::total 13734000 # number of ReadCleanReq miss cycles 332system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles 333system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles 334system.cpu.l2cache.demand_miss_latency::cpu.inst 13734000 # number of demand (read+write) miss cycles 335system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles 336system.cpu.l2cache.demand_miss_latency::total 21841000 # number of demand (read+write) miss cycles 337system.cpu.l2cache.overall_miss_latency::cpu.inst 13734000 # number of overall miss cycles 338system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles 339system.cpu.l2cache.overall_miss_latency::total 21841000 # number of overall miss cycles 340system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) 341system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) 342system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses) 343system.cpu.l2cache.ReadCleanReq_accesses::total 228 # number of ReadCleanReq accesses(hits+misses) 344system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) 345system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) 346system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses 347system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses 348system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses 349system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses 350system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses 351system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses 352system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 353system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 354system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadCleanReq accesses 355system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995614 # miss rate for ReadCleanReq accesses 356system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 357system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 358system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses 359system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 360system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses 361system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses 362system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 363system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses 364system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency 365system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency 366system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.202643 # average ReadCleanReq miss latency 367system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.202643 # average ReadCleanReq miss latency 368system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency 369system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency 370system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency 371system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency 372system.cpu.l2cache.demand_avg_miss_latency::total 60501.385042 # average overall miss latency 373system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency 374system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency 375system.cpu.l2cache.overall_avg_miss_latency::total 60501.385042 # average overall miss latency 376system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 377system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 378system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 379system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 380system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 381system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 382system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses 383system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses 384system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 227 # number of ReadCleanReq MSHR misses 385system.cpu.l2cache.ReadCleanReq_mshr_misses::total 227 # number of ReadCleanReq MSHR misses 386system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses 387system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses 388system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses 389system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 390system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses 391system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses 392system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 393system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses 394system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3989500 # number of ReadExReq MSHR miss cycles 395system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3989500 # number of ReadExReq MSHR miss cycles 396system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11464000 # number of ReadCleanReq MSHR miss cycles 397system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11464000 # number of ReadCleanReq MSHR miss cycles 398system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2777500 # number of ReadSharedReq MSHR miss cycles 399system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2777500 # number of ReadSharedReq MSHR miss cycles 400system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11464000 # number of demand (read+write) MSHR miss cycles 401system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles 402system.cpu.l2cache.demand_mshr_miss_latency::total 18231000 # number of demand (read+write) MSHR miss cycles 403system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11464000 # number of overall MSHR miss cycles 404system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles 405system.cpu.l2cache.overall_mshr_miss_latency::total 18231000 # number of overall MSHR miss cycles 406system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 407system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 408system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses 409system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995614 # mshr miss rate for ReadCleanReq accesses 410system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 411system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 412system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses 413system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 414system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses 415system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses 416system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 417system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses 418system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency 419system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency 420system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.202643 # average ReadCleanReq mshr miss latency 421system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.202643 # average ReadCleanReq mshr miss latency 422system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency 423system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency 424system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency 425system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 426system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency 427system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency 428system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 429system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency 430system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. 431system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 432system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 433system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 434system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 435system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 436system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 437system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution 438system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution 439system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution 440system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 # Transaction distribution 441system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution 442system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) 443system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) 444system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) 445system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes) 446system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes) 447system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) 448system.cpu.toL2Bus.snoops 0 # Total snoops (count) 449system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 450system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram 451system.cpu.toL2Bus.snoop_fanout::mean 0.002762 # Request fanout histogram 452system.cpu.toL2Bus.snoop_fanout::stdev 0.052559 # Request fanout histogram 453system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 454system.cpu.toL2Bus.snoop_fanout::0 361 99.72% 99.72% # Request fanout histogram 455system.cpu.toL2Bus.snoop_fanout::1 1 0.28% 100.00% # Request fanout histogram 456system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 457system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 458system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 459system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 460system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram 461system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) 462system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 463system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) 464system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%) 465system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) 466system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) 467system.membus.snoop_filter.tot_requests 361 # Total number of requests made to the snoop filter. 468system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 469system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 470system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 471system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 472system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 473system.membus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states 474system.membus.trans_dist::ReadResp 282 # Transaction distribution 475system.membus.trans_dist::ReadExReq 79 # Transaction distribution 476system.membus.trans_dist::ReadExResp 79 # Transaction distribution 477system.membus.trans_dist::ReadSharedReq 282 # Transaction distribution 478system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) 479system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) 480system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) 481system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) 482system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) 483system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) 484system.membus.snoops 0 # Total snoops (count) 485system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 486system.membus.snoop_fanout::samples 361 # Request fanout histogram 487system.membus.snoop_fanout::mean 0 # Request fanout histogram 488system.membus.snoop_fanout::stdev 0 # Request fanout histogram 489system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 490system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram 491system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 492system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 493system.membus.snoop_fanout::min_value 0 # Request fanout histogram 494system.membus.snoop_fanout::max_value 0 # Request fanout histogram 495system.membus.snoop_fanout::total 361 # Request fanout histogram 496system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks) 497system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) 498system.membus.respLayer1.occupancy 1805000 # Layer occupancy (ticks) 499system.membus.respLayer1.utilization 5.8 # Layer utilization (%) 500 501---------- End Simulation Statistics ----------