1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000028 # Number of seconds simulated
4sim_ticks 28358000 # Number of ticks simulated
5final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000028 # Number of seconds simulated
4sim_ticks 28358000 # Number of ticks simulated
5final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 44998 # Simulator instruction rate (inst/s)
8host_op_rate 81497 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 237030591 # Simulator tick rate (ticks/s)
10host_mem_usage 247544 # Number of bytes of host memory used
11host_seconds 0.12 # Real time elapsed on the host
| 7host_inst_rate 50744 # Simulator instruction rate (inst/s)
8host_op_rate 91910 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 267330545 # Simulator tick rate (ticks/s)
10host_mem_usage 295388 # Number of bytes of host memory used
11host_seconds 0.11 # Real time elapsed on the host
|
12sim_insts 5381 # Number of instructions simulated
13sim_ops 9748 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
18system.physmem.bytes_read::total 23104 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 361 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 512306933 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 302419070 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 814726003 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 512306933 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 512306933 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s)
32system.membus.throughput 814726003 # Throughput (bytes/s)
33system.membus.trans_dist::ReadReq 282 # Transaction distribution
34system.membus.trans_dist::ReadResp 282 # Transaction distribution
35system.membus.trans_dist::ReadExReq 79 # Transaction distribution
36system.membus.trans_dist::ReadExResp 79 # Transaction distribution
37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes)
38system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes)
39system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes)
40system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
41system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes)
42system.membus.tot_pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes)
43system.membus.data_through_bus 23104 # Total data (bytes)
44system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
45system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks)
46system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
47system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks)
48system.membus.respLayer1.utilization 11.5 # Layer utilization (%)
49system.cpu_clk_domain.clock 500 # Clock period in ticks
50system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
51system.cpu.workload.num_syscalls 11 # Number of system calls
52system.cpu.numCycles 56716 # number of cpu cycles simulated
53system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
54system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
55system.cpu.committedInsts 5381 # Number of instructions committed
56system.cpu.committedOps 9748 # Number of ops (including micro ops) committed
57system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses
58system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
59system.cpu.num_func_calls 209 # number of times a function call or return occured
60system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
61system.cpu.num_int_insts 9654 # number of integer instructions
62system.cpu.num_fp_insts 0 # number of float instructions
63system.cpu.num_int_register_reads 18335 # number of times the integer registers were read
64system.cpu.num_int_register_writes 7527 # number of times the integer registers were written
65system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
66system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
67system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read
68system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written
69system.cpu.num_mem_refs 1988 # number of memory refs
70system.cpu.num_load_insts 1053 # Number of load instructions
71system.cpu.num_store_insts 935 # Number of store instructions
72system.cpu.num_idle_cycles 0 # Number of idle cycles
73system.cpu.num_busy_cycles 56716 # Number of busy cycles
74system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
75system.cpu.idle_fraction 0 # Percentage of idle cycles
| 12sim_insts 5381 # Number of instructions simulated
13sim_ops 9748 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
18system.physmem.bytes_read::total 23104 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 361 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 512306933 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 302419070 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 814726003 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 512306933 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 512306933 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s)
32system.membus.throughput 814726003 # Throughput (bytes/s)
33system.membus.trans_dist::ReadReq 282 # Transaction distribution
34system.membus.trans_dist::ReadResp 282 # Transaction distribution
35system.membus.trans_dist::ReadExReq 79 # Transaction distribution
36system.membus.trans_dist::ReadExResp 79 # Transaction distribution
37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes)
38system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes)
39system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes)
40system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
41system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes)
42system.membus.tot_pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes)
43system.membus.data_through_bus 23104 # Total data (bytes)
44system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
45system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks)
46system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
47system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks)
48system.membus.respLayer1.utilization 11.5 # Layer utilization (%)
49system.cpu_clk_domain.clock 500 # Clock period in ticks
50system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
51system.cpu.workload.num_syscalls 11 # Number of system calls
52system.cpu.numCycles 56716 # number of cpu cycles simulated
53system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
54system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
55system.cpu.committedInsts 5381 # Number of instructions committed
56system.cpu.committedOps 9748 # Number of ops (including micro ops) committed
57system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses
58system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
59system.cpu.num_func_calls 209 # number of times a function call or return occured
60system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
61system.cpu.num_int_insts 9654 # number of integer instructions
62system.cpu.num_fp_insts 0 # number of float instructions
63system.cpu.num_int_register_reads 18335 # number of times the integer registers were read
64system.cpu.num_int_register_writes 7527 # number of times the integer registers were written
65system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
66system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
67system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read
68system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written
69system.cpu.num_mem_refs 1988 # number of memory refs
70system.cpu.num_load_insts 1053 # Number of load instructions
71system.cpu.num_store_insts 935 # Number of store instructions
72system.cpu.num_idle_cycles 0 # Number of idle cycles
73system.cpu.num_busy_cycles 56716 # Number of busy cycles
74system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
75system.cpu.idle_fraction 0 # Percentage of idle cycles
|
| 76system.cpu.Branches 1208 # Number of branches fetched
|
76system.cpu.icache.tags.replacements 0 # number of replacements
77system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use
78system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks.
79system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks.
80system.cpu.icache.tags.avg_refs 29.109649 # Average number of references to valid blocks.
81system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
82system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor
83system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy
84system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy
85system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id
86system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
87system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id
88system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id
89system.cpu.icache.tags.tag_accesses 13958 # Number of tag accesses
90system.cpu.icache.tags.data_accesses 13958 # Number of data accesses
91system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits
92system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits
93system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits
94system.cpu.icache.demand_hits::total 6637 # number of demand (read+write) hits
95system.cpu.icache.overall_hits::cpu.inst 6637 # number of overall hits
96system.cpu.icache.overall_hits::total 6637 # number of overall hits
97system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses
98system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses
99system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses
100system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses
101system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses
102system.cpu.icache.overall_misses::total 228 # number of overall misses
103system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498000 # number of ReadReq miss cycles
104system.cpu.icache.ReadReq_miss_latency::total 12498000 # number of ReadReq miss cycles
105system.cpu.icache.demand_miss_latency::cpu.inst 12498000 # number of demand (read+write) miss cycles
106system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles
107system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles
108system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles
109system.cpu.icache.ReadReq_accesses::cpu.inst 6865 # number of ReadReq accesses(hits+misses)
110system.cpu.icache.ReadReq_accesses::total 6865 # number of ReadReq accesses(hits+misses)
111system.cpu.icache.demand_accesses::cpu.inst 6865 # number of demand (read+write) accesses
112system.cpu.icache.demand_accesses::total 6865 # number of demand (read+write) accesses
113system.cpu.icache.overall_accesses::cpu.inst 6865 # number of overall (read+write) accesses
114system.cpu.icache.overall_accesses::total 6865 # number of overall (read+write) accesses
115system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033212 # miss rate for ReadReq accesses
116system.cpu.icache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses
117system.cpu.icache.demand_miss_rate::cpu.inst 0.033212 # miss rate for demand accesses
118system.cpu.icache.demand_miss_rate::total 0.033212 # miss rate for demand accesses
119system.cpu.icache.overall_miss_rate::cpu.inst 0.033212 # miss rate for overall accesses
120system.cpu.icache.overall_miss_rate::total 0.033212 # miss rate for overall accesses
121system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency
122system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency
123system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency
124system.cpu.icache.demand_avg_miss_latency::total 54815.789474 # average overall miss latency
125system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency
126system.cpu.icache.overall_avg_miss_latency::total 54815.789474 # average overall miss latency
127system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
128system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
129system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
130system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
131system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
132system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
133system.cpu.icache.fast_writes 0 # number of fast writes performed
134system.cpu.icache.cache_copies 0 # number of cache copies performed
135system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses
136system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
137system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses
138system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
139system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses
140system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses
141system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles
142system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles
143system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles
144system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles
145system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles
146system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles
147system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for ReadReq accesses
148system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033212 # mshr miss rate for ReadReq accesses
149system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for demand accesses
150system.cpu.icache.demand_mshr_miss_rate::total 0.033212 # mshr miss rate for demand accesses
151system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for overall accesses
152system.cpu.icache.overall_mshr_miss_rate::total 0.033212 # mshr miss rate for overall accesses
153system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency
154system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency
155system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
156system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
157system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
158system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
159system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
160system.cpu.l2cache.tags.replacements 0 # number of replacements
161system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use
162system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
163system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks.
164system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks.
165system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
166system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor
167system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor
168system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy
169system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy
170system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy
171system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id
172system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
173system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
174system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id
175system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses
176system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses
177system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
178system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
179system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
180system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
181system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
182system.cpu.l2cache.overall_hits::total 1 # number of overall hits
183system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses
184system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
185system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses
186system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses
187system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses
188system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
189system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
190system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses
191system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses
192system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
193system.cpu.l2cache.overall_misses::total 361 # number of overall misses
194system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles
195system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles
196system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles
197system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles
198system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles
199system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles
200system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles
201system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles
202system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles
203system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles
204system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles
205system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses)
206system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
207system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses)
208system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses)
209system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses)
210system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses
211system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses
212system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses
213system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses
214system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses
215system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses
216system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses
217system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
218system.cpu.l2cache.ReadReq_miss_rate::total 0.996466 # miss rate for ReadReq accesses
219system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
220system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
221system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses
222system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
223system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses
224system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses
225system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
226system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses
227system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
228system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
229system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
230system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
231system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
232system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
233system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
234system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
235system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
236system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
237system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
238system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
239system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
240system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
241system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
242system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
243system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
244system.cpu.l2cache.fast_writes 0 # number of fast writes performed
245system.cpu.l2cache.cache_copies 0 # number of cache copies performed
246system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses
247system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
248system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses
249system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses
250system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses
251system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses
252system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
253system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
254system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses
255system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
256system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses
257system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles
258system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
259system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles
260system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles
261system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles
262system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles
263system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
264system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles
265system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles
266system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
267system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles
268system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses
269system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
270system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses
271system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
272system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
273system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses
274system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
275system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses
276system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses
277system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
278system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses
279system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
280system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
281system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
282system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
283system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
284system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
285system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
286system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
287system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
288system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
289system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
290system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
291system.cpu.dcache.tags.replacements 0 # number of replacements
292system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use
293system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks.
294system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks.
295system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks.
296system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
297system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor
298system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
299system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy
300system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id
301system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
302system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
303system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id
304system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses
305system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses
306system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits
307system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits
308system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
309system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
310system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits
311system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits
312system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits
313system.cpu.dcache.overall_hits::total 1854 # number of overall hits
314system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
315system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
316system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
317system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
318system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
319system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
320system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
321system.cpu.dcache.overall_misses::total 134 # number of overall misses
322system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
323system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
324system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
325system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles
326system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles
327system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
328system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
329system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
330system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses)
331system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses)
332system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
333system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
334system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses
335system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses
336system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses
337system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses
338system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses
339system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses
340system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses
341system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses
342system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses
343system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses
344system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses
345system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses
346system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
347system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
348system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
349system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
350system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
351system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
352system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
353system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
354system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
355system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
356system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
357system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
358system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
359system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
360system.cpu.dcache.fast_writes 0 # number of fast writes performed
361system.cpu.dcache.cache_copies 0 # number of cache copies performed
362system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
363system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
364system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
365system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
366system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
367system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
368system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
369system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
370system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
371system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
372system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles
373system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles
374system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles
375system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
376system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
377system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
378system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses
379system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses
380system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
381system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses
382system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses
383system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses
384system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses
385system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses
386system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
387system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
388system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
389system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
390system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
391system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
392system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
393system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
394system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
395system.cpu.toL2Bus.throughput 816982862 # Throughput (bytes/s)
396system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution
397system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution
398system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution
399system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution
400system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes)
401system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes)
402system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes)
403system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes)
404system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes)
405system.cpu.toL2Bus.tot_pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes)
406system.cpu.toL2Bus.data_through_bus 23168 # Total data (bytes)
407system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
408system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
409system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
410system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks)
411system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%)
412system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks)
413system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
414
415---------- End Simulation Statistics ----------
| 77system.cpu.icache.tags.replacements 0 # number of replacements
78system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use
79system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks.
80system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks.
81system.cpu.icache.tags.avg_refs 29.109649 # Average number of references to valid blocks.
82system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
83system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor
84system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy
85system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy
86system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id
87system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
88system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id
89system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id
90system.cpu.icache.tags.tag_accesses 13958 # Number of tag accesses
91system.cpu.icache.tags.data_accesses 13958 # Number of data accesses
92system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits
93system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits
94system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits
95system.cpu.icache.demand_hits::total 6637 # number of demand (read+write) hits
96system.cpu.icache.overall_hits::cpu.inst 6637 # number of overall hits
97system.cpu.icache.overall_hits::total 6637 # number of overall hits
98system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses
99system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses
100system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses
101system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses
102system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses
103system.cpu.icache.overall_misses::total 228 # number of overall misses
104system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498000 # number of ReadReq miss cycles
105system.cpu.icache.ReadReq_miss_latency::total 12498000 # number of ReadReq miss cycles
106system.cpu.icache.demand_miss_latency::cpu.inst 12498000 # number of demand (read+write) miss cycles
107system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles
108system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles
109system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles
110system.cpu.icache.ReadReq_accesses::cpu.inst 6865 # number of ReadReq accesses(hits+misses)
111system.cpu.icache.ReadReq_accesses::total 6865 # number of ReadReq accesses(hits+misses)
112system.cpu.icache.demand_accesses::cpu.inst 6865 # number of demand (read+write) accesses
113system.cpu.icache.demand_accesses::total 6865 # number of demand (read+write) accesses
114system.cpu.icache.overall_accesses::cpu.inst 6865 # number of overall (read+write) accesses
115system.cpu.icache.overall_accesses::total 6865 # number of overall (read+write) accesses
116system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033212 # miss rate for ReadReq accesses
117system.cpu.icache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses
118system.cpu.icache.demand_miss_rate::cpu.inst 0.033212 # miss rate for demand accesses
119system.cpu.icache.demand_miss_rate::total 0.033212 # miss rate for demand accesses
120system.cpu.icache.overall_miss_rate::cpu.inst 0.033212 # miss rate for overall accesses
121system.cpu.icache.overall_miss_rate::total 0.033212 # miss rate for overall accesses
122system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency
123system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency
124system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency
125system.cpu.icache.demand_avg_miss_latency::total 54815.789474 # average overall miss latency
126system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency
127system.cpu.icache.overall_avg_miss_latency::total 54815.789474 # average overall miss latency
128system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
129system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
130system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
131system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
132system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
133system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
134system.cpu.icache.fast_writes 0 # number of fast writes performed
135system.cpu.icache.cache_copies 0 # number of cache copies performed
136system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses
137system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
138system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses
139system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
140system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses
141system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses
142system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles
143system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles
144system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles
145system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles
146system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles
147system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles
148system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for ReadReq accesses
149system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033212 # mshr miss rate for ReadReq accesses
150system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for demand accesses
151system.cpu.icache.demand_mshr_miss_rate::total 0.033212 # mshr miss rate for demand accesses
152system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for overall accesses
153system.cpu.icache.overall_mshr_miss_rate::total 0.033212 # mshr miss rate for overall accesses
154system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency
155system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency
156system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
157system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
158system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
159system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
160system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
161system.cpu.l2cache.tags.replacements 0 # number of replacements
162system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use
163system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
164system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks.
165system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks.
166system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
167system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor
168system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor
169system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy
170system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy
171system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy
172system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id
173system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
174system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
175system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id
176system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses
177system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses
178system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
179system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
180system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
181system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
182system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
183system.cpu.l2cache.overall_hits::total 1 # number of overall hits
184system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses
185system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
186system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses
187system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses
188system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses
189system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
190system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
191system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses
192system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses
193system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
194system.cpu.l2cache.overall_misses::total 361 # number of overall misses
195system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles
196system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles
197system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles
198system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles
199system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles
200system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles
201system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles
202system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles
203system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles
204system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles
205system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles
206system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses)
207system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
208system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses)
209system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses)
210system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses)
211system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses
212system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses
213system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses
214system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses
215system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses
216system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses
217system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses
218system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
219system.cpu.l2cache.ReadReq_miss_rate::total 0.996466 # miss rate for ReadReq accesses
220system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
221system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
222system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses
223system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
224system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses
225system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses
226system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
227system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses
228system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
229system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
230system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
231system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
232system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
233system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
234system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
235system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
236system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
237system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
238system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
239system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
240system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
241system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
242system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
243system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
244system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
245system.cpu.l2cache.fast_writes 0 # number of fast writes performed
246system.cpu.l2cache.cache_copies 0 # number of cache copies performed
247system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses
248system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
249system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses
250system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses
251system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses
252system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses
253system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
254system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
255system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses
256system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
257system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses
258system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles
259system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
260system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles
261system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles
262system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles
263system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles
264system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
265system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles
266system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles
267system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
268system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles
269system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses
270system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
271system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses
272system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
273system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
274system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses
275system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
276system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses
277system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses
278system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
279system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses
280system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
281system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
282system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
283system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
284system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
285system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
286system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
287system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
288system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
289system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
290system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
291system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
292system.cpu.dcache.tags.replacements 0 # number of replacements
293system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use
294system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks.
295system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks.
296system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks.
297system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
298system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor
299system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
300system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy
301system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id
302system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
303system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
304system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id
305system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses
306system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses
307system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits
308system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits
309system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
310system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
311system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits
312system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits
313system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits
314system.cpu.dcache.overall_hits::total 1854 # number of overall hits
315system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
316system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
317system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
318system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
319system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
320system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
321system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
322system.cpu.dcache.overall_misses::total 134 # number of overall misses
323system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
324system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
325system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
326system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles
327system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles
328system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
329system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
330system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
331system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses)
332system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses)
333system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
334system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
335system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses
336system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses
337system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses
338system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses
339system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses
340system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses
341system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses
342system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses
343system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses
344system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses
345system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses
346system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses
347system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
348system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
349system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
350system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
351system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
352system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
353system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
354system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
355system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
356system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
357system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
358system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
359system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
360system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
361system.cpu.dcache.fast_writes 0 # number of fast writes performed
362system.cpu.dcache.cache_copies 0 # number of cache copies performed
363system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
364system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
365system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
366system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
367system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
368system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
369system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
370system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
371system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
372system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
373system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles
374system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles
375system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles
376system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
377system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
378system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
379system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses
380system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses
381system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
382system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses
383system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses
384system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses
385system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses
386system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses
387system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
388system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
389system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
390system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
391system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
392system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
393system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
394system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
395system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
396system.cpu.toL2Bus.throughput 816982862 # Throughput (bytes/s)
397system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution
398system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution
399system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution
400system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution
401system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes)
402system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes)
403system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes)
404system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes)
405system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes)
406system.cpu.toL2Bus.tot_pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes)
407system.cpu.toL2Bus.data_through_bus 23168 # Total data (bytes)
408system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
409system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
410system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
411system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks)
412system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%)
413system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks)
414system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
415
416---------- End Simulation Statistics ----------
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