| config.ini (9213:5cab5448909c) | config.ini (9276:a5ede748a1d9) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 50 unchanged lines hidden (view full) --- 59[system.cpu.dcache] 60type=BaseCache 61addr_ranges=0:18446744073709551615 62assoc=2 63block_size=64 64clock=1 65forward_snoops=true 66hash_delay=1 | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 50 unchanged lines hidden (view full) --- 59[system.cpu.dcache] 60type=BaseCache 61addr_ranges=0:18446744073709551615 62assoc=2 63block_size=64 64clock=1 65forward_snoops=true 66hash_delay=1 |
| 67hit_latency=1000 |
|
| 67is_top_level=true | 68is_top_level=true |
| 68latency=1000 | |
| 69max_miss_count=0 70mshrs=10 71prefetch_on_access=false 72prefetcher=Null 73prioritizeRequests=false 74repl=Null | 69max_miss_count=0 70mshrs=10 71prefetch_on_access=false 72prefetcher=Null 73prioritizeRequests=false 74repl=Null |
| 75response_latency=1000 |
|
| 75size=262144 76subblock_size=0 77system=system 78tgts_per_mshr=5 79trace_addr=0 80two_queue=false 81write_buffers=8 82cpu_side=system.cpu.dcache_port --- 14 unchanged lines hidden (view full) --- 97[system.cpu.icache] 98type=BaseCache 99addr_ranges=0:18446744073709551615 100assoc=2 101block_size=64 102clock=1 103forward_snoops=true 104hash_delay=1 | 76size=262144 77subblock_size=0 78system=system 79tgts_per_mshr=5 80trace_addr=0 81two_queue=false 82write_buffers=8 83cpu_side=system.cpu.dcache_port --- 14 unchanged lines hidden (view full) --- 98[system.cpu.icache] 99type=BaseCache 100addr_ranges=0:18446744073709551615 101assoc=2 102block_size=64 103clock=1 104forward_snoops=true 105hash_delay=1 |
| 106hit_latency=1000 |
|
| 105is_top_level=true | 107is_top_level=true |
| 106latency=1000 | |
| 107max_miss_count=0 108mshrs=10 109prefetch_on_access=false 110prefetcher=Null 111prioritizeRequests=false 112repl=Null | 108max_miss_count=0 109mshrs=10 110prefetch_on_access=false 111prefetcher=Null 112prioritizeRequests=false 113repl=Null |
| 114response_latency=1000 |
|
| 113size=131072 114subblock_size=0 115system=system 116tgts_per_mshr=5 117trace_addr=0 118two_queue=false 119write_buffers=8 120cpu_side=system.cpu.icache_port --- 25 unchanged lines hidden (view full) --- 146[system.cpu.l2cache] 147type=BaseCache 148addr_ranges=0:18446744073709551615 149assoc=2 150block_size=64 151clock=1 152forward_snoops=true 153hash_delay=1 | 115size=131072 116subblock_size=0 117system=system 118tgts_per_mshr=5 119trace_addr=0 120two_queue=false 121write_buffers=8 122cpu_side=system.cpu.icache_port --- 25 unchanged lines hidden (view full) --- 148[system.cpu.l2cache] 149type=BaseCache 150addr_ranges=0:18446744073709551615 151assoc=2 152block_size=64 153clock=1 154forward_snoops=true 155hash_delay=1 |
| 156hit_latency=10000 |
|
| 154is_top_level=false | 157is_top_level=false |
| 155latency=10000 | |
| 156max_miss_count=0 157mshrs=10 158prefetch_on_access=false 159prefetcher=Null 160prioritizeRequests=false 161repl=Null | 158max_miss_count=0 159mshrs=10 160prefetch_on_access=false 161prefetcher=Null 162prioritizeRequests=false 163repl=Null |
| 164response_latency=10000 |
|
| 162size=2097152 163subblock_size=0 164system=system 165tgts_per_mshr=5 166trace_addr=0 167two_queue=false 168write_buffers=8 169cpu_side=system.cpu.toL2Bus.master[0] --- 38 unchanged lines hidden (view full) --- 208header_cycles=1 209use_default_range=false 210width=8 211master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 212slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 213 214[system.physmem] 215type=SimpleMemory | 165size=2097152 166subblock_size=0 167system=system 168tgts_per_mshr=5 169trace_addr=0 170two_queue=false 171write_buffers=8 172cpu_side=system.cpu.toL2Bus.master[0] --- 38 unchanged lines hidden (view full) --- 211header_cycles=1 212use_default_range=false 213width=8 214master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 215slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 216 217[system.physmem] 218type=SimpleMemory |
| 219bandwidth=73.000000 |
|
| 216clock=1 217conf_table_reported=false | 220clock=1 221conf_table_reported=false |
| 218file= | |
| 219in_addr_map=true 220latency=30000 221latency_var=0 222null=false 223range=0:134217727 224zero=false 225port=system.membus.master[0] 226 | 222in_addr_map=true 223latency=30000 224latency_var=0 225null=false 226range=0:134217727 227zero=false 228port=system.membus.master[0] 229 |