config.ini (10736:4433fb00fa7d) config.ini (10901:8cfa8dac39fe)
1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 79 unchanged lines hidden (view full) ---

88children=tags
89addr_ranges=0:18446744073709551615
90assoc=2
91clk_domain=system.cpu_clk_domain
92demand_mshr_reserve=1
93eventq_index=0
94forward_snoops=true
95hit_latency=2
1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 79 unchanged lines hidden (view full) ---

88children=tags
89addr_ranges=0:18446744073709551615
90assoc=2
91clk_domain=system.cpu_clk_domain
92demand_mshr_reserve=1
93eventq_index=0
94forward_snoops=true
95hit_latency=2
96is_top_level=true
96is_read_only=false
97max_miss_count=0
98mshrs=4
99prefetch_on_access=false
100prefetcher=Null
101response_latency=2
102sequential_access=false
103size=262144
104system=system
105tags=system.cpu.dcache.tags
106tgts_per_mshr=20
97max_miss_count=0
98mshrs=4
99prefetch_on_access=false
100prefetcher=Null
101response_latency=2
102sequential_access=false
103size=262144
104system=system
105tags=system.cpu.dcache.tags
106tgts_per_mshr=20
107two_queue=false
108write_buffers=8
109cpu_side=system.cpu.dcache_port
110mem_side=system.cpu.toL2Bus.slave[1]
111
112[system.cpu.dcache.tags]
113type=LRU
114assoc=2
115block_size=64

--- 23 unchanged lines hidden (view full) ---

139children=tags
140addr_ranges=0:18446744073709551615
141assoc=2
142clk_domain=system.cpu_clk_domain
143demand_mshr_reserve=1
144eventq_index=0
145forward_snoops=true
146hit_latency=2
107write_buffers=8
108cpu_side=system.cpu.dcache_port
109mem_side=system.cpu.toL2Bus.slave[1]
110
111[system.cpu.dcache.tags]
112type=LRU
113assoc=2
114block_size=64

--- 23 unchanged lines hidden (view full) ---

138children=tags
139addr_ranges=0:18446744073709551615
140assoc=2
141clk_domain=system.cpu_clk_domain
142demand_mshr_reserve=1
143eventq_index=0
144forward_snoops=true
145hit_latency=2
147is_top_level=true
146is_read_only=true
148max_miss_count=0
149mshrs=4
150prefetch_on_access=false
151prefetcher=Null
152response_latency=2
153sequential_access=false
154size=131072
155system=system
156tags=system.cpu.icache.tags
157tgts_per_mshr=20
147max_miss_count=0
148mshrs=4
149prefetch_on_access=false
150prefetcher=Null
151response_latency=2
152sequential_access=false
153size=131072
154system=system
155tags=system.cpu.icache.tags
156tgts_per_mshr=20
158two_queue=false
159write_buffers=8
160cpu_side=system.cpu.icache_port
161mem_side=system.cpu.toL2Bus.slave[0]
162
163[system.cpu.icache.tags]
164type=LRU
165assoc=2
166block_size=64

--- 39 unchanged lines hidden (view full) ---

206children=tags
207addr_ranges=0:18446744073709551615
208assoc=8
209clk_domain=system.cpu_clk_domain
210demand_mshr_reserve=1
211eventq_index=0
212forward_snoops=true
213hit_latency=20
157write_buffers=8
158cpu_side=system.cpu.icache_port
159mem_side=system.cpu.toL2Bus.slave[0]
160
161[system.cpu.icache.tags]
162type=LRU
163assoc=2
164block_size=64

--- 39 unchanged lines hidden (view full) ---

204children=tags
205addr_ranges=0:18446744073709551615
206assoc=8
207clk_domain=system.cpu_clk_domain
208demand_mshr_reserve=1
209eventq_index=0
210forward_snoops=true
211hit_latency=20
214is_top_level=false
212is_read_only=false
215max_miss_count=0
216mshrs=20
217prefetch_on_access=false
218prefetcher=Null
219response_latency=20
220sequential_access=false
221size=2097152
222system=system
223tags=system.cpu.l2cache.tags
224tgts_per_mshr=12
213max_miss_count=0
214mshrs=20
215prefetch_on_access=false
216prefetcher=Null
217response_latency=20
218sequential_access=false
219size=2097152
220system=system
221tags=system.cpu.l2cache.tags
222tgts_per_mshr=12
225two_queue=false
226write_buffers=8
227cpu_side=system.cpu.toL2Bus.master[0]
228mem_side=system.membus.slave[1]
229
230[system.cpu.l2cache.tags]
231type=LRU
232assoc=8
233block_size=64

--- 97 unchanged lines hidden ---
223write_buffers=8
224cpu_side=system.cpu.toL2Bus.master[0]
225mem_side=system.membus.slave[1]
226
227[system.cpu.l2cache.tags]
228type=LRU
229assoc=8
230block_size=64

--- 97 unchanged lines hidden ---