1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 150 unchanged lines hidden (view full) --- 159tgts_per_mshr=5 160trace_addr=0 161two_queue=false 162write_buffers=8 163cpu_side=system.cpu.toL2Bus.master[0] 164mem_side=system.membus.slave[1] 165 166[system.cpu.toL2Bus] |
167type=CoherentBus |
168block_size=64 |
169clock=1000 170header_cycles=1 171use_default_range=false 172width=64 173master=system.cpu.l2cache.cpu_side 174slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 175 176[system.cpu.tracer] 177type=ExeTracer 178 179[system.cpu.workload] 180type=LiveProcess 181cmd=hello 182cwd= 183egid=100 184env= 185errout=cerr 186euid=100 |
187executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello |
188gid=100 189input=cin 190max_stack_size=67108864 191output=cout 192pid=100 193ppid=99 194simpoint=0 195system=system 196uid=100 197 198[system.membus] |
199type=CoherentBus |
200block_size=64 |
201clock=1000 202header_cycles=1 203use_default_range=false 204width=64 205master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave 206slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 207 208[system.physmem] 209type=SimpleMemory 210conf_table_reported=false 211file= 212in_addr_map=true 213latency=30000 214latency_var=0 215null=false 216range=0:134217727 217zero=false 218port=system.membus.master[0] 219 |