1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem |
26mmap_using_noreserve=false |
27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 --- 201 unchanged lines hidden (view full) --- 236hit_latency=20 237sequential_access=false 238size=2097152 239 240[system.cpu.toL2Bus] 241type=CoherentXBar 242clk_domain=system.cpu_clk_domain 243eventq_index=0 |
244forward_latency=0 245frontend_latency=1 246response_latency=1 |
247snoop_filter=Null |
248snoop_response_latency=1 |
249system=system 250use_default_range=false 251width=32 252master=system.cpu.l2cache.cpu_side 253slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 254 255[system.cpu.tracer] 256type=ExeTracer --- 37 unchanged lines hidden (view full) --- 294eventq_index=0 295sys_clk_domain=system.clk_domain 296transition_latency=100000000 297 298[system.membus] 299type=CoherentXBar 300clk_domain=system.clk_domain 301eventq_index=0 |
302forward_latency=4 303frontend_latency=3 304response_latency=2 |
305snoop_filter=Null |
306snoop_response_latency=4 |
307system=system 308use_default_range=false |
309width=16 |
310master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 311slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 312 313[system.physmem] 314type=SimpleMemory 315bandwidth=73.000000 316clk_domain=system.clk_domain 317conf_table_reported=true --- 13 unchanged lines hidden --- |