| stats.txt (10220:9eab5efc02e8) | stats.txt (10488:7c27480a5031) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000122 # Number of seconds simulated 4sim_ticks 121759 # Number of ticks simulated 5final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000 # Frequency of simulated ticks 7host_inst_rate 47256 # Simulator instruction rate (inst/s) 8host_op_rate 85597 # Simulator op (including micro ops) rate (op/s) --- 7 unchanged lines hidden (view full) --- 16system.ruby.clk_domain.clock 1 # Clock period in ticks 17system.ruby.delayHist::bucket_size 1 # delay histogram for all message 18system.ruby.delayHist::max_bucket 9 # delay histogram for all message 19system.ruby.delayHist::samples 2750 # delay histogram for all message 20system.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 21system.ruby.delayHist::total 2750 # delay histogram for all message 22system.ruby.outstanding_req_hist::bucket_size 1 23system.ruby.outstanding_req_hist::max_bucket 9 | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000122 # Number of seconds simulated 4sim_ticks 121759 # Number of ticks simulated 5final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000 # Frequency of simulated ticks 7host_inst_rate 47256 # Simulator instruction rate (inst/s) 8host_op_rate 85597 # Simulator op (including micro ops) rate (op/s) --- 7 unchanged lines hidden (view full) --- 16system.ruby.clk_domain.clock 1 # Clock period in ticks 17system.ruby.delayHist::bucket_size 1 # delay histogram for all message 18system.ruby.delayHist::max_bucket 9 # delay histogram for all message 19system.ruby.delayHist::samples 2750 # delay histogram for all message 20system.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 21system.ruby.delayHist::total 2750 # delay histogram for all message 22system.ruby.outstanding_req_hist::bucket_size 1 23system.ruby.outstanding_req_hist::max_bucket 9 |
| 24system.ruby.outstanding_req_hist::samples 8853 | 24system.ruby.outstanding_req_hist::samples 8852 |
| 25system.ruby.outstanding_req_hist::mean 1 26system.ruby.outstanding_req_hist::gmean 1 | 25system.ruby.outstanding_req_hist::mean 1 26system.ruby.outstanding_req_hist::gmean 1 |
| 27system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8853 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 28system.ruby.outstanding_req_hist::total 8853 | 27system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8852 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 28system.ruby.outstanding_req_hist::total 8852 |
| 29system.ruby.latency_hist::bucket_size 16 30system.ruby.latency_hist::max_bucket 159 31system.ruby.latency_hist::samples 8852 32system.ruby.latency_hist::mean 12.754971 33system.ruby.latency_hist::gmean 4.846146 34system.ruby.latency_hist::stdev 22.865469 35system.ruby.latency_hist | 7475 84.44% 84.44% | 0 0.00% 84.44% | 0 0.00% 84.44% | 329 3.72% 88.16% | 977 11.04% 99.20% | 69 0.78% 99.98% | 1 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 36system.ruby.latency_hist::total 8852 --- 84 unchanged lines hidden (view full) --- 121system.cpu.num_int_register_writes 7527 # number of times the integer registers were written 122system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 123system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 124system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read 125system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written 126system.cpu.num_mem_refs 1988 # number of memory refs 127system.cpu.num_load_insts 1053 # Number of load instructions 128system.cpu.num_store_insts 935 # Number of store instructions | 29system.ruby.latency_hist::bucket_size 16 30system.ruby.latency_hist::max_bucket 159 31system.ruby.latency_hist::samples 8852 32system.ruby.latency_hist::mean 12.754971 33system.ruby.latency_hist::gmean 4.846146 34system.ruby.latency_hist::stdev 22.865469 35system.ruby.latency_hist | 7475 84.44% 84.44% | 0 0.00% 84.44% | 0 0.00% 84.44% | 329 3.72% 88.16% | 977 11.04% 99.20% | 69 0.78% 99.98% | 1 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 36system.ruby.latency_hist::total 8852 --- 84 unchanged lines hidden (view full) --- 121system.cpu.num_int_register_writes 7527 # number of times the integer registers were written 122system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 123system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 124system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read 125system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written 126system.cpu.num_mem_refs 1988 # number of memory refs 127system.cpu.num_load_insts 1053 # Number of load instructions 128system.cpu.num_store_insts 935 # Number of store instructions |
| 129system.cpu.num_idle_cycles 0 # Number of idle cycles 130system.cpu.num_busy_cycles 121759 # Number of busy cycles 131system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 132system.cpu.idle_fraction 0 # Percentage of idle cycles | 129system.cpu.num_idle_cycles 0.999992 # Number of idle cycles 130system.cpu.num_busy_cycles 121758.000008 # Number of busy cycles 131system.cpu.not_idle_fraction 0.999992 # Percentage of non-idle cycles 132system.cpu.idle_fraction 0.000008 # Percentage of idle cycles |
| 133system.cpu.Branches 1208 # Number of branches fetched 134system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 135system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction 136system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction 137system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction 138system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction 139system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction 140system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction --- 252 unchanged lines hidden --- | 133system.cpu.Branches 1208 # Number of branches fetched 134system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 135system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction 136system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction 137system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction 138system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction 139system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction 140system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction --- 252 unchanged lines hidden --- |