19d18
< physmem=system.physmem
29c28
< system_port=system.sys_port_proxy.port[0]
---
> system_port=system.sys_port_proxy.slave[0]
57,58c56,57
< dcache_port=system.l1_cntrl0.sequencer.port[1]
< icache_port=system.l1_cntrl0.sequencer.port[0]
---
> dcache_port=system.l1_cntrl0.sequencer.slave[1]
> icache_port=system.l1_cntrl0.sequencer.slave[0]
69c68
< port=system.l1_cntrl0.sequencer.port[3]
---
> port=system.l1_cntrl0.sequencer.slave[3]
77,78c76,78
< int_port=system.l1_cntrl0.sequencer.port[5]
< pio=system.l1_cntrl0.sequencer.port[4]
---
> int_master=system.l1_cntrl0.sequencer.slave[4]
> int_slave=system.l1_cntrl0.sequencer.master[1]
> pio=system.l1_cntrl0.sequencer.master[0]
89c89
< port=system.l1_cntrl0.sequencer.port[2]
---
> port=system.l1_cntrl0.sequencer.slave[2]
188d187
< physmem=system.physmem
189a189,191
> support_data_reqs=true
> support_inst_reqs=true
> system=system
193,194c195,196
< physMemPort=system.physmem.port[0]
< port=system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
---
> master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave
> slave=system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
197c199,200
< type=PhysicalMemory
---
> type=SimpleMemory
> conf_table_reported=false
198a202
> in_addr_map=true
204d207
< port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
295d297
< physmem=system.physmem
296a299,301
> support_data_reqs=true
> support_inst_reqs=true
> system=system
300,301c305
< physMemPort=system.physmem.port[1]
< port=system.system_port
---
> slave=system.system_port