13c13
< children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
---
> children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
25c25
< memories=system.physmem
---
> memories=system.mem_ctrls
172,174c172,203
< [system.physmem]
< type=SimpleMemory
< bandwidth=0.000000
---
> [system.mem_ctrls]
> type=DRAMCtrl
> IDD0=0.075000
> IDD02=0.000000
> IDD2N=0.050000
> IDD2N2=0.000000
> IDD2P0=0.000000
> IDD2P02=0.000000
> IDD2P1=0.000000
> IDD2P12=0.000000
> IDD3N=0.057000
> IDD3N2=0.000000
> IDD3P0=0.000000
> IDD3P02=0.000000
> IDD3P1=0.000000
> IDD3P12=0.000000
> IDD4R=0.187000
> IDD4R2=0.000000
> IDD4W=0.165000
> IDD4W2=0.000000
> IDD5=0.220000
> IDD52=0.000000
> IDD6=0.000000
> IDD62=0.000000
> VDD=1.500000
> VDD2=0.000000
> activation_limit=4
> addr_mapping=RoRaBaChCo
> bank_groups_per_rank=0
> banks_per_rank=8
> burst_length=8
> channels=1
176a206,210
> device_bus_width=8
> device_rowbuffer_size=1024
> device_size=536870912
> devices_per_rank=8
> dll=true
179,182c213,247
< latency=30
< latency_var=0
< null=true
< range=0:134217727
---
> max_accesses_per_row=16
> mem_sched_policy=frfcfs
> min_writes_per_switch=16
> null=false
> page_policy=open_adaptive
> range=0:268435455
> ranks_per_channel=2
> read_buffer_size=32
> static_backend_latency=10
> static_frontend_latency=10
> tBURST=5
> tCCD_L=0
> tCK=1
> tCL=14
> tCS=3
> tRAS=35
> tRCD=14
> tREFI=7800
> tRFC=260
> tRP=14
> tRRD=6
> tRRD_L=0
> tRTP=8
> tRTW=3
> tWR=15
> tWTR=8
> tXAW=30
> tXP=0
> tXPDLL=0
> tXS=0
> tXSDLL=0
> write_buffer_size=64
> write_high_thresh_perc=85
> write_low_thresh_perc=50
> port=system.ruby.dir_cntrl0.memory
192,193c257
< mem_size=268435456
< no_mem_vec=false
---
> memory_size_bits=48
194a259
> phys_mem=Null
208c273
< children=directory memBuffer
---
> children=directory
215d279
< memBuffer=system.ruby.dir_cntrl0.memBuffer
217d280
< peer=Null
219a283,284
> system=system
> to_memory_controller_latency=1
224a290
> memory=system.mem_ctrls.port
231d296
< map_levels=4
234d298
< use_map=false
237,259d300
< [system.ruby.dir_cntrl0.memBuffer]
< type=RubyMemoryControl
< bank_bit_0=8
< bank_busy_time=11
< bank_queue_size=12
< banks_per_rank=8
< basic_bus_busy_time=2
< clk_domain=system.ruby.memctrl_clk_domain
< dimm_bit_0=12
< dimms_per_channel=2
< eventq_index=0
< mem_ctl_latency=12
< mem_fixed_delay=0
< mem_random_arbitrate=0
< rank_bit_0=11
< rank_rank_delay=1
< ranks_per_dimm=2
< read_write_delay=2
< refresh_period=1560
< ruby_system=system.ruby
< tFaw=0
< version=0
<
271d311
< peer=Null
275a316
> system=system
300c341
< access_phys_mem=false
---
> access_backing_store=false
405c446
< access_phys_mem=true
---
> access_backing_store=false