| stats.txt (9702:094d0280e481) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000016 # Number of seconds simulated 4sim_ticks 16021500 # Number of ticks simulated 5final_tick 16021500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000020 # Number of seconds simulated 4sim_ticks 19589000 # Number of ticks simulated 5final_tick 19589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 25477 # Simulator instruction rate (inst/s) 8host_op_rate 46153 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 75857343 # Simulator tick rate (ticks/s) 10host_mem_usage 290184 # Number of bytes of host memory used 11host_seconds 0.21 # Real time elapsed on the host | 7host_inst_rate 1364 # Simulator instruction rate (inst/s) 8host_op_rate 2472 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4967212 # Simulator tick rate (ticks/s) 10host_mem_usage 245432 # Number of bytes of host memory used 11host_seconds 3.94 # Real time elapsed on the host |
| 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated | 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9152 # Number of bytes read from this memory 16system.physmem.bytes_read::total 26944 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 143 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 421 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1110507755 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 571232406 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1681740162 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1110507755 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1110507755 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1110507755 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 571232406 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1681740162 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 422 # Total number of read requests seen | 14system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory 16system.physmem.bytes_read::total 26432 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 413 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 891929144 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 457399561 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1349328705 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 891929144 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 891929144 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 891929144 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 457399561 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1349328705 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 414 # Total number of read requests seen |
| 31system.physmem.writeReqs 0 # Total number of write requests seen | 31system.physmem.writeReqs 0 # Total number of write requests seen |
| 32system.physmem.cpureqs 422 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 26944 # Total number of bytes read from memory | 32system.physmem.cpureqs 414 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 26432 # Total number of bytes read from memory |
| 34system.physmem.bytesWritten 0 # Total number of bytes written to memory | 34system.physmem.bytesWritten 0 # Total number of bytes written to memory |
| 35system.physmem.bytesConsumedRd 26944 # bytesRead derated as per pkt->getSize() | 35system.physmem.bytesConsumedRd 26432 # bytesRead derated as per pkt->getSize() |
| 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed | 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed |
| 39system.physmem.perBankRdReqs::0 45 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 35 # Track reads on a per bank basis | 39system.physmem.perBankRdReqs::0 33 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 5 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 50 # Track reads on a per bank basis |
| 44system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis | 44system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis |
| 45system.physmem.perBankRdReqs::6 26 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 33 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 24 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 7 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 33 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 12 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 3 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 24 # Track reads on a per bank basis | 45system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 36 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 63 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 2 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 6 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis |
| 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 16004000 # Total gap between requests | 73system.physmem.totGap 19541000 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 80system.physmem.readPktSize::6 422 # Categorize read packet sizes | 80system.physmem.readPktSize::6 414 # Categorize read packet sizes |
| 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes | 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes |
| 88system.physmem.rdQLenPdf::0 233 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see | 88system.physmem.rdQLenPdf::0 249 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 3 # What read queue length does an incoming req see |
| 92system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 44 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 92system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 44 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 152system.physmem.totQLat 2229750 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 13029750 # Sum of mem lat for all requests 154system.physmem.totBusLat 2110000 # Total cycles spent in databus access 155system.physmem.totBankLat 8690000 # Total cycles spent in bank access 156system.physmem.avgQLat 5283.77 # Average queueing delay per request 157system.physmem.avgBankLat 20592.42 # Average bank access latency per request | 152system.physmem.bytesPerActivate::samples 87 # Bytes accessed per row activation 153system.physmem.bytesPerActivate::mean 216.275862 # Bytes accessed per row activation 154system.physmem.bytesPerActivate::gmean 131.153640 # Bytes accessed per row activation 155system.physmem.bytesPerActivate::stdev 325.056442 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::64 43 49.43% 49.43% # Bytes accessed per row activation 157system.physmem.bytesPerActivate::128 13 14.94% 64.37% # Bytes accessed per row activation 158system.physmem.bytesPerActivate::192 9 10.34% 74.71% # Bytes accessed per row activation 159system.physmem.bytesPerActivate::256 4 4.60% 79.31% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::320 7 8.05% 87.36% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::384 3 3.45% 90.80% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::512 1 1.15% 91.95% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::640 1 1.15% 93.10% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::704 1 1.15% 94.25% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::768 1 1.15% 95.40% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::960 2 2.30% 97.70% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::1344 1 1.15% 98.85% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::2368 1 1.15% 100.00% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::total 87 # Bytes accessed per row activation 170system.physmem.totQLat 1394000 # Total cycles spent in queuing delays 171system.physmem.totMemAccLat 11081500 # Sum of mem lat for all requests 172system.physmem.totBusLat 2070000 # Total cycles spent in databus access 173system.physmem.totBankLat 7617500 # Total cycles spent in bank access 174system.physmem.avgQLat 3367.15 # Average queueing delay per request 175system.physmem.avgBankLat 18399.76 # Average bank access latency per request |
| 158system.physmem.avgBusLat 5000.00 # Average bus latency per request | 176system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 159system.physmem.avgMemAccLat 30876.18 # Average memory access latency 160system.physmem.avgRdBW 1681.74 # Average achieved read bandwidth in MB/s | 177system.physmem.avgMemAccLat 26766.91 # Average memory access latency 178system.physmem.avgRdBW 1349.33 # Average achieved read bandwidth in MB/s |
| 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s | 179system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 162system.physmem.avgConsumedRdBW 1681.74 # Average consumed read bandwidth in MB/s | 180system.physmem.avgConsumedRdBW 1349.33 # Average consumed read bandwidth in MB/s |
| 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s | 181system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 182system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s |
| 165system.physmem.busUtil 13.14 # Data bus utilization in percentage 166system.physmem.avgRdQLen 0.81 # Average read queue length over time | 183system.physmem.busUtil 10.54 # Data bus utilization in percentage 184system.physmem.avgRdQLen 0.57 # Average read queue length over time |
| 167system.physmem.avgWrQLen 0.00 # Average write queue length over time | 185system.physmem.avgWrQLen 0.00 # Average write queue length over time |
| 168system.physmem.readRowHits 302 # Number of row buffer hits during reads | 186system.physmem.readRowHits 327 # Number of row buffer hits during reads |
| 169system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 187system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 170system.physmem.readRowHitRate 71.56 # Row buffer hit rate for reads | 188system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads |
| 171system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 189system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 172system.physmem.avgGap 37924.17 # Average gap between requests 173system.cpu.branchPred.lookups 3090 # Number of BP lookups 174system.cpu.branchPred.condPredicted 3090 # Number of conditional branches predicted | 190system.physmem.avgGap 47200.48 # Average gap between requests 191system.membus.throughput 1349328705 # Throughput (bytes/s) 192system.membus.trans_dist::ReadReq 337 # Transaction distribution 193system.membus.trans_dist::ReadResp 336 # Transaction distribution 194system.membus.trans_dist::ReadExReq 77 # Transaction distribution 195system.membus.trans_dist::ReadExResp 77 # Transaction distribution 196system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 827 # Packet count per connected master and slave (bytes) 197system.membus.pkt_count_system.cpu.l2cache.mem_side::total 827 # Packet count per connected master and slave (bytes) 198system.membus.pkt_count::system.physmem.port 827 # Packet count per connected master and slave (bytes) 199system.membus.pkt_count::total 827 # Packet count per connected master and slave (bytes) 200system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26432 # Cumulative packet size per connected master and slave (bytes) 201system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26432 # Cumulative packet size per connected master and slave (bytes) 202system.membus.tot_pkt_size::system.physmem.port 26432 # Cumulative packet size per connected master and slave (bytes) 203system.membus.tot_pkt_size::total 26432 # Cumulative packet size per connected master and slave (bytes) 204system.membus.data_through_bus 26432 # Total data (bytes) 205system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 206system.membus.reqLayer0.occupancy 498000 # Layer occupancy (ticks) 207system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) 208system.membus.respLayer1.occupancy 3864000 # Layer occupancy (ticks) 209system.membus.respLayer1.utilization 19.7 # Layer utilization (%) 210system.cpu.branchPred.lookups 3089 # Number of BP lookups 211system.cpu.branchPred.condPredicted 3089 # Number of conditional branches predicted |
| 175system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect | 212system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect |
| 176system.cpu.branchPred.BTBLookups 2310 # Number of BTB lookups 177system.cpu.branchPred.BTBHits 714 # Number of BTB hits | 213system.cpu.branchPred.BTBLookups 2286 # Number of BTB lookups 214system.cpu.branchPred.BTBHits 726 # Number of BTB hits |
| 178system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 215system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 179system.cpu.branchPred.BTBHitPct 30.909091 # BTB Hit Percentage 180system.cpu.branchPred.usedRAS 211 # Number of times the RAS was used to get a target. 181system.cpu.branchPred.RASInCorrect 78 # Number of incorrect RAS predictions. | 216system.cpu.branchPred.BTBHitPct 31.758530 # BTB Hit Percentage 217system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. 218system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions. |
| 182system.cpu.workload.num_syscalls 11 # Number of system calls | 219system.cpu.workload.num_syscalls 11 # Number of system calls |
| 183system.cpu.numCycles 32044 # number of cpu cycles simulated | 220system.cpu.numCycles 39179 # number of cpu cycles simulated |
| 184system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 185system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 221system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 222system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 186system.cpu.fetch.icacheStallCycles 9523 # Number of cycles fetch is stalled on an Icache miss 187system.cpu.fetch.Insts 14230 # Number of instructions fetch has processed 188system.cpu.fetch.Branches 3090 # Number of branches that fetch encountered 189system.cpu.fetch.predictedBranches 925 # Number of branches that fetch has predicted taken 190system.cpu.fetch.Cycles 3948 # Number of cycles fetch has run and was not squashing or blocked 191system.cpu.fetch.SquashCycles 2389 # Number of cycles fetch has spent squashing 192system.cpu.fetch.BlockedCycles 3636 # Number of cycles fetch has spent blocked 193system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 194system.cpu.fetch.PendingTrapStallCycles 340 # Number of stall cycles due to pending traps 195system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched 196system.cpu.fetch.IcacheSquashes 259 # Number of outstanding Icache misses that were squashed 197system.cpu.fetch.rateDist::samples 19279 # Number of instructions fetched each cycle (Total) 198system.cpu.fetch.rateDist::mean 1.312568 # Number of instructions fetched each cycle (Total) 199system.cpu.fetch.rateDist::stdev 2.813131 # Number of instructions fetched each cycle (Total) | 223system.cpu.fetch.icacheStallCycles 10273 # Number of cycles fetch is stalled on an Icache miss 224system.cpu.fetch.Insts 14155 # Number of instructions fetch has processed 225system.cpu.fetch.Branches 3089 # Number of branches that fetch encountered 226system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken 227system.cpu.fetch.Cycles 3944 # Number of cycles fetch has run and was not squashing or blocked 228system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing 229system.cpu.fetch.BlockedCycles 5406 # Number of cycles fetch has spent blocked 230system.cpu.fetch.MiscStallCycles 59 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 231system.cpu.fetch.PendingTrapStallCycles 375 # Number of stall cycles due to pending traps 232system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR 233system.cpu.fetch.CacheLines 1981 # Number of cache lines fetched 234system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed 235system.cpu.fetch.rateDist::samples 21925 # Number of instructions fetched each cycle (Total) 236system.cpu.fetch.rateDist::mean 1.151015 # Number of instructions fetched each cycle (Total) 237system.cpu.fetch.rateDist::stdev 2.666624 # Number of instructions fetched each cycle (Total) |
| 200system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 238system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 201system.cpu.fetch.rateDist::0 15433 80.05% 80.05% # Number of instructions fetched each cycle (Total) 202system.cpu.fetch.rateDist::1 214 1.11% 81.16% # Number of instructions fetched each cycle (Total) 203system.cpu.fetch.rateDist::2 145 0.75% 81.91% # Number of instructions fetched each cycle (Total) 204system.cpu.fetch.rateDist::3 217 1.13% 83.04% # Number of instructions fetched each cycle (Total) 205system.cpu.fetch.rateDist::4 192 1.00% 84.03% # Number of instructions fetched each cycle (Total) 206system.cpu.fetch.rateDist::5 169 0.88% 84.91% # Number of instructions fetched each cycle (Total) 207system.cpu.fetch.rateDist::6 290 1.50% 86.42% # Number of instructions fetched each cycle (Total) 208system.cpu.fetch.rateDist::7 155 0.80% 87.22% # Number of instructions fetched each cycle (Total) 209system.cpu.fetch.rateDist::8 2464 12.78% 100.00% # Number of instructions fetched each cycle (Total) | 239system.cpu.fetch.rateDist::0 18081 82.47% 82.47% # Number of instructions fetched each cycle (Total) 240system.cpu.fetch.rateDist::1 213 0.97% 83.44% # Number of instructions fetched each cycle (Total) 241system.cpu.fetch.rateDist::2 143 0.65% 84.09% # Number of instructions fetched each cycle (Total) 242system.cpu.fetch.rateDist::3 223 1.02% 85.11% # Number of instructions fetched each cycle (Total) 243system.cpu.fetch.rateDist::4 185 0.84% 85.95% # Number of instructions fetched each cycle (Total) 244system.cpu.fetch.rateDist::5 200 0.91% 86.86% # Number of instructions fetched each cycle (Total) 245system.cpu.fetch.rateDist::6 277 1.26% 88.13% # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.rateDist::7 158 0.72% 88.85% # Number of instructions fetched each cycle (Total) 247system.cpu.fetch.rateDist::8 2445 11.15% 100.00% # Number of instructions fetched each cycle (Total) |
| 210system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 211system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 212system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 248system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 250system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 213system.cpu.fetch.rateDist::total 19279 # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.branchRate 0.096430 # Number of branch fetches per cycle 215system.cpu.fetch.rate 0.444077 # Number of inst fetches per cycle 216system.cpu.decode.IdleCycles 10008 # Number of cycles decode is idle 217system.cpu.decode.BlockedCycles 3780 # Number of cycles decode is blocked 218system.cpu.decode.RunCycles 3579 # Number of cycles decode is running 219system.cpu.decode.UnblockCycles 127 # Number of cycles decode is unblocking 220system.cpu.decode.SquashCycles 1785 # Number of cycles decode is squashing 221system.cpu.decode.DecodedInsts 24215 # Number of instructions handled by decode 222system.cpu.rename.SquashCycles 1785 # Number of cycles rename is squashing 223system.cpu.rename.IdleCycles 10348 # Number of cycles rename is idle 224system.cpu.rename.BlockCycles 2654 # Number of cycles rename is blocking 225system.cpu.rename.serializeStallCycles 416 # count of cycles rename stalled for serializing inst 226system.cpu.rename.RunCycles 3350 # Number of cycles rename is running 227system.cpu.rename.UnblockCycles 726 # Number of cycles rename is unblocking 228system.cpu.rename.RenamedInsts 22708 # Number of instructions processed by rename 229system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full 230system.cpu.rename.IQFullEvents 31 # Number of times rename has blocked due to IQ full 231system.cpu.rename.LSQFullEvents 620 # Number of times rename has blocked due to LSQ full 232system.cpu.rename.RenamedOperands 25234 # Number of destination operands rename has renamed 233system.cpu.rename.RenameLookups 54863 # Number of register rename lookups that rename has made 234system.cpu.rename.int_rename_lookups 54847 # Number of integer rename lookups | 251system.cpu.fetch.rateDist::total 21925 # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.branchRate 0.078843 # Number of branch fetches per cycle 253system.cpu.fetch.rate 0.361290 # Number of inst fetches per cycle 254system.cpu.decode.IdleCycles 11051 # Number of cycles decode is idle 255system.cpu.decode.BlockedCycles 5299 # Number of cycles decode is blocked 256system.cpu.decode.RunCycles 3578 # Number of cycles decode is running 257system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking 258system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing 259system.cpu.decode.DecodedInsts 24188 # Number of instructions handled by decode 260system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing 261system.cpu.rename.IdleCycles 11417 # Number of cycles rename is idle 262system.cpu.rename.BlockCycles 3782 # Number of cycles rename is blocking 263system.cpu.rename.serializeStallCycles 753 # count of cycles rename stalled for serializing inst 264system.cpu.rename.RunCycles 3333 # Number of cycles rename is running 265system.cpu.rename.UnblockCycles 783 # Number of cycles rename is unblocking 266system.cpu.rename.RenamedInsts 22649 # Number of instructions processed by rename 267system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full 268system.cpu.rename.IQFullEvents 35 # Number of times rename has blocked due to IQ full 269system.cpu.rename.LSQFullEvents 669 # Number of times rename has blocked due to LSQ full 270system.cpu.rename.RenamedOperands 25230 # Number of destination operands rename has renamed 271system.cpu.rename.RenameLookups 54980 # Number of register rename lookups that rename has made 272system.cpu.rename.int_rename_lookups 54964 # Number of integer rename lookups |
| 235system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups 236system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed | 273system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups 274system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed |
| 237system.cpu.rename.UndoneMaps 14171 # Number of HB maps that are undone due to squashing 238system.cpu.rename.serializingInsts 30 # count of serializing insts renamed 239system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed 240system.cpu.rename.skidInsts 1819 # count of insts added to the skid buffer 241system.cpu.memDep0.insertedLoads 2277 # Number of loads inserted to the mem dependence unit. 242system.cpu.memDep0.insertedStores 1616 # Number of stores inserted to the mem dependence unit. 243system.cpu.memDep0.conflictingLoads 17 # Number of conflicting loads. | 275system.cpu.rename.UndoneMaps 14167 # Number of HB maps that are undone due to squashing 276system.cpu.rename.serializingInsts 32 # count of serializing insts renamed 277system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed 278system.cpu.rename.skidInsts 2073 # count of insts added to the skid buffer 279system.cpu.memDep0.insertedLoads 2281 # Number of loads inserted to the mem dependence unit. 280system.cpu.memDep0.insertedStores 1568 # Number of stores inserted to the mem dependence unit. 281system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. |
| 244system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. | 282system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. |
| 245system.cpu.iq.iqInstsAdded 20098 # Number of instructions added to the IQ (excludes non-spec) 246system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ 247system.cpu.iq.iqInstsIssued 17004 # Number of instructions issued 248system.cpu.iq.iqSquashedInstsIssued 251 # Number of squashed instructions issued 249system.cpu.iq.iqSquashedInstsExamined 9536 # Number of squashed instructions iterated over during squash; mainly for profiling 250system.cpu.iq.iqSquashedOperandsExamined 13688 # Number of squashed operands that are examined and possibly removed from graph 251system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed 252system.cpu.iq.issued_per_cycle::samples 19279 # Number of insts issued each cycle 253system.cpu.iq.issued_per_cycle::mean 0.881996 # Number of insts issued each cycle 254system.cpu.iq.issued_per_cycle::stdev 1.736426 # Number of insts issued each cycle | 283system.cpu.iq.iqInstsAdded 20212 # Number of instructions added to the IQ (excludes non-spec) 284system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ 285system.cpu.iq.iqInstsIssued 17024 # Number of instructions issued 286system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued 287system.cpu.iq.iqSquashedInstsExamined 9720 # Number of squashed instructions iterated over during squash; mainly for profiling 288system.cpu.iq.iqSquashedOperandsExamined 13890 # Number of squashed operands that are examined and possibly removed from graph 289system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed 290system.cpu.iq.issued_per_cycle::samples 21925 # Number of insts issued each cycle 291system.cpu.iq.issued_per_cycle::mean 0.776465 # Number of insts issued each cycle 292system.cpu.iq.issued_per_cycle::stdev 1.650682 # Number of insts issued each cycle |
| 255system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 293system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 256system.cpu.iq.issued_per_cycle::0 13831 71.74% 71.74% # Number of insts issued each cycle 257system.cpu.iq.issued_per_cycle::1 1491 7.73% 79.48% # Number of insts issued each cycle 258system.cpu.iq.issued_per_cycle::2 1108 5.75% 85.22% # Number of insts issued each cycle 259system.cpu.iq.issued_per_cycle::3 718 3.72% 88.95% # Number of insts issued each cycle 260system.cpu.iq.issued_per_cycle::4 686 3.56% 92.50% # Number of insts issued each cycle 261system.cpu.iq.issued_per_cycle::5 589 3.06% 95.56% # Number of insts issued each cycle 262system.cpu.iq.issued_per_cycle::6 582 3.02% 98.58% # Number of insts issued each cycle 263system.cpu.iq.issued_per_cycle::7 230 1.19% 99.77% # Number of insts issued each cycle 264system.cpu.iq.issued_per_cycle::8 44 0.23% 100.00% # Number of insts issued each cycle | 294system.cpu.iq.issued_per_cycle::0 16429 74.93% 74.93% # Number of insts issued each cycle 295system.cpu.iq.issued_per_cycle::1 1551 7.07% 82.01% # Number of insts issued each cycle 296system.cpu.iq.issued_per_cycle::2 1089 4.97% 86.97% # Number of insts issued each cycle 297system.cpu.iq.issued_per_cycle::3 725 3.31% 90.28% # Number of insts issued each cycle 298system.cpu.iq.issued_per_cycle::4 705 3.22% 93.50% # Number of insts issued each cycle 299system.cpu.iq.issued_per_cycle::5 574 2.62% 96.11% # Number of insts issued each cycle 300system.cpu.iq.issued_per_cycle::6 578 2.64% 98.75% # Number of insts issued each cycle 301system.cpu.iq.issued_per_cycle::7 230 1.05% 99.80% # Number of insts issued each cycle 302system.cpu.iq.issued_per_cycle::8 44 0.20% 100.00% # Number of insts issued each cycle |
| 265system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 266system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 267system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 303system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 304system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 305system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 268system.cpu.iq.issued_per_cycle::total 19279 # Number of insts issued each cycle | 306system.cpu.iq.issued_per_cycle::total 21925 # Number of insts issued each cycle |
| 269system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 307system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 270system.cpu.iq.fu_full::IntAlu 127 76.51% 76.51% # attempts to use FU when none available 271system.cpu.iq.fu_full::IntMult 0 0.00% 76.51% # attempts to use FU when none available 272system.cpu.iq.fu_full::IntDiv 0 0.00% 76.51% # attempts to use FU when none available 273system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.51% # attempts to use FU when none available 274system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.51% # attempts to use FU when none available 275system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.51% # attempts to use FU when none available 276system.cpu.iq.fu_full::FloatMult 0 0.00% 76.51% # attempts to use FU when none available 277system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.51% # attempts to use FU when none available 278system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.51% # attempts to use FU when none available 279system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.51% # attempts to use FU when none available 280system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.51% # attempts to use FU when none available 281system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.51% # attempts to use FU when none available 282system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.51% # attempts to use FU when none available 283system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.51% # attempts to use FU when none available 284system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.51% # attempts to use FU when none available 285system.cpu.iq.fu_full::SimdMult 0 0.00% 76.51% # attempts to use FU when none available 286system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.51% # attempts to use FU when none available 287system.cpu.iq.fu_full::SimdShift 0 0.00% 76.51% # attempts to use FU when none available 288system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.51% # attempts to use FU when none available 289system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.51% # attempts to use FU when none available 290system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.51% # attempts to use FU when none available 291system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.51% # attempts to use FU when none available 292system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.51% # attempts to use FU when none available 293system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.51% # attempts to use FU when none available 294system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.51% # attempts to use FU when none available 295system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.51% # attempts to use FU when none available 296system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.51% # attempts to use FU when none available 297system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.51% # attempts to use FU when none available 298system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.51% # attempts to use FU when none available 299system.cpu.iq.fu_full::MemRead 24 14.46% 90.96% # attempts to use FU when none available 300system.cpu.iq.fu_full::MemWrite 15 9.04% 100.00% # attempts to use FU when none available | 308system.cpu.iq.fu_full::IntAlu 139 76.80% 76.80% # attempts to use FU when none available 309system.cpu.iq.fu_full::IntMult 0 0.00% 76.80% # attempts to use FU when none available 310system.cpu.iq.fu_full::IntDiv 0 0.00% 76.80% # attempts to use FU when none available 311system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.80% # attempts to use FU when none available 312system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.80% # attempts to use FU when none available 313system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.80% # attempts to use FU when none available 314system.cpu.iq.fu_full::FloatMult 0 0.00% 76.80% # attempts to use FU when none available 315system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.80% # attempts to use FU when none available 316system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.80% # attempts to use FU when none available 317system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.80% # attempts to use FU when none available 318system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.80% # attempts to use FU when none available 319system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.80% # attempts to use FU when none available 320system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.80% # attempts to use FU when none available 321system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.80% # attempts to use FU when none available 322system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.80% # attempts to use FU when none available 323system.cpu.iq.fu_full::SimdMult 0 0.00% 76.80% # attempts to use FU when none available 324system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.80% # attempts to use FU when none available 325system.cpu.iq.fu_full::SimdShift 0 0.00% 76.80% # attempts to use FU when none available 326system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.80% # attempts to use FU when none available 327system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.80% # attempts to use FU when none available 328system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.80% # attempts to use FU when none available 329system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.80% # attempts to use FU when none available 330system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.80% # attempts to use FU when none available 331system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.80% # attempts to use FU when none available 332system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.80% # attempts to use FU when none available 333system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.80% # attempts to use FU when none available 334system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.80% # attempts to use FU when none available 335system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.80% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.80% # attempts to use FU when none available 337system.cpu.iq.fu_full::MemRead 27 14.92% 91.71% # attempts to use FU when none available 338system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available |
| 301system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 302system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 303system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued | 339system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 340system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 341system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued |
| 304system.cpu.iq.FU_type_0::IntAlu 13619 80.09% 80.11% # Type of FU issued 305system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.13% # Type of FU issued 306system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.18% # Type of FU issued 307system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued 308system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued 309system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued 310system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued 311system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued 312system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued 313system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued 314system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued 315system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued 316system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued 317system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued 318system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued 319system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued 320system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued 321system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued 322system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued 323system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued 324system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued 325system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued 326system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued 327system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued 328system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued 329system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued 330system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued 331system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued 332system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued 333system.cpu.iq.FU_type_0::MemRead 1977 11.63% 91.80% # Type of FU issued 334system.cpu.iq.FU_type_0::MemWrite 1394 8.20% 100.00% # Type of FU issued | 342system.cpu.iq.FU_type_0::IntAlu 13662 80.25% 80.27% # Type of FU issued 343system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.29% # Type of FU issued 344system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.33% # Type of FU issued 345system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.33% # Type of FU issued 346system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.33% # Type of FU issued 347system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.33% # Type of FU issued 348system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.33% # Type of FU issued 349system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.33% # Type of FU issued 350system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.33% # Type of FU issued 351system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.33% # Type of FU issued 352system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.33% # Type of FU issued 353system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.33% # Type of FU issued 354system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.33% # Type of FU issued 355system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.33% # Type of FU issued 356system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.33% # Type of FU issued 357system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.33% # Type of FU issued 358system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.33% # Type of FU issued 359system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.33% # Type of FU issued 360system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.33% # Type of FU issued 361system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.33% # Type of FU issued 362system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.33% # Type of FU issued 363system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.33% # Type of FU issued 364system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.33% # Type of FU issued 365system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.33% # Type of FU issued 366system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.33% # Type of FU issued 367system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.33% # Type of FU issued 368system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.33% # Type of FU issued 369system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.33% # Type of FU issued 370system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.33% # Type of FU issued 371system.cpu.iq.FU_type_0::MemRead 1972 11.58% 91.92% # Type of FU issued 372system.cpu.iq.FU_type_0::MemWrite 1376 8.08% 100.00% # Type of FU issued |
| 335system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 336system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 373system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 374system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 337system.cpu.iq.FU_type_0::total 17004 # Type of FU issued 338system.cpu.iq.rate 0.530645 # Inst issue rate 339system.cpu.iq.fu_busy_cnt 166 # FU busy when requested 340system.cpu.iq.fu_busy_rate 0.009762 # FU busy rate (busy events/executed inst) 341system.cpu.iq.int_inst_queue_reads 53696 # Number of integer instruction queue reads 342system.cpu.iq.int_inst_queue_writes 29666 # Number of integer instruction queue writes 343system.cpu.iq.int_inst_queue_wakeup_accesses 15641 # Number of integer instruction queue wakeup accesses | 375system.cpu.iq.FU_type_0::total 17024 # Type of FU issued 376system.cpu.iq.rate 0.434518 # Inst issue rate 377system.cpu.iq.fu_busy_cnt 181 # FU busy when requested 378system.cpu.iq.fu_busy_rate 0.010632 # FU busy rate (busy events/executed inst) 379system.cpu.iq.int_inst_queue_reads 56436 # Number of integer instruction queue reads 380system.cpu.iq.int_inst_queue_writes 29967 # Number of integer instruction queue writes 381system.cpu.iq.int_inst_queue_wakeup_accesses 15651 # Number of integer instruction queue wakeup accesses |
| 344system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 345system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 346system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses | 382system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 383system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 384system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses |
| 347system.cpu.iq.int_alu_accesses 17163 # Number of integer alu accesses | 385system.cpu.iq.int_alu_accesses 17198 # Number of integer alu accesses |
| 348system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses | 386system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses |
| 349system.cpu.iew.lsq.thread0.forwLoads 167 # Number of loads that had data forwarded from stores | 387system.cpu.iew.lsq.thread0.forwLoads 173 # Number of loads that had data forwarded from stores |
| 350system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 388system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 351system.cpu.iew.lsq.thread0.squashedLoads 1224 # Number of loads squashed 352system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed | 389system.cpu.iew.lsq.thread0.squashedLoads 1228 # Number of loads squashed 390system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed |
| 353system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations | 391system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations |
| 354system.cpu.iew.lsq.thread0.squashedStores 681 # Number of stores squashed | 392system.cpu.iew.lsq.thread0.squashedStores 633 # Number of stores squashed |
| 355system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 356system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 393system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 394system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 357system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 358system.cpu.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked | 395system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 396system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked |
| 359system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 397system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 360system.cpu.iew.iewSquashCycles 1785 # Number of cycles IEW is squashing 361system.cpu.iew.iewBlockCycles 1955 # Number of cycles IEW is blocking 362system.cpu.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking 363system.cpu.iew.iewDispatchedInsts 20123 # Number of instructions dispatched to IQ 364system.cpu.iew.iewDispSquashedInsts 54 # Number of squashed instructions skipped by dispatch 365system.cpu.iew.iewDispLoadInsts 2277 # Number of dispatched load instructions 366system.cpu.iew.iewDispStoreInsts 1616 # Number of dispatched store instructions 367system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions 368system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall | 398system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing 399system.cpu.iew.iewBlockCycles 2975 # Number of cycles IEW is blocking 400system.cpu.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking 401system.cpu.iew.iewDispatchedInsts 20240 # Number of instructions dispatched to IQ 402system.cpu.iew.iewDispSquashedInsts 40 # Number of squashed instructions skipped by dispatch 403system.cpu.iew.iewDispLoadInsts 2281 # Number of dispatched load instructions 404system.cpu.iew.iewDispStoreInsts 1568 # Number of dispatched store instructions 405system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions 406system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall |
| 369system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 370system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations | 407system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 408system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations |
| 371system.cpu.iew.predictedTakenIncorrect 121 # Number of branches that were predicted taken incorrectly 372system.cpu.iew.predictedNotTakenIncorrect 553 # Number of branches that were predicted not taken incorrectly 373system.cpu.iew.branchMispredicts 674 # Number of branch mispredicts detected at execute 374system.cpu.iew.iewExecutedInsts 16111 # Number of executed instructions 375system.cpu.iew.iewExecLoadInsts 1853 # Number of load instructions executed 376system.cpu.iew.iewExecSquashedInsts 893 # Number of squashed instructions skipped in execute | 409system.cpu.iew.predictedTakenIncorrect 114 # Number of branches that were predicted taken incorrectly 410system.cpu.iew.predictedNotTakenIncorrect 569 # Number of branches that were predicted not taken incorrectly 411system.cpu.iew.branchMispredicts 683 # Number of branch mispredicts detected at execute 412system.cpu.iew.iewExecutedInsts 16133 # Number of executed instructions 413system.cpu.iew.iewExecLoadInsts 1855 # Number of load instructions executed 414system.cpu.iew.iewExecSquashedInsts 891 # Number of squashed instructions skipped in execute |
| 377system.cpu.iew.exec_swp 0 # number of swp insts executed 378system.cpu.iew.exec_nop 0 # number of nop insts executed | 415system.cpu.iew.exec_swp 0 # number of swp insts executed 416system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 379system.cpu.iew.exec_refs 3149 # number of memory reference insts executed 380system.cpu.iew.exec_branches 1620 # Number of branches executed 381system.cpu.iew.exec_stores 1296 # Number of stores executed 382system.cpu.iew.exec_rate 0.502777 # Inst execution rate 383system.cpu.iew.wb_sent 15852 # cumulative count of insts sent to commit 384system.cpu.iew.wb_count 15645 # cumulative count of insts written-back 385system.cpu.iew.wb_producers 10112 # num instructions producing a value 386system.cpu.iew.wb_consumers 15481 # num instructions consuming a value | 417system.cpu.iew.exec_refs 3133 # number of memory reference insts executed 418system.cpu.iew.exec_branches 1621 # Number of branches executed 419system.cpu.iew.exec_stores 1278 # Number of stores executed 420system.cpu.iew.exec_rate 0.411777 # Inst execution rate 421system.cpu.iew.wb_sent 15873 # cumulative count of insts sent to commit 422system.cpu.iew.wb_count 15655 # cumulative count of insts written-back 423system.cpu.iew.wb_producers 10119 # num instructions producing a value 424system.cpu.iew.wb_consumers 15566 # num instructions consuming a value |
| 387system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 425system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 388system.cpu.iew.wb_rate 0.488235 # insts written-back per cycle 389system.cpu.iew.wb_fanout 0.653188 # average fanout of values written-back | 426system.cpu.iew.wb_rate 0.399576 # insts written-back per cycle 427system.cpu.iew.wb_fanout 0.650071 # average fanout of values written-back |
| 390system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 428system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 391system.cpu.commit.commitSquashedInsts 10375 # The number of squashed insts skipped by commit | 429system.cpu.commit.commitSquashedInsts 10504 # The number of squashed insts skipped by commit |
| 392system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards | 430system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards |
| 393system.cpu.commit.branchMispredicts 582 # The number of times a branch was mispredicted 394system.cpu.commit.committed_per_cycle::samples 17494 # Number of insts commited each cycle 395system.cpu.commit.committed_per_cycle::mean 0.557162 # Number of insts commited each cycle 396system.cpu.commit.committed_per_cycle::stdev 1.425293 # Number of insts commited each cycle | 431system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted 432system.cpu.commit.committed_per_cycle::samples 20068 # Number of insts commited each cycle 433system.cpu.commit.committed_per_cycle::mean 0.485699 # Number of insts commited each cycle 434system.cpu.commit.committed_per_cycle::stdev 1.341238 # Number of insts commited each cycle |
| 397system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 435system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 398system.cpu.commit.committed_per_cycle::0 13941 79.69% 79.69% # Number of insts commited each cycle 399system.cpu.commit.committed_per_cycle::1 1339 7.65% 87.34% # Number of insts commited each cycle 400system.cpu.commit.committed_per_cycle::2 594 3.40% 90.74% # Number of insts commited each cycle 401system.cpu.commit.committed_per_cycle::3 714 4.08% 94.82% # Number of insts commited each cycle 402system.cpu.commit.committed_per_cycle::4 361 2.06% 96.88% # Number of insts commited each cycle 403system.cpu.commit.committed_per_cycle::5 136 0.78% 97.66% # Number of insts commited each cycle 404system.cpu.commit.committed_per_cycle::6 122 0.70% 98.36% # Number of insts commited each cycle 405system.cpu.commit.committed_per_cycle::7 74 0.42% 98.78% # Number of insts commited each cycle 406system.cpu.commit.committed_per_cycle::8 213 1.22% 100.00% # Number of insts commited each cycle | 436system.cpu.commit.committed_per_cycle::0 16495 82.20% 82.20% # Number of insts commited each cycle 437system.cpu.commit.committed_per_cycle::1 1364 6.80% 88.99% # Number of insts commited each cycle 438system.cpu.commit.committed_per_cycle::2 592 2.95% 91.94% # Number of insts commited each cycle 439system.cpu.commit.committed_per_cycle::3 713 3.55% 95.50% # Number of insts commited each cycle 440system.cpu.commit.committed_per_cycle::4 362 1.80% 97.30% # Number of insts commited each cycle 441system.cpu.commit.committed_per_cycle::5 137 0.68% 97.98% # Number of insts commited each cycle 442system.cpu.commit.committed_per_cycle::6 121 0.60% 98.58% # Number of insts commited each cycle 443system.cpu.commit.committed_per_cycle::7 71 0.35% 98.94% # Number of insts commited each cycle 444system.cpu.commit.committed_per_cycle::8 213 1.06% 100.00% # Number of insts commited each cycle |
| 407system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 408system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 445system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 446system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 447system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 410system.cpu.commit.committed_per_cycle::total 17494 # Number of insts commited each cycle | 448system.cpu.commit.committed_per_cycle::total 20068 # Number of insts commited each cycle |
| 411system.cpu.commit.committedInsts 5380 # Number of instructions committed 412system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed 413system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 414system.cpu.commit.refs 1988 # Number of memory references committed 415system.cpu.commit.loads 1053 # Number of loads committed 416system.cpu.commit.membars 0 # Number of memory barriers committed 417system.cpu.commit.branches 1208 # Number of branches committed 418system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 419system.cpu.commit.int_insts 9654 # Number of committed integer instructions. 420system.cpu.commit.function_calls 106 # Number of function calls committed. 421system.cpu.commit.bw_lim_events 213 # number cycles where commit BW limit reached 422system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 449system.cpu.commit.committedInsts 5380 # Number of instructions committed 450system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed 451system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 452system.cpu.commit.refs 1988 # Number of memory references committed 453system.cpu.commit.loads 1053 # Number of loads committed 454system.cpu.commit.membars 0 # Number of memory barriers committed 455system.cpu.commit.branches 1208 # Number of branches committed 456system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 457system.cpu.commit.int_insts 9654 # Number of committed integer instructions. 458system.cpu.commit.function_calls 106 # Number of function calls committed. 459system.cpu.commit.bw_lim_events 213 # number cycles where commit BW limit reached 460system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 423system.cpu.rob.rob_reads 37403 # The number of ROB reads 424system.cpu.rob.rob_writes 42056 # The number of ROB writes 425system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself 426system.cpu.idleCycles 12765 # Total number of cycles that the CPU has spent unscheduled due to idling | 461system.cpu.rob.rob_reads 40106 # The number of ROB reads 462system.cpu.rob.rob_writes 42382 # The number of ROB writes 463system.cpu.timesIdled 168 # Number of times that the entire CPU went into an idle state and unscheduled itself 464system.cpu.idleCycles 17254 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 427system.cpu.committedInsts 5380 # Number of Instructions Simulated 428system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated 429system.cpu.committedInsts_total 5380 # Number of Instructions Simulated | 465system.cpu.committedInsts 5380 # Number of Instructions Simulated 466system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated 467system.cpu.committedInsts_total 5380 # Number of Instructions Simulated |
| 430system.cpu.cpi 5.956134 # CPI: Cycles Per Instruction 431system.cpu.cpi_total 5.956134 # CPI: Total CPI of All Threads 432system.cpu.ipc 0.167894 # IPC: Instructions Per Cycle 433system.cpu.ipc_total 0.167894 # IPC: Total IPC of All Threads 434system.cpu.int_regfile_reads 28607 # number of integer regfile reads 435system.cpu.int_regfile_writes 17139 # number of integer regfile writes | 468system.cpu.cpi 7.282342 # CPI: Cycles Per Instruction 469system.cpu.cpi_total 7.282342 # CPI: Total CPI of All Threads 470system.cpu.ipc 0.137318 # IPC: Instructions Per Cycle 471system.cpu.ipc_total 0.137318 # IPC: Total IPC of All Threads 472system.cpu.int_regfile_reads 28721 # number of integer regfile reads 473system.cpu.int_regfile_writes 17199 # number of integer regfile writes |
| 436system.cpu.fp_regfile_reads 4 # number of floating regfile reads | 474system.cpu.fp_regfile_reads 4 # number of floating regfile reads |
| 437system.cpu.misc_regfile_reads 7155 # number of misc regfile reads | 475system.cpu.misc_regfile_reads 7135 # number of misc regfile reads |
| 438system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 476system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 477system.cpu.toL2Bus.throughput 1355862984 # Throughput (bytes/s) 478system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution 479system.cpu.toL2Bus.trans_dist::ReadResp 338 # Transaction distribution 480system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution 481system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution 482system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 548 # Packet count per connected master and slave (bytes) 483system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 283 # Packet count per connected master and slave (bytes) 484system.cpu.toL2Bus.pkt_count 831 # Packet count per connected master and slave (bytes) 485system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17536 # Cumulative packet size per connected master and slave (bytes) 486system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes) 487system.cpu.toL2Bus.tot_pkt_size 26560 # Cumulative packet size per connected master and slave (bytes) 488system.cpu.toL2Bus.data_through_bus 26560 # Total data (bytes) 489system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 490system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks) 491system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 492system.cpu.toL2Bus.respLayer0.occupancy 411000 # Layer occupancy (ticks) 493system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) 494system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) 495system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) |
|
| 439system.cpu.icache.replacements 0 # number of replacements | 496system.cpu.icache.replacements 0 # number of replacements |
| 440system.cpu.icache.tagsinuse 134.419040 # Cycle average of tags in use 441system.cpu.icache.total_refs 1594 # Total number of references to valid blocks. 442system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. 443system.cpu.icache.avg_refs 5.713262 # Average number of references to valid blocks. | 497system.cpu.icache.tagsinuse 130.964375 # Cycle average of tags in use 498system.cpu.icache.total_refs 1611 # Total number of references to valid blocks. 499system.cpu.icache.sampled_refs 274 # Sample count of references to valid blocks. 500system.cpu.icache.avg_refs 5.879562 # Average number of references to valid blocks. |
| 444system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 501system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 445system.cpu.icache.occ_blocks::cpu.inst 134.419040 # Average occupied blocks per requestor 446system.cpu.icache.occ_percent::cpu.inst 0.065634 # Average percentage of cache occupancy 447system.cpu.icache.occ_percent::total 0.065634 # Average percentage of cache occupancy 448system.cpu.icache.ReadReq_hits::cpu.inst 1594 # number of ReadReq hits 449system.cpu.icache.ReadReq_hits::total 1594 # number of ReadReq hits 450system.cpu.icache.demand_hits::cpu.inst 1594 # number of demand (read+write) hits 451system.cpu.icache.demand_hits::total 1594 # number of demand (read+write) hits 452system.cpu.icache.overall_hits::cpu.inst 1594 # number of overall hits 453system.cpu.icache.overall_hits::total 1594 # number of overall hits 454system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses 455system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses 456system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses 457system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses 458system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses 459system.cpu.icache.overall_misses::total 371 # number of overall misses 460system.cpu.icache.ReadReq_miss_latency::cpu.inst 19224000 # number of ReadReq miss cycles 461system.cpu.icache.ReadReq_miss_latency::total 19224000 # number of ReadReq miss cycles 462system.cpu.icache.demand_miss_latency::cpu.inst 19224000 # number of demand (read+write) miss cycles 463system.cpu.icache.demand_miss_latency::total 19224000 # number of demand (read+write) miss cycles 464system.cpu.icache.overall_miss_latency::cpu.inst 19224000 # number of overall miss cycles 465system.cpu.icache.overall_miss_latency::total 19224000 # number of overall miss cycles 466system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) 467system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) 468system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses 469system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses 470system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses 471system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses 472system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.188804 # miss rate for ReadReq accesses 473system.cpu.icache.ReadReq_miss_rate::total 0.188804 # miss rate for ReadReq accesses 474system.cpu.icache.demand_miss_rate::cpu.inst 0.188804 # miss rate for demand accesses 475system.cpu.icache.demand_miss_rate::total 0.188804 # miss rate for demand accesses 476system.cpu.icache.overall_miss_rate::cpu.inst 0.188804 # miss rate for overall accesses 477system.cpu.icache.overall_miss_rate::total 0.188804 # miss rate for overall accesses 478system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51816.711590 # average ReadReq miss latency 479system.cpu.icache.ReadReq_avg_miss_latency::total 51816.711590 # average ReadReq miss latency 480system.cpu.icache.demand_avg_miss_latency::cpu.inst 51816.711590 # average overall miss latency 481system.cpu.icache.demand_avg_miss_latency::total 51816.711590 # average overall miss latency 482system.cpu.icache.overall_avg_miss_latency::cpu.inst 51816.711590 # average overall miss latency 483system.cpu.icache.overall_avg_miss_latency::total 51816.711590 # average overall miss latency 484system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 502system.cpu.icache.occ_blocks::cpu.inst 130.964375 # Average occupied blocks per requestor 503system.cpu.icache.occ_percent::cpu.inst 0.063947 # Average percentage of cache occupancy 504system.cpu.icache.occ_percent::total 0.063947 # Average percentage of cache occupancy 505system.cpu.icache.ReadReq_hits::cpu.inst 1611 # number of ReadReq hits 506system.cpu.icache.ReadReq_hits::total 1611 # number of ReadReq hits 507system.cpu.icache.demand_hits::cpu.inst 1611 # number of demand (read+write) hits 508system.cpu.icache.demand_hits::total 1611 # number of demand (read+write) hits 509system.cpu.icache.overall_hits::cpu.inst 1611 # number of overall hits 510system.cpu.icache.overall_hits::total 1611 # number of overall hits 511system.cpu.icache.ReadReq_misses::cpu.inst 370 # number of ReadReq misses 512system.cpu.icache.ReadReq_misses::total 370 # number of ReadReq misses 513system.cpu.icache.demand_misses::cpu.inst 370 # number of demand (read+write) misses 514system.cpu.icache.demand_misses::total 370 # number of demand (read+write) misses 515system.cpu.icache.overall_misses::cpu.inst 370 # number of overall misses 516system.cpu.icache.overall_misses::total 370 # number of overall misses 517system.cpu.icache.ReadReq_miss_latency::cpu.inst 24285500 # number of ReadReq miss cycles 518system.cpu.icache.ReadReq_miss_latency::total 24285500 # number of ReadReq miss cycles 519system.cpu.icache.demand_miss_latency::cpu.inst 24285500 # number of demand (read+write) miss cycles 520system.cpu.icache.demand_miss_latency::total 24285500 # number of demand (read+write) miss cycles 521system.cpu.icache.overall_miss_latency::cpu.inst 24285500 # number of overall miss cycles 522system.cpu.icache.overall_miss_latency::total 24285500 # number of overall miss cycles 523system.cpu.icache.ReadReq_accesses::cpu.inst 1981 # number of ReadReq accesses(hits+misses) 524system.cpu.icache.ReadReq_accesses::total 1981 # number of ReadReq accesses(hits+misses) 525system.cpu.icache.demand_accesses::cpu.inst 1981 # number of demand (read+write) accesses 526system.cpu.icache.demand_accesses::total 1981 # number of demand (read+write) accesses 527system.cpu.icache.overall_accesses::cpu.inst 1981 # number of overall (read+write) accesses 528system.cpu.icache.overall_accesses::total 1981 # number of overall (read+write) accesses 529system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186774 # miss rate for ReadReq accesses 530system.cpu.icache.ReadReq_miss_rate::total 0.186774 # miss rate for ReadReq accesses 531system.cpu.icache.demand_miss_rate::cpu.inst 0.186774 # miss rate for demand accesses 532system.cpu.icache.demand_miss_rate::total 0.186774 # miss rate for demand accesses 533system.cpu.icache.overall_miss_rate::cpu.inst 0.186774 # miss rate for overall accesses 534system.cpu.icache.overall_miss_rate::total 0.186774 # miss rate for overall accesses 535system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65636.486486 # average ReadReq miss latency 536system.cpu.icache.ReadReq_avg_miss_latency::total 65636.486486 # average ReadReq miss latency 537system.cpu.icache.demand_avg_miss_latency::cpu.inst 65636.486486 # average overall miss latency 538system.cpu.icache.demand_avg_miss_latency::total 65636.486486 # average overall miss latency 539system.cpu.icache.overall_avg_miss_latency::cpu.inst 65636.486486 # average overall miss latency 540system.cpu.icache.overall_avg_miss_latency::total 65636.486486 # average overall miss latency 541system.cpu.icache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked |
| 485system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 542system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 486system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked | 543system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked |
| 487system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 544system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 488system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 545system.cpu.icache.avg_blocked_cycles::no_mshrs 46 # average number of cycles each access was blocked |
| 489system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 490system.cpu.icache.fast_writes 0 # number of fast writes performed 491system.cpu.icache.cache_copies 0 # number of cache copies performed | 546system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 547system.cpu.icache.fast_writes 0 # number of fast writes performed 548system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 492system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits 493system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits 494system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits 495system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits 496system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits 497system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits 498system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses 499system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses 500system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses 501system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses 502system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses 503system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses 504system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15030000 # number of ReadReq MSHR miss cycles 505system.cpu.icache.ReadReq_mshr_miss_latency::total 15030000 # number of ReadReq MSHR miss cycles 506system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15030000 # number of demand (read+write) MSHR miss cycles 507system.cpu.icache.demand_mshr_miss_latency::total 15030000 # number of demand (read+write) MSHR miss cycles 508system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15030000 # number of overall MSHR miss cycles 509system.cpu.icache.overall_mshr_miss_latency::total 15030000 # number of overall MSHR miss cycles 510system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142494 # mshr miss rate for ReadReq accesses 511system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142494 # mshr miss rate for ReadReq accesses 512system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142494 # mshr miss rate for demand accesses 513system.cpu.icache.demand_mshr_miss_rate::total 0.142494 # mshr miss rate for demand accesses 514system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142494 # mshr miss rate for overall accesses 515system.cpu.icache.overall_mshr_miss_rate::total 0.142494 # mshr miss rate for overall accesses 516system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53678.571429 # average ReadReq mshr miss latency 517system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53678.571429 # average ReadReq mshr miss latency 518system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53678.571429 # average overall mshr miss latency 519system.cpu.icache.demand_avg_mshr_miss_latency::total 53678.571429 # average overall mshr miss latency 520system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53678.571429 # average overall mshr miss latency 521system.cpu.icache.overall_avg_mshr_miss_latency::total 53678.571429 # average overall mshr miss latency | 549system.cpu.icache.ReadReq_mshr_hits::cpu.inst 96 # number of ReadReq MSHR hits 550system.cpu.icache.ReadReq_mshr_hits::total 96 # number of ReadReq MSHR hits 551system.cpu.icache.demand_mshr_hits::cpu.inst 96 # number of demand (read+write) MSHR hits 552system.cpu.icache.demand_mshr_hits::total 96 # number of demand (read+write) MSHR hits 553system.cpu.icache.overall_mshr_hits::cpu.inst 96 # number of overall MSHR hits 554system.cpu.icache.overall_mshr_hits::total 96 # number of overall MSHR hits 555system.cpu.icache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses 556system.cpu.icache.ReadReq_mshr_misses::total 274 # number of ReadReq MSHR misses 557system.cpu.icache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses 558system.cpu.icache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses 559system.cpu.icache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses 560system.cpu.icache.overall_mshr_misses::total 274 # number of overall MSHR misses 561system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18984000 # number of ReadReq MSHR miss cycles 562system.cpu.icache.ReadReq_mshr_miss_latency::total 18984000 # number of ReadReq MSHR miss cycles 563system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18984000 # number of demand (read+write) MSHR miss cycles 564system.cpu.icache.demand_mshr_miss_latency::total 18984000 # number of demand (read+write) MSHR miss cycles 565system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18984000 # number of overall MSHR miss cycles 566system.cpu.icache.overall_mshr_miss_latency::total 18984000 # number of overall MSHR miss cycles 567system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for ReadReq accesses 568system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138314 # mshr miss rate for ReadReq accesses 569system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for demand accesses 570system.cpu.icache.demand_mshr_miss_rate::total 0.138314 # mshr miss rate for demand accesses 571system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for overall accesses 572system.cpu.icache.overall_mshr_miss_rate::total 0.138314 # mshr miss rate for overall accesses 573system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69284.671533 # average ReadReq mshr miss latency 574system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69284.671533 # average ReadReq mshr miss latency 575system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69284.671533 # average overall mshr miss latency 576system.cpu.icache.demand_avg_mshr_miss_latency::total 69284.671533 # average overall mshr miss latency 577system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69284.671533 # average overall mshr miss latency 578system.cpu.icache.overall_avg_mshr_miss_latency::total 69284.671533 # average overall mshr miss latency |
| 522system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 523system.cpu.l2cache.replacements 0 # number of replacements | 579system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 580system.cpu.l2cache.replacements 0 # number of replacements |
| 524system.cpu.l2cache.tagsinuse 167.756635 # Cycle average of tags in use | 581system.cpu.l2cache.tagsinuse 162.651714 # Cycle average of tags in use |
| 525system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. | 582system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. |
| 526system.cpu.l2cache.sampled_refs 344 # Sample count of references to valid blocks. 527system.cpu.l2cache.avg_refs 0.005814 # Average number of references to valid blocks. | 583system.cpu.l2cache.sampled_refs 336 # Sample count of references to valid blocks. 584system.cpu.l2cache.avg_refs 0.005952 # Average number of references to valid blocks. |
| 528system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 585system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 529system.cpu.l2cache.occ_blocks::cpu.inst 134.530220 # Average occupied blocks per requestor 530system.cpu.l2cache.occ_blocks::cpu.data 33.226414 # Average occupied blocks per requestor 531system.cpu.l2cache.occ_percent::cpu.inst 0.004106 # Average percentage of cache occupancy 532system.cpu.l2cache.occ_percent::cpu.data 0.001014 # Average percentage of cache occupancy 533system.cpu.l2cache.occ_percent::total 0.005120 # Average percentage of cache occupancy | 586system.cpu.l2cache.occ_blocks::cpu.inst 131.033866 # Average occupied blocks per requestor 587system.cpu.l2cache.occ_blocks::cpu.data 31.617848 # Average occupied blocks per requestor 588system.cpu.l2cache.occ_percent::cpu.inst 0.003999 # Average percentage of cache occupancy 589system.cpu.l2cache.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy 590system.cpu.l2cache.occ_percent::total 0.004964 # Average percentage of cache occupancy |
| 534system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 535system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 536system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 537system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 538system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 539system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 540system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 541system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 542system.cpu.l2cache.overall_hits::total 2 # number of overall hits | 591system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 592system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 593system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 594system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 595system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 596system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 597system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 598system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 599system.cpu.l2cache.overall_hits::total 2 # number of overall hits |
| 543system.cpu.l2cache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 544system.cpu.l2cache.ReadReq_misses::cpu.data 66 # number of ReadReq misses 545system.cpu.l2cache.ReadReq_misses::total 345 # number of ReadReq misses | 600system.cpu.l2cache.ReadReq_misses::cpu.inst 273 # number of ReadReq misses 601system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses 602system.cpu.l2cache.ReadReq_misses::total 337 # number of ReadReq misses |
| 546system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses 547system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses | 603system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses 604system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses |
| 548system.cpu.l2cache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 549system.cpu.l2cache.demand_misses::cpu.data 143 # number of demand (read+write) misses 550system.cpu.l2cache.demand_misses::total 422 # number of demand (read+write) misses 551system.cpu.l2cache.overall_misses::cpu.inst 279 # number of overall misses 552system.cpu.l2cache.overall_misses::cpu.data 143 # number of overall misses 553system.cpu.l2cache.overall_misses::total 422 # number of overall misses 554system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14740500 # number of ReadReq miss cycles 555system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3980000 # number of ReadReq miss cycles 556system.cpu.l2cache.ReadReq_miss_latency::total 18720500 # number of ReadReq miss cycles 557system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4206500 # number of ReadExReq miss cycles 558system.cpu.l2cache.ReadExReq_miss_latency::total 4206500 # number of ReadExReq miss cycles 559system.cpu.l2cache.demand_miss_latency::cpu.inst 14740500 # number of demand (read+write) miss cycles 560system.cpu.l2cache.demand_miss_latency::cpu.data 8186500 # number of demand (read+write) miss cycles 561system.cpu.l2cache.demand_miss_latency::total 22927000 # number of demand (read+write) miss cycles 562system.cpu.l2cache.overall_miss_latency::cpu.inst 14740500 # number of overall miss cycles 563system.cpu.l2cache.overall_miss_latency::cpu.data 8186500 # number of overall miss cycles 564system.cpu.l2cache.overall_miss_latency::total 22927000 # number of overall miss cycles 565system.cpu.l2cache.ReadReq_accesses::cpu.inst 280 # number of ReadReq accesses(hits+misses) 566system.cpu.l2cache.ReadReq_accesses::cpu.data 67 # number of ReadReq accesses(hits+misses) 567system.cpu.l2cache.ReadReq_accesses::total 347 # number of ReadReq accesses(hits+misses) | 605system.cpu.l2cache.demand_misses::cpu.inst 273 # number of demand (read+write) misses 606system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses 607system.cpu.l2cache.demand_misses::total 414 # number of demand (read+write) misses 608system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses 609system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses 610system.cpu.l2cache.overall_misses::total 414 # number of overall misses 611system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18699000 # number of ReadReq miss cycles 612system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4915000 # number of ReadReq miss cycles 613system.cpu.l2cache.ReadReq_miss_latency::total 23614000 # number of ReadReq miss cycles 614system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5418500 # number of ReadExReq miss cycles 615system.cpu.l2cache.ReadExReq_miss_latency::total 5418500 # number of ReadExReq miss cycles 616system.cpu.l2cache.demand_miss_latency::cpu.inst 18699000 # number of demand (read+write) miss cycles 617system.cpu.l2cache.demand_miss_latency::cpu.data 10333500 # number of demand (read+write) miss cycles 618system.cpu.l2cache.demand_miss_latency::total 29032500 # number of demand (read+write) miss cycles 619system.cpu.l2cache.overall_miss_latency::cpu.inst 18699000 # number of overall miss cycles 620system.cpu.l2cache.overall_miss_latency::cpu.data 10333500 # number of overall miss cycles 621system.cpu.l2cache.overall_miss_latency::total 29032500 # number of overall miss cycles 622system.cpu.l2cache.ReadReq_accesses::cpu.inst 274 # number of ReadReq accesses(hits+misses) 623system.cpu.l2cache.ReadReq_accesses::cpu.data 65 # number of ReadReq accesses(hits+misses) 624system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) |
| 568system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses) 569system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses) | 625system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses) 626system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses) |
| 570system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses 571system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses 572system.cpu.l2cache.demand_accesses::total 424 # number of demand (read+write) accesses 573system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses 574system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses 575system.cpu.l2cache.overall_accesses::total 424 # number of overall (read+write) accesses 576system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996429 # miss rate for ReadReq accesses 577system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.985075 # miss rate for ReadReq accesses 578system.cpu.l2cache.ReadReq_miss_rate::total 0.994236 # miss rate for ReadReq accesses | 627system.cpu.l2cache.demand_accesses::cpu.inst 274 # number of demand (read+write) accesses 628system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 629system.cpu.l2cache.demand_accesses::total 416 # number of demand (read+write) accesses 630system.cpu.l2cache.overall_accesses::cpu.inst 274 # number of overall (read+write) accesses 631system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses 632system.cpu.l2cache.overall_accesses::total 416 # number of overall (read+write) accesses 633system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996350 # miss rate for ReadReq accesses 634system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.984615 # miss rate for ReadReq accesses 635system.cpu.l2cache.ReadReq_miss_rate::total 0.994100 # miss rate for ReadReq accesses |
| 579system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 580system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 636system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 637system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 581system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996429 # miss rate for demand accesses 582system.cpu.l2cache.demand_miss_rate::cpu.data 0.993056 # miss rate for demand accesses 583system.cpu.l2cache.demand_miss_rate::total 0.995283 # miss rate for demand accesses 584system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996429 # miss rate for overall accesses 585system.cpu.l2cache.overall_miss_rate::cpu.data 0.993056 # miss rate for overall accesses 586system.cpu.l2cache.overall_miss_rate::total 0.995283 # miss rate for overall accesses 587system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52833.333333 # average ReadReq miss latency 588system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60303.030303 # average ReadReq miss latency 589system.cpu.l2cache.ReadReq_avg_miss_latency::total 54262.318841 # average ReadReq miss latency 590system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54629.870130 # average ReadExReq miss latency 591system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54629.870130 # average ReadExReq miss latency 592system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52833.333333 # average overall miss latency 593system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57248.251748 # average overall miss latency 594system.cpu.l2cache.demand_avg_miss_latency::total 54329.383886 # average overall miss latency 595system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52833.333333 # average overall miss latency 596system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57248.251748 # average overall miss latency 597system.cpu.l2cache.overall_avg_miss_latency::total 54329.383886 # average overall miss latency | 638system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996350 # miss rate for demand accesses 639system.cpu.l2cache.demand_miss_rate::cpu.data 0.992958 # miss rate for demand accesses 640system.cpu.l2cache.demand_miss_rate::total 0.995192 # miss rate for demand accesses 641system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996350 # miss rate for overall accesses 642system.cpu.l2cache.overall_miss_rate::cpu.data 0.992958 # miss rate for overall accesses 643system.cpu.l2cache.overall_miss_rate::total 0.995192 # miss rate for overall accesses 644system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68494.505495 # average ReadReq miss latency 645system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76796.875000 # average ReadReq miss latency 646system.cpu.l2cache.ReadReq_avg_miss_latency::total 70071.216617 # average ReadReq miss latency 647system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70370.129870 # average ReadExReq miss latency 648system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70370.129870 # average ReadExReq miss latency 649system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68494.505495 # average overall miss latency 650system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73287.234043 # average overall miss latency 651system.cpu.l2cache.demand_avg_miss_latency::total 70126.811594 # average overall miss latency 652system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68494.505495 # average overall miss latency 653system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73287.234043 # average overall miss latency 654system.cpu.l2cache.overall_avg_miss_latency::total 70126.811594 # average overall miss latency |
| 598system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 599system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 600system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 601system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 602system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 603system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 604system.cpu.l2cache.fast_writes 0 # number of fast writes performed 605system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 655system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 656system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 657system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 658system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 659system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 660system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 661system.cpu.l2cache.fast_writes 0 # number of fast writes performed 662system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 606system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 607system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses 608system.cpu.l2cache.ReadReq_mshr_misses::total 345 # number of ReadReq MSHR misses | 663system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses 664system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 665system.cpu.l2cache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses |
| 609system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses 610system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses | 666system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses 667system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses |
| 611system.cpu.l2cache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 612system.cpu.l2cache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses 613system.cpu.l2cache.demand_mshr_misses::total 422 # number of demand (read+write) MSHR misses 614system.cpu.l2cache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 615system.cpu.l2cache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses 616system.cpu.l2cache.overall_mshr_misses::total 422 # number of overall MSHR misses 617system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11293716 # number of ReadReq MSHR miss cycles 618system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3166039 # number of ReadReq MSHR miss cycles 619system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14459755 # number of ReadReq MSHR miss cycles 620system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3259559 # number of ReadExReq MSHR miss cycles 621system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3259559 # number of ReadExReq MSHR miss cycles 622system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11293716 # number of demand (read+write) MSHR miss cycles 623system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6425598 # number of demand (read+write) MSHR miss cycles 624system.cpu.l2cache.demand_mshr_miss_latency::total 17719314 # number of demand (read+write) MSHR miss cycles 625system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11293716 # number of overall MSHR miss cycles 626system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6425598 # number of overall MSHR miss cycles 627system.cpu.l2cache.overall_mshr_miss_latency::total 17719314 # number of overall MSHR miss cycles 628system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996429 # mshr miss rate for ReadReq accesses 629system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.985075 # mshr miss rate for ReadReq accesses 630system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994236 # mshr miss rate for ReadReq accesses | 668system.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses 669system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 670system.cpu.l2cache.demand_mshr_misses::total 414 # number of demand (read+write) MSHR misses 671system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses 672system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 673system.cpu.l2cache.overall_mshr_misses::total 414 # number of overall MSHR misses 674system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15318750 # number of ReadReq MSHR miss cycles 675system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4136000 # number of ReadReq MSHR miss cycles 676system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19454750 # number of ReadReq MSHR miss cycles 677system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4474750 # number of ReadExReq MSHR miss cycles 678system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4474750 # number of ReadExReq MSHR miss cycles 679system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15318750 # number of demand (read+write) MSHR miss cycles 680system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8610750 # number of demand (read+write) MSHR miss cycles 681system.cpu.l2cache.demand_mshr_miss_latency::total 23929500 # number of demand (read+write) MSHR miss cycles 682system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15318750 # number of overall MSHR miss cycles 683system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8610750 # number of overall MSHR miss cycles 684system.cpu.l2cache.overall_mshr_miss_latency::total 23929500 # number of overall MSHR miss cycles 685system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for ReadReq accesses 686system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.984615 # mshr miss rate for ReadReq accesses 687system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994100 # mshr miss rate for ReadReq accesses |
| 631system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 632system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 688system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 689system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 633system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996429 # mshr miss rate for demand accesses 634system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for demand accesses 635system.cpu.l2cache.demand_mshr_miss_rate::total 0.995283 # mshr miss rate for demand accesses 636system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996429 # mshr miss rate for overall accesses 637system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for overall accesses 638system.cpu.l2cache.overall_mshr_miss_rate::total 0.995283 # mshr miss rate for overall accesses 639system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40479.268817 # average ReadReq mshr miss latency 640system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47970.287879 # average ReadReq mshr miss latency 641system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41912.333333 # average ReadReq mshr miss latency 642system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42331.935065 # average ReadExReq mshr miss latency 643system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42331.935065 # average ReadExReq mshr miss latency 644system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40479.268817 # average overall mshr miss latency 645system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44934.251748 # average overall mshr miss latency 646system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41988.895735 # average overall mshr miss latency 647system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40479.268817 # average overall mshr miss latency 648system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44934.251748 # average overall mshr miss latency 649system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41988.895735 # average overall mshr miss latency | 690system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for demand accesses 691system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992958 # mshr miss rate for demand accesses 692system.cpu.l2cache.demand_mshr_miss_rate::total 0.995192 # mshr miss rate for demand accesses 693system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses 694system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992958 # mshr miss rate for overall accesses 695system.cpu.l2cache.overall_mshr_miss_rate::total 0.995192 # mshr miss rate for overall accesses 696system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56112.637363 # average ReadReq mshr miss latency 697system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64625 # average ReadReq mshr miss latency 698system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57729.228487 # average ReadReq mshr miss latency 699system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58113.636364 # average ReadExReq mshr miss latency 700system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58113.636364 # average ReadExReq mshr miss latency 701system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56112.637363 # average overall mshr miss latency 702system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61069.148936 # average overall mshr miss latency 703system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57800.724638 # average overall mshr miss latency 704system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56112.637363 # average overall mshr miss latency 705system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61069.148936 # average overall mshr miss latency 706system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57800.724638 # average overall mshr miss latency |
| 650system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 651system.cpu.dcache.replacements 0 # number of replacements | 707system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 708system.cpu.dcache.replacements 0 # number of replacements |
| 652system.cpu.dcache.tagsinuse 84.412169 # Cycle average of tags in use 653system.cpu.dcache.total_refs 2338 # Total number of references to valid blocks. 654system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks. 655system.cpu.dcache.avg_refs 16.236111 # Average number of references to valid blocks. | 709system.cpu.dcache.tagsinuse 81.657362 # Cycle average of tags in use 710system.cpu.dcache.total_refs 2334 # Total number of references to valid blocks. 711system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. 712system.cpu.dcache.avg_refs 16.553191 # Average number of references to valid blocks. |
| 656system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 713system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 657system.cpu.dcache.occ_blocks::cpu.data 84.412169 # Average occupied blocks per requestor 658system.cpu.dcache.occ_percent::cpu.data 0.020608 # Average percentage of cache occupancy 659system.cpu.dcache.occ_percent::total 0.020608 # Average percentage of cache occupancy 660system.cpu.dcache.ReadReq_hits::cpu.data 1480 # number of ReadReq hits 661system.cpu.dcache.ReadReq_hits::total 1480 # number of ReadReq hits | 714system.cpu.dcache.occ_blocks::cpu.data 81.657362 # Average occupied blocks per requestor 715system.cpu.dcache.occ_percent::cpu.data 0.019936 # Average percentage of cache occupancy 716system.cpu.dcache.occ_percent::total 0.019936 # Average percentage of cache occupancy 717system.cpu.dcache.ReadReq_hits::cpu.data 1476 # number of ReadReq hits 718system.cpu.dcache.ReadReq_hits::total 1476 # number of ReadReq hits |
| 662system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits 663system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits | 719system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits 720system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits |
| 664system.cpu.dcache.demand_hits::cpu.data 2338 # number of demand (read+write) hits 665system.cpu.dcache.demand_hits::total 2338 # number of demand (read+write) hits 666system.cpu.dcache.overall_hits::cpu.data 2338 # number of overall hits 667system.cpu.dcache.overall_hits::total 2338 # number of overall hits 668system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses 669system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses | 721system.cpu.dcache.demand_hits::cpu.data 2334 # number of demand (read+write) hits 722system.cpu.dcache.demand_hits::total 2334 # number of demand (read+write) hits 723system.cpu.dcache.overall_hits::cpu.data 2334 # number of overall hits 724system.cpu.dcache.overall_hits::total 2334 # number of overall hits 725system.cpu.dcache.ReadReq_misses::cpu.data 131 # number of ReadReq misses 726system.cpu.dcache.ReadReq_misses::total 131 # number of ReadReq misses |
| 670system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses 671system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses | 727system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses 728system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses |
| 672system.cpu.dcache.demand_misses::cpu.data 213 # number of demand (read+write) misses 673system.cpu.dcache.demand_misses::total 213 # number of demand (read+write) misses 674system.cpu.dcache.overall_misses::cpu.data 213 # number of overall misses 675system.cpu.dcache.overall_misses::total 213 # number of overall misses 676system.cpu.dcache.ReadReq_miss_latency::cpu.data 8307000 # number of ReadReq miss cycles 677system.cpu.dcache.ReadReq_miss_latency::total 8307000 # number of ReadReq miss cycles 678system.cpu.dcache.WriteReq_miss_latency::cpu.data 4438000 # number of WriteReq miss cycles 679system.cpu.dcache.WriteReq_miss_latency::total 4438000 # number of WriteReq miss cycles 680system.cpu.dcache.demand_miss_latency::cpu.data 12745000 # number of demand (read+write) miss cycles 681system.cpu.dcache.demand_miss_latency::total 12745000 # number of demand (read+write) miss cycles 682system.cpu.dcache.overall_miss_latency::cpu.data 12745000 # number of overall miss cycles 683system.cpu.dcache.overall_miss_latency::total 12745000 # number of overall miss cycles 684system.cpu.dcache.ReadReq_accesses::cpu.data 1616 # number of ReadReq accesses(hits+misses) 685system.cpu.dcache.ReadReq_accesses::total 1616 # number of ReadReq accesses(hits+misses) | 729system.cpu.dcache.demand_misses::cpu.data 208 # number of demand (read+write) misses 730system.cpu.dcache.demand_misses::total 208 # number of demand (read+write) misses 731system.cpu.dcache.overall_misses::cpu.data 208 # number of overall misses 732system.cpu.dcache.overall_misses::total 208 # number of overall misses 733system.cpu.dcache.ReadReq_miss_latency::cpu.data 9350500 # number of ReadReq miss cycles 734system.cpu.dcache.ReadReq_miss_latency::total 9350500 # number of ReadReq miss cycles 735system.cpu.dcache.WriteReq_miss_latency::cpu.data 5649500 # number of WriteReq miss cycles 736system.cpu.dcache.WriteReq_miss_latency::total 5649500 # number of WriteReq miss cycles 737system.cpu.dcache.demand_miss_latency::cpu.data 15000000 # number of demand (read+write) miss cycles 738system.cpu.dcache.demand_miss_latency::total 15000000 # number of demand (read+write) miss cycles 739system.cpu.dcache.overall_miss_latency::cpu.data 15000000 # number of overall miss cycles 740system.cpu.dcache.overall_miss_latency::total 15000000 # number of overall miss cycles 741system.cpu.dcache.ReadReq_accesses::cpu.data 1607 # number of ReadReq accesses(hits+misses) 742system.cpu.dcache.ReadReq_accesses::total 1607 # number of ReadReq accesses(hits+misses) |
| 686system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 687system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) | 743system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 744system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) |
| 688system.cpu.dcache.demand_accesses::cpu.data 2551 # number of demand (read+write) accesses 689system.cpu.dcache.demand_accesses::total 2551 # number of demand (read+write) accesses 690system.cpu.dcache.overall_accesses::cpu.data 2551 # number of overall (read+write) accesses 691system.cpu.dcache.overall_accesses::total 2551 # number of overall (read+write) accesses 692system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084158 # miss rate for ReadReq accesses 693system.cpu.dcache.ReadReq_miss_rate::total 0.084158 # miss rate for ReadReq accesses | 745system.cpu.dcache.demand_accesses::cpu.data 2542 # number of demand (read+write) accesses 746system.cpu.dcache.demand_accesses::total 2542 # number of demand (read+write) accesses 747system.cpu.dcache.overall_accesses::cpu.data 2542 # number of overall (read+write) accesses 748system.cpu.dcache.overall_accesses::total 2542 # number of overall (read+write) accesses 749system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081518 # miss rate for ReadReq accesses 750system.cpu.dcache.ReadReq_miss_rate::total 0.081518 # miss rate for ReadReq accesses |
| 694system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses 695system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses | 751system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses 752system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses |
| 696system.cpu.dcache.demand_miss_rate::cpu.data 0.083497 # miss rate for demand accesses 697system.cpu.dcache.demand_miss_rate::total 0.083497 # miss rate for demand accesses 698system.cpu.dcache.overall_miss_rate::cpu.data 0.083497 # miss rate for overall accesses 699system.cpu.dcache.overall_miss_rate::total 0.083497 # miss rate for overall accesses 700system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61080.882353 # average ReadReq miss latency 701system.cpu.dcache.ReadReq_avg_miss_latency::total 61080.882353 # average ReadReq miss latency 702system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57636.363636 # average WriteReq miss latency 703system.cpu.dcache.WriteReq_avg_miss_latency::total 57636.363636 # average WriteReq miss latency 704system.cpu.dcache.demand_avg_miss_latency::cpu.data 59835.680751 # average overall miss latency 705system.cpu.dcache.demand_avg_miss_latency::total 59835.680751 # average overall miss latency 706system.cpu.dcache.overall_avg_miss_latency::cpu.data 59835.680751 # average overall miss latency 707system.cpu.dcache.overall_avg_miss_latency::total 59835.680751 # average overall miss latency 708system.cpu.dcache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked | 753system.cpu.dcache.demand_miss_rate::cpu.data 0.081825 # miss rate for demand accesses 754system.cpu.dcache.demand_miss_rate::total 0.081825 # miss rate for demand accesses 755system.cpu.dcache.overall_miss_rate::cpu.data 0.081825 # miss rate for overall accesses 756system.cpu.dcache.overall_miss_rate::total 0.081825 # miss rate for overall accesses 757system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71377.862595 # average ReadReq miss latency 758system.cpu.dcache.ReadReq_avg_miss_latency::total 71377.862595 # average ReadReq miss latency 759system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73370.129870 # average WriteReq miss latency 760system.cpu.dcache.WriteReq_avg_miss_latency::total 73370.129870 # average WriteReq miss latency 761system.cpu.dcache.demand_avg_miss_latency::cpu.data 72115.384615 # average overall miss latency 762system.cpu.dcache.demand_avg_miss_latency::total 72115.384615 # average overall miss latency 763system.cpu.dcache.overall_avg_miss_latency::cpu.data 72115.384615 # average overall miss latency 764system.cpu.dcache.overall_avg_miss_latency::total 72115.384615 # average overall miss latency 765system.cpu.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked |
| 709system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 766system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 710system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked | 767system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked |
| 711system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 768system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 712system.cpu.dcache.avg_blocked_cycles::no_mshrs 23.400000 # average number of cycles each access was blocked | 769system.cpu.dcache.avg_blocked_cycles::no_mshrs 46 # average number of cycles each access was blocked |
| 713system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 714system.cpu.dcache.fast_writes 0 # number of fast writes performed 715system.cpu.dcache.cache_copies 0 # number of cache copies performed | 770system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 771system.cpu.dcache.fast_writes 0 # number of fast writes performed 772system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 716system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits 717system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits 718system.cpu.dcache.demand_mshr_hits::cpu.data 69 # number of demand (read+write) MSHR hits 719system.cpu.dcache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits 720system.cpu.dcache.overall_mshr_hits::cpu.data 69 # number of overall MSHR hits 721system.cpu.dcache.overall_mshr_hits::total 69 # number of overall MSHR hits 722system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses 723system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses | 773system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits 774system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits 775system.cpu.dcache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits 776system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits 777system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits 778system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits 779system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 780system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses |
| 724system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses 725system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses | 781system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses 782system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses |
| 726system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses 727system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses 728system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses 729system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses 730system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4057000 # number of ReadReq MSHR miss cycles 731system.cpu.dcache.ReadReq_mshr_miss_latency::total 4057000 # number of ReadReq MSHR miss cycles 732system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4284000 # number of WriteReq MSHR miss cycles 733system.cpu.dcache.WriteReq_mshr_miss_latency::total 4284000 # number of WriteReq MSHR miss cycles 734system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8341000 # number of demand (read+write) MSHR miss cycles 735system.cpu.dcache.demand_mshr_miss_latency::total 8341000 # number of demand (read+write) MSHR miss cycles 736system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8341000 # number of overall MSHR miss cycles 737system.cpu.dcache.overall_mshr_miss_latency::total 8341000 # number of overall MSHR miss cycles 738system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041460 # mshr miss rate for ReadReq accesses 739system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041460 # mshr miss rate for ReadReq accesses | 783system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 784system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 785system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 786system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses 787system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4989000 # number of ReadReq MSHR miss cycles 788system.cpu.dcache.ReadReq_mshr_miss_latency::total 4989000 # number of ReadReq MSHR miss cycles 789system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5495500 # number of WriteReq MSHR miss cycles 790system.cpu.dcache.WriteReq_mshr_miss_latency::total 5495500 # number of WriteReq MSHR miss cycles 791system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10484500 # number of demand (read+write) MSHR miss cycles 792system.cpu.dcache.demand_mshr_miss_latency::total 10484500 # number of demand (read+write) MSHR miss cycles 793system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10484500 # number of overall MSHR miss cycles 794system.cpu.dcache.overall_mshr_miss_latency::total 10484500 # number of overall MSHR miss cycles 795system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040448 # mshr miss rate for ReadReq accesses 796system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040448 # mshr miss rate for ReadReq accesses |
| 740system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses 741system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses | 797system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses 798system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses |
| 742system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for demand accesses 743system.cpu.dcache.demand_mshr_miss_rate::total 0.056448 # mshr miss rate for demand accesses 744system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for overall accesses 745system.cpu.dcache.overall_mshr_miss_rate::total 0.056448 # mshr miss rate for overall accesses 746system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60552.238806 # average ReadReq mshr miss latency 747system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60552.238806 # average ReadReq mshr miss latency 748system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55636.363636 # average WriteReq mshr miss latency 749system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55636.363636 # average WriteReq mshr miss latency 750system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57923.611111 # average overall mshr miss latency 751system.cpu.dcache.demand_avg_mshr_miss_latency::total 57923.611111 # average overall mshr miss latency 752system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57923.611111 # average overall mshr miss latency 753system.cpu.dcache.overall_avg_mshr_miss_latency::total 57923.611111 # average overall mshr miss latency | 799system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055862 # mshr miss rate for demand accesses 800system.cpu.dcache.demand_mshr_miss_rate::total 0.055862 # mshr miss rate for demand accesses 801system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055862 # mshr miss rate for overall accesses 802system.cpu.dcache.overall_mshr_miss_rate::total 0.055862 # mshr miss rate for overall accesses 803system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76753.846154 # average ReadReq mshr miss latency 804system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76753.846154 # average ReadReq mshr miss latency 805system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71370.129870 # average WriteReq mshr miss latency 806system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71370.129870 # average WriteReq mshr miss latency 807system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73834.507042 # average overall mshr miss latency 808system.cpu.dcache.demand_avg_mshr_miss_latency::total 73834.507042 # average overall mshr miss latency 809system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73834.507042 # average overall mshr miss latency 810system.cpu.dcache.overall_avg_mshr_miss_latency::total 73834.507042 # average overall mshr miss latency |
| 754system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 755 756---------- End Simulation Statistics ---------- | 811system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 812 813---------- End Simulation Statistics ---------- |