| stats.txt (9348:44d31345e360) | stats.txt (9373:26ba525347fe) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000015 # Number of seconds simulated 4sim_ticks 15014000 # Number of ticks simulated 5final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000015 # Number of seconds simulated 4sim_ticks 15014000 # Number of ticks simulated 5final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 32657 # Simulator instruction rate (inst/s) 8host_op_rate 59148 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 91121721 # Simulator tick rate (ticks/s) 10host_mem_usage 223384 # Number of bytes of host memory used 11host_seconds 0.16 # Real time elapsed on the host | 7host_inst_rate 27939 # Simulator instruction rate (inst/s) 8host_op_rate 50607 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 77954156 # Simulator tick rate (ticks/s) 10host_mem_usage 273052 # Number of bytes of host memory used 11host_seconds 0.19 # Real time elapsed on the host |
| 12sim_insts 5380 # Number of instructions simulated | 12sim_insts 5380 # Number of instructions simulated |
| 13sim_ops 9745 # Number of ops (including micro ops) simulated | 13sim_ops 9746 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28736 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 19392 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 19392 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 449 # Number of read requests responded to by this memory --- 183 unchanged lines hidden (view full) --- 205system.cpu.fetch.SquashCycles 2417 # Number of cycles fetch has spent squashing 206system.cpu.fetch.BlockedCycles 3663 # Number of cycles fetch has spent blocked 207system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 208system.cpu.fetch.PendingTrapStallCycles 144 # Number of stall cycles due to pending traps 209system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR 210system.cpu.fetch.CacheLines 1880 # Number of cache lines fetched 211system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed 212system.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total) | 14system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28736 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 19392 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 19392 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 449 # Number of read requests responded to by this memory --- 183 unchanged lines hidden (view full) --- 205system.cpu.fetch.SquashCycles 2417 # Number of cycles fetch has spent squashing 206system.cpu.fetch.BlockedCycles 3663 # Number of cycles fetch has spent blocked 207system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 208system.cpu.fetch.PendingTrapStallCycles 144 # Number of stall cycles due to pending traps 209system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR 210system.cpu.fetch.CacheLines 1880 # Number of cache lines fetched 211system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed 212system.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total) |
| 213system.cpu.fetch.rateDist::mean 1.378572 # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::stdev 2.879282 # Number of instructions fetched each cycle (Total) | 213system.cpu.fetch.rateDist::mean 1.378787 # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::stdev 2.879591 # Number of instructions fetched each cycle (Total) |
| 215system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::0 14745 79.35% 79.35% # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::1 189 1.02% 80.36% # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.rateDist::2 157 0.84% 81.21% # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::3 193 1.04% 82.25% # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::4 162 0.87% 83.12% # Number of instructions fetched each cycle (Total) | 215system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::0 14745 79.35% 79.35% # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::1 189 1.02% 80.36% # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.rateDist::2 157 0.84% 81.21% # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::3 193 1.04% 82.25% # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::4 162 0.87% 83.12% # Number of instructions fetched each cycle (Total) |
| 221system.cpu.fetch.rateDist::5 175 0.94% 84.06% # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::6 261 1.40% 85.47% # Number of instructions fetched each cycle (Total) | 221system.cpu.fetch.rateDist::5 171 0.92% 84.04% # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::6 265 1.43% 85.47% # Number of instructions fetched each cycle (Total) |
| 223system.cpu.fetch.rateDist::7 161 0.87% 86.33% # Number of instructions fetched each cycle (Total) 224system.cpu.fetch.rateDist::8 2540 13.67% 100.00% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 227system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 228system.cpu.fetch.rateDist::total 18583 # Number of instructions fetched each cycle (Total) 229system.cpu.fetch.branchRate 0.100503 # Number of branch fetches per cycle 230system.cpu.fetch.rate 0.483266 # Number of inst fetches per cycle 231system.cpu.decode.IdleCycles 9455 # Number of cycles decode is idle 232system.cpu.decode.BlockedCycles 3616 # Number of cycles decode is blocked 233system.cpu.decode.RunCycles 3547 # Number of cycles decode is running 234system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking 235system.cpu.decode.SquashCycles 1830 # Number of cycles decode is squashing | 223system.cpu.fetch.rateDist::7 161 0.87% 86.33% # Number of instructions fetched each cycle (Total) 224system.cpu.fetch.rateDist::8 2540 13.67% 100.00% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 227system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 228system.cpu.fetch.rateDist::total 18583 # Number of instructions fetched each cycle (Total) 229system.cpu.fetch.branchRate 0.100503 # Number of branch fetches per cycle 230system.cpu.fetch.rate 0.483266 # Number of inst fetches per cycle 231system.cpu.decode.IdleCycles 9455 # Number of cycles decode is idle 232system.cpu.decode.BlockedCycles 3616 # Number of cycles decode is blocked 233system.cpu.decode.RunCycles 3547 # Number of cycles decode is running 234system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking 235system.cpu.decode.SquashCycles 1830 # Number of cycles decode is squashing |
| 236system.cpu.decode.DecodedInsts 24449 # Number of instructions handled by decode | 236system.cpu.decode.DecodedInsts 24452 # Number of instructions handled by decode |
| 237system.cpu.rename.SquashCycles 1830 # Number of cycles rename is squashing 238system.cpu.rename.IdleCycles 9798 # Number of cycles rename is idle 239system.cpu.rename.BlockCycles 2386 # Number of cycles rename is blocking 240system.cpu.rename.serializeStallCycles 485 # count of cycles rename stalled for serializing inst 241system.cpu.rename.RunCycles 3325 # Number of cycles rename is running 242system.cpu.rename.UnblockCycles 759 # Number of cycles rename is unblocking | 237system.cpu.rename.SquashCycles 1830 # Number of cycles rename is squashing 238system.cpu.rename.IdleCycles 9798 # Number of cycles rename is idle 239system.cpu.rename.BlockCycles 2386 # Number of cycles rename is blocking 240system.cpu.rename.serializeStallCycles 485 # count of cycles rename stalled for serializing inst 241system.cpu.rename.RunCycles 3325 # Number of cycles rename is running 242system.cpu.rename.UnblockCycles 759 # Number of cycles rename is unblocking |
| 243system.cpu.rename.RenamedInsts 22967 # Number of instructions processed by rename | 243system.cpu.rename.RenamedInsts 22970 # Number of instructions processed by rename |
| 244system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full 245system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full 246system.cpu.rename.LSQFullEvents 640 # Number of times rename has blocked due to LSQ full | 244system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full 245system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full 246system.cpu.rename.LSQFullEvents 640 # Number of times rename has blocked due to LSQ full |
| 247system.cpu.rename.RenamedOperands 25104 # Number of destination operands rename has renamed 248system.cpu.rename.RenameLookups 55188 # Number of register rename lookups that rename has made 249system.cpu.rename.int_rename_lookups 55172 # Number of integer rename lookups | 247system.cpu.rename.RenamedOperands 25107 # Number of destination operands rename has renamed 248system.cpu.rename.RenameLookups 55203 # Number of register rename lookups that rename has made 249system.cpu.rename.int_rename_lookups 55187 # Number of integer rename lookups |
| 250system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups | 250system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups |
| 251system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed 252system.cpu.rename.UndoneMaps 14044 # Number of HB maps that are undone due to squashing | 251system.cpu.rename.CommittedMaps 11061 # Number of HB maps that are committed 252system.cpu.rename.UndoneMaps 14046 # Number of HB maps that are undone due to squashing |
| 253system.cpu.rename.serializingInsts 31 # count of serializing insts renamed 254system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed 255system.cpu.rename.skidInsts 2021 # count of insts added to the skid buffer 256system.cpu.memDep0.insertedLoads 2205 # Number of loads inserted to the mem dependence unit. | 253system.cpu.rename.serializingInsts 31 # count of serializing insts renamed 254system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed 255system.cpu.rename.skidInsts 2021 # count of insts added to the skid buffer 256system.cpu.memDep0.insertedLoads 2205 # Number of loads inserted to the mem dependence unit. |
| 257system.cpu.memDep0.insertedStores 1755 # Number of stores inserted to the mem dependence unit. | 257system.cpu.memDep0.insertedStores 1757 # Number of stores inserted to the mem dependence unit. |
| 258system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. 259system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. | 258system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. 259system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. |
| 260system.cpu.iq.iqInstsAdded 20454 # Number of instructions added to the IQ (excludes non-spec) 261system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ 262system.cpu.iq.iqInstsIssued 17349 # Number of instructions issued | 260system.cpu.iq.iqInstsAdded 20458 # Number of instructions added to the IQ (excludes non-spec) 261system.cpu.iq.iqNonSpecInstsAdded 35 # Number of non-speculative instructions added to the IQ 262system.cpu.iq.iqInstsIssued 17350 # Number of instructions issued |
| 263system.cpu.iq.iqSquashedInstsIssued 213 # Number of squashed instructions issued | 263system.cpu.iq.iqSquashedInstsIssued 213 # Number of squashed instructions issued |
| 264system.cpu.iq.iqSquashedInstsExamined 9974 # Number of squashed instructions iterated over during squash; mainly for profiling 265system.cpu.iq.iqSquashedOperandsExamined 13873 # Number of squashed operands that are examined and possibly removed from graph 266system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed | 264system.cpu.iq.iqSquashedInstsExamined 9975 # Number of squashed instructions iterated over during squash; mainly for profiling 265system.cpu.iq.iqSquashedOperandsExamined 13877 # Number of squashed operands that are examined and possibly removed from graph 266system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed |
| 267system.cpu.iq.issued_per_cycle::samples 18583 # Number of insts issued each cycle | 267system.cpu.iq.issued_per_cycle::samples 18583 # Number of insts issued each cycle |
| 268system.cpu.iq.issued_per_cycle::mean 0.933595 # Number of insts issued each cycle 269system.cpu.iq.issued_per_cycle::stdev 1.794406 # Number of insts issued each cycle | 268system.cpu.iq.issued_per_cycle::mean 0.933649 # Number of insts issued each cycle 269system.cpu.iq.issued_per_cycle::stdev 1.794423 # Number of insts issued each cycle |
| 270system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 271system.cpu.iq.issued_per_cycle::0 13202 71.04% 71.04% # Number of insts issued each cycle | 270system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 271system.cpu.iq.issued_per_cycle::0 13202 71.04% 71.04% # Number of insts issued each cycle |
| 272system.cpu.iq.issued_per_cycle::1 1386 7.46% 78.50% # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::2 1042 5.61% 84.11% # Number of insts issued each cycle | 272system.cpu.iq.issued_per_cycle::1 1385 7.45% 78.50% # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::2 1043 5.61% 84.11% # Number of insts issued each cycle |
| 274system.cpu.iq.issued_per_cycle::3 691 3.72% 87.83% # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::4 742 3.99% 91.82% # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::5 623 3.35% 95.17% # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::6 598 3.22% 98.39% # Number of insts issued each cycle 278system.cpu.iq.issued_per_cycle::7 257 1.38% 99.77% # Number of insts issued each cycle 279system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle 280system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 281system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle --- 28 unchanged lines hidden (view full) --- 310system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.53% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.53% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.53% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.53% # attempts to use FU when none available 314system.cpu.iq.fu_full::MemRead 19 10.67% 88.20% # attempts to use FU when none available 315system.cpu.iq.fu_full::MemWrite 21 11.80% 100.00% # attempts to use FU when none available 316system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 317system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 274system.cpu.iq.issued_per_cycle::3 691 3.72% 87.83% # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::4 742 3.99% 91.82% # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::5 623 3.35% 95.17% # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::6 598 3.22% 98.39% # Number of insts issued each cycle 278system.cpu.iq.issued_per_cycle::7 257 1.38% 99.77% # Number of insts issued each cycle 279system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle 280system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 281system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle --- 28 unchanged lines hidden (view full) --- 310system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.53% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.53% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.53% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.53% # attempts to use FU when none available 314system.cpu.iq.fu_full::MemRead 19 10.67% 88.20% # attempts to use FU when none available 315system.cpu.iq.fu_full::MemWrite 21 11.80% 100.00% # attempts to use FU when none available 316system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 317system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 318system.cpu.iq.FU_type_0::No_OpClass 5 0.03% 0.03% # Type of FU issued 319system.cpu.iq.FU_type_0::IntAlu 13962 80.48% 80.51% # Type of FU issued | 318system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued 319system.cpu.iq.FU_type_0::IntAlu 13964 80.48% 80.51% # Type of FU issued |
| 320system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.51% # Type of FU issued 321system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.51% # Type of FU issued 322system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.51% # Type of FU issued 323system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.51% # Type of FU issued 324system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.51% # Type of FU issued 325system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.51% # Type of FU issued 326system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.51% # Type of FU issued 327system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.51% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 340system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.51% # Type of FU issued 341system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.51% # Type of FU issued 342system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.51% # Type of FU issued 343system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.51% # Type of FU issued 344system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.51% # Type of FU issued 345system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.51% # Type of FU issued 346system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.51% # Type of FU issued 347system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.51% # Type of FU issued | 320system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.51% # Type of FU issued 321system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.51% # Type of FU issued 322system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.51% # Type of FU issued 323system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.51% # Type of FU issued 324system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.51% # Type of FU issued 325system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.51% # Type of FU issued 326system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.51% # Type of FU issued 327system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.51% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 340system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.51% # Type of FU issued 341system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.51% # Type of FU issued 342system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.51% # Type of FU issued 343system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.51% # Type of FU issued 344system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.51% # Type of FU issued 345system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.51% # Type of FU issued 346system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.51% # Type of FU issued 347system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.51% # Type of FU issued |
| 348system.cpu.iq.FU_type_0::MemRead 1900 10.95% 91.46% # Type of FU issued 349system.cpu.iq.FU_type_0::MemWrite 1482 8.54% 100.00% # Type of FU issued | 348system.cpu.iq.FU_type_0::MemRead 1899 10.95% 91.45% # Type of FU issued 349system.cpu.iq.FU_type_0::MemWrite 1483 8.55% 100.00% # Type of FU issued |
| 350system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 351system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 350system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 351system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 352system.cpu.iq.FU_type_0::total 17349 # Type of FU issued 353system.cpu.iq.rate 0.577742 # Inst issue rate | 352system.cpu.iq.FU_type_0::total 17350 # Type of FU issued 353system.cpu.iq.rate 0.577775 # Inst issue rate |
| 354system.cpu.iq.fu_busy_cnt 178 # FU busy when requested | 354system.cpu.iq.fu_busy_cnt 178 # FU busy when requested |
| 355system.cpu.iq.fu_busy_rate 0.010260 # FU busy rate (busy events/executed inst) 356system.cpu.iq.int_inst_queue_reads 53664 # Number of integer instruction queue reads 357system.cpu.iq.int_inst_queue_writes 30472 # Number of integer instruction queue writes 358system.cpu.iq.int_inst_queue_wakeup_accesses 16003 # Number of integer instruction queue wakeup accesses | 355system.cpu.iq.fu_busy_rate 0.010259 # FU busy rate (busy events/executed inst) 356system.cpu.iq.int_inst_queue_reads 53666 # Number of integer instruction queue reads 357system.cpu.iq.int_inst_queue_writes 30475 # Number of integer instruction queue writes 358system.cpu.iq.int_inst_queue_wakeup_accesses 16004 # Number of integer instruction queue wakeup accesses |
| 359system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 360system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 361system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses | 359system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 360system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 361system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses |
| 362system.cpu.iq.int_alu_accesses 17518 # Number of integer alu accesses | 362system.cpu.iq.int_alu_accesses 17520 # Number of integer alu accesses |
| 363system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses | 363system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses |
| 364system.cpu.iew.lsq.thread0.forwLoads 157 # Number of loads that had data forwarded from stores | 364system.cpu.iew.lsq.thread0.forwLoads 158 # Number of loads that had data forwarded from stores |
| 365system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 366system.cpu.iew.lsq.thread0.squashedLoads 1153 # Number of loads squashed 367system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed 368system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations | 365system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 366system.cpu.iew.lsq.thread0.squashedLoads 1153 # Number of loads squashed 367system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed 368system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations |
| 369system.cpu.iew.lsq.thread0.squashedStores 821 # Number of stores squashed | 369system.cpu.iew.lsq.thread0.squashedStores 822 # Number of stores squashed |
| 370system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 371system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 372system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 373system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked 374system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 375system.cpu.iew.iewSquashCycles 1830 # Number of cycles IEW is squashing 376system.cpu.iew.iewBlockCycles 1703 # Number of cycles IEW is blocking 377system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking | 370system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 371system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 372system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 373system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked 374system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 375system.cpu.iew.iewSquashCycles 1830 # Number of cycles IEW is squashing 376system.cpu.iew.iewBlockCycles 1703 # Number of cycles IEW is blocking 377system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking |
| 378system.cpu.iew.iewDispatchedInsts 20491 # Number of instructions dispatched to IQ | 378system.cpu.iew.iewDispatchedInsts 20493 # Number of instructions dispatched to IQ |
| 379system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch 380system.cpu.iew.iewDispLoadInsts 2205 # Number of dispatched load instructions | 379system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch 380system.cpu.iew.iewDispLoadInsts 2205 # Number of dispatched load instructions |
| 381system.cpu.iew.iewDispStoreInsts 1755 # Number of dispatched store instructions 382system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions | 381system.cpu.iew.iewDispStoreInsts 1757 # Number of dispatched store instructions 382system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions |
| 383system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 384system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 385system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations 386system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly 387system.cpu.iew.predictedNotTakenIncorrect 601 # Number of branches that were predicted not taken incorrectly 388system.cpu.iew.branchMispredicts 657 # Number of branch mispredicts detected at execute | 383system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 384system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 385system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations 386system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly 387system.cpu.iew.predictedNotTakenIncorrect 601 # Number of branches that were predicted not taken incorrectly 388system.cpu.iew.branchMispredicts 657 # Number of branch mispredicts detected at execute |
| 389system.cpu.iew.iewExecutedInsts 16425 # Number of executed instructions | 389system.cpu.iew.iewExecutedInsts 16426 # Number of executed instructions |
| 390system.cpu.iew.iewExecLoadInsts 1777 # Number of load instructions executed 391system.cpu.iew.iewExecSquashedInsts 924 # Number of squashed instructions skipped in execute 392system.cpu.iew.exec_swp 0 # number of swp insts executed 393system.cpu.iew.exec_nop 0 # number of nop insts executed | 390system.cpu.iew.iewExecLoadInsts 1777 # Number of load instructions executed 391system.cpu.iew.iewExecSquashedInsts 924 # Number of squashed instructions skipped in execute 392system.cpu.iew.exec_swp 0 # number of swp insts executed 393system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 394system.cpu.iew.exec_refs 3140 # number of memory reference insts executed | 394system.cpu.iew.exec_refs 3141 # number of memory reference insts executed |
| 395system.cpu.iew.exec_branches 1630 # Number of branches executed | 395system.cpu.iew.exec_branches 1630 # Number of branches executed |
| 396system.cpu.iew.exec_stores 1363 # Number of stores executed 397system.cpu.iew.exec_rate 0.546971 # Inst execution rate 398system.cpu.iew.wb_sent 16197 # cumulative count of insts sent to commit 399system.cpu.iew.wb_count 16007 # cumulative count of insts written-back 400system.cpu.iew.wb_producers 10178 # num instructions producing a value 401system.cpu.iew.wb_consumers 15727 # num instructions consuming a value | 396system.cpu.iew.exec_stores 1364 # Number of stores executed 397system.cpu.iew.exec_rate 0.547005 # Inst execution rate 398system.cpu.iew.wb_sent 16198 # cumulative count of insts sent to commit 399system.cpu.iew.wb_count 16008 # cumulative count of insts written-back 400system.cpu.iew.wb_producers 10179 # num instructions producing a value 401system.cpu.iew.wb_consumers 15729 # num instructions consuming a value |
| 402system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 402system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 403system.cpu.iew.wb_rate 0.533051 # insts written-back per cycle 404system.cpu.iew.wb_fanout 0.647167 # average fanout of values written-back | 403system.cpu.iew.wb_rate 0.533085 # insts written-back per cycle 404system.cpu.iew.wb_fanout 0.647149 # average fanout of values written-back |
| 405system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 405system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 406system.cpu.commit.commitSquashedInsts 10745 # The number of squashed insts skipped by commit 407system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards | 406system.cpu.commit.commitSquashedInsts 10746 # The number of squashed insts skipped by commit 407system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards |
| 408system.cpu.commit.branchMispredicts 566 # The number of times a branch was mispredicted 409system.cpu.commit.committed_per_cycle::samples 16753 # Number of insts commited each cycle | 408system.cpu.commit.branchMispredicts 566 # The number of times a branch was mispredicted 409system.cpu.commit.committed_per_cycle::samples 16753 # Number of insts commited each cycle |
| 410system.cpu.commit.committed_per_cycle::mean 0.581687 # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::stdev 1.458321 # Number of insts commited each cycle | 410system.cpu.commit.committed_per_cycle::mean 0.581747 # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::stdev 1.458276 # Number of insts commited each cycle |
| 412system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 412system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 413system.cpu.commit.committed_per_cycle::0 13226 78.95% 78.95% # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::1 1316 7.86% 86.80% # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::2 596 3.56% 90.36% # Number of insts commited each cycle | 413system.cpu.commit.committed_per_cycle::0 13224 78.94% 78.94% # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::1 1319 7.87% 86.81% # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::2 595 3.55% 90.36% # Number of insts commited each cycle |
| 416system.cpu.commit.committed_per_cycle::3 710 4.24% 94.60% # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::4 351 2.10% 96.69% # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::5 138 0.82% 97.52% # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::6 120 0.72% 98.23% # Number of insts commited each cycle 420system.cpu.commit.committed_per_cycle::7 75 0.45% 98.68% # Number of insts commited each cycle 421system.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle 422system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 423system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 424system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 425system.cpu.commit.committed_per_cycle::total 16753 # Number of insts commited each cycle 426system.cpu.commit.committedInsts 5380 # Number of instructions committed | 416system.cpu.commit.committed_per_cycle::3 710 4.24% 94.60% # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::4 351 2.10% 96.69% # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::5 138 0.82% 97.52% # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::6 120 0.72% 98.23% # Number of insts commited each cycle 420system.cpu.commit.committed_per_cycle::7 75 0.45% 98.68% # Number of insts commited each cycle 421system.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle 422system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 423system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 424system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 425system.cpu.commit.committed_per_cycle::total 16753 # Number of insts commited each cycle 426system.cpu.commit.committedInsts 5380 # Number of instructions committed |
| 427system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed | 427system.cpu.commit.committedOps 9746 # Number of ops (including micro ops) committed |
| 428system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 428system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 429system.cpu.commit.refs 1986 # Number of memory references committed | 429system.cpu.commit.refs 1987 # Number of memory references committed |
| 430system.cpu.commit.loads 1052 # Number of loads committed 431system.cpu.commit.membars 0 # Number of memory barriers committed 432system.cpu.commit.branches 1208 # Number of branches committed 433system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. | 430system.cpu.commit.loads 1052 # Number of loads committed 431system.cpu.commit.membars 0 # Number of memory barriers committed 432system.cpu.commit.branches 1208 # Number of branches committed 433system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. |
| 434system.cpu.commit.int_insts 9650 # Number of committed integer instructions. | 434system.cpu.commit.int_insts 9652 # Number of committed integer instructions. |
| 435system.cpu.commit.function_calls 0 # Number of function calls committed. 436system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached 437system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 435system.cpu.commit.function_calls 0 # Number of function calls committed. 436system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached 437system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 438system.cpu.rob.rob_reads 37022 # The number of ROB reads 439system.cpu.rob.rob_writes 42839 # The number of ROB writes | 438system.cpu.rob.rob_reads 37024 # The number of ROB reads 439system.cpu.rob.rob_writes 42843 # The number of ROB writes |
| 440system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself 441system.cpu.idleCycles 11446 # Total number of cycles that the CPU has spent unscheduled due to idling 442system.cpu.committedInsts 5380 # Number of Instructions Simulated | 440system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself 441system.cpu.idleCycles 11446 # Total number of cycles that the CPU has spent unscheduled due to idling 442system.cpu.committedInsts 5380 # Number of Instructions Simulated |
| 443system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated | 443system.cpu.committedOps 9746 # Number of Ops (including micro ops) Simulated |
| 444system.cpu.committedInsts_total 5380 # Number of Instructions Simulated 445system.cpu.cpi 5.581599 # CPI: Cycles Per Instruction 446system.cpu.cpi_total 5.581599 # CPI: Total CPI of All Threads 447system.cpu.ipc 0.179160 # IPC: Instructions Per Cycle 448system.cpu.ipc_total 0.179160 # IPC: Total IPC of All Threads | 444system.cpu.committedInsts_total 5380 # Number of Instructions Simulated 445system.cpu.cpi 5.581599 # CPI: Cycles Per Instruction 446system.cpu.cpi_total 5.581599 # CPI: Total CPI of All Threads 447system.cpu.ipc 0.179160 # IPC: Instructions Per Cycle 448system.cpu.ipc_total 0.179160 # IPC: Total IPC of All Threads |
| 449system.cpu.int_regfile_reads 28874 # number of integer regfile reads 450system.cpu.int_regfile_writes 17232 # number of integer regfile writes | 449system.cpu.int_regfile_reads 28877 # number of integer regfile reads 450system.cpu.int_regfile_writes 17233 # number of integer regfile writes |
| 451system.cpu.fp_regfile_reads 4 # number of floating regfile reads | 451system.cpu.fp_regfile_reads 4 # number of floating regfile reads |
| 452system.cpu.misc_regfile_reads 7155 # number of misc regfile reads | 452system.cpu.misc_regfile_reads 7157 # number of misc regfile reads |
| 453system.cpu.icache.replacements 0 # number of replacements 454system.cpu.icache.tagsinuse 144.838361 # Cycle average of tags in use 455system.cpu.icache.total_refs 1482 # Total number of references to valid blocks. 456system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. 457system.cpu.icache.avg_refs 4.875000 # Average number of references to valid blocks. 458system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 459system.cpu.icache.occ_blocks::cpu.inst 144.838361 # Average occupied blocks per requestor 460system.cpu.icache.occ_percent::cpu.inst 0.070722 # Average percentage of cache occupancy --- 68 unchanged lines hidden (view full) --- 529system.cpu.icache.overall_mshr_miss_rate::total 0.161702 # mshr miss rate for overall accesses 530system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50860.197368 # average ReadReq mshr miss latency 531system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50860.197368 # average ReadReq mshr miss latency 532system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency 533system.cpu.icache.demand_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency 534system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency 535system.cpu.icache.overall_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency 536system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 453system.cpu.icache.replacements 0 # number of replacements 454system.cpu.icache.tagsinuse 144.838361 # Cycle average of tags in use 455system.cpu.icache.total_refs 1482 # Total number of references to valid blocks. 456system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. 457system.cpu.icache.avg_refs 4.875000 # Average number of references to valid blocks. 458system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 459system.cpu.icache.occ_blocks::cpu.inst 144.838361 # Average occupied blocks per requestor 460system.cpu.icache.occ_percent::cpu.inst 0.070722 # Average percentage of cache occupancy --- 68 unchanged lines hidden (view full) --- 529system.cpu.icache.overall_mshr_miss_rate::total 0.161702 # mshr miss rate for overall accesses 530system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50860.197368 # average ReadReq mshr miss latency 531system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50860.197368 # average ReadReq mshr miss latency 532system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency 533system.cpu.icache.demand_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency 534system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency 535system.cpu.icache.overall_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency 536system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 537system.cpu.dcache.replacements 0 # number of replacements 538system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use 539system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks. 540system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks. 541system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks. 542system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 543system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor 544system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy 545system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy 546system.cpu.dcache.ReadReq_hits::cpu.data 1425 # number of ReadReq hits 547system.cpu.dcache.ReadReq_hits::total 1425 # number of ReadReq hits 548system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits 549system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits 550system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits 551system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits 552system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits 553system.cpu.dcache.overall_hits::total 2284 # number of overall hits 554system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses 555system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses 556system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses 557system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses 558system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses 559system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses 560system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses 561system.cpu.dcache.overall_misses::total 202 # number of overall misses 562system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336000 # number of ReadReq miss cycles 563system.cpu.dcache.ReadReq_miss_latency::total 6336000 # number of ReadReq miss cycles 564system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles 565system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles 566system.cpu.dcache.demand_miss_latency::cpu.data 10556500 # number of demand (read+write) miss cycles 567system.cpu.dcache.demand_miss_latency::total 10556500 # number of demand (read+write) miss cycles 568system.cpu.dcache.overall_miss_latency::cpu.data 10556500 # number of overall miss cycles 569system.cpu.dcache.overall_miss_latency::total 10556500 # number of overall miss cycles 570system.cpu.dcache.ReadReq_accesses::cpu.data 1551 # number of ReadReq accesses(hits+misses) 571system.cpu.dcache.ReadReq_accesses::total 1551 # number of ReadReq accesses(hits+misses) 572system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 573system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) 574system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses 575system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses 576system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses 577system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses 578system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081238 # miss rate for ReadReq accesses 579system.cpu.dcache.ReadReq_miss_rate::total 0.081238 # miss rate for ReadReq accesses 580system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses 581system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses 582system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses 583system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses 584system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses 585system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses 586system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50285.714286 # average ReadReq miss latency 587system.cpu.dcache.ReadReq_avg_miss_latency::total 50285.714286 # average ReadReq miss latency 588system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency 589system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency 590system.cpu.dcache.demand_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency 591system.cpu.dcache.demand_avg_miss_latency::total 52259.900990 # average overall miss latency 592system.cpu.dcache.overall_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency 593system.cpu.dcache.overall_avg_miss_latency::total 52259.900990 # average overall miss latency 594system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked 595system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 596system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 597system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 598system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked 599system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 600system.cpu.dcache.fast_writes 0 # number of fast writes performed 601system.cpu.dcache.cache_copies 0 # number of cache copies performed 602system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits 603system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits 604system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits 605system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits 606system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits 607system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits 608system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses 609system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses 610system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses 611system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses 612system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 613system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 614system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 615system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 616system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735000 # number of ReadReq MSHR miss cycles 617system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735000 # number of ReadReq MSHR miss cycles 618system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles 619system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles 620system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7803500 # number of demand (read+write) MSHR miss cycles 621system.cpu.dcache.demand_mshr_miss_latency::total 7803500 # number of demand (read+write) MSHR miss cycles 622system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7803500 # number of overall MSHR miss cycles 623system.cpu.dcache.overall_mshr_miss_latency::total 7803500 # number of overall MSHR miss cycles 624system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045777 # mshr miss rate for ReadReq accesses 625system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045777 # mshr miss rate for ReadReq accesses 626system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses 627system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses 628system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses 629system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses 630system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses 631system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses 632system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.633803 # average ReadReq mshr miss latency 633system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.633803 # average ReadReq mshr miss latency 634system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency 635system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency 636system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency 637system.cpu.dcache.demand_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency 638system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency 639system.cpu.dcache.overall_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency 640system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 537system.cpu.l2cache.replacements 0 # number of replacements 538system.cpu.l2cache.tagsinuse 178.021325 # Cycle average of tags in use 539system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 540system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. 541system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. 542system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 543system.cpu.l2cache.occ_blocks::cpu.inst 144.985294 # Average occupied blocks per requestor 544system.cpu.l2cache.occ_blocks::cpu.data 33.036031 # Average occupied blocks per requestor --- 109 unchanged lines hidden (view full) --- 654system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39856.710526 # average ReadExReq mshr miss latency 655system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency 656system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency 657system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency 658system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency 659system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency 660system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency 661system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 641system.cpu.l2cache.replacements 0 # number of replacements 642system.cpu.l2cache.tagsinuse 178.021325 # Cycle average of tags in use 643system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 644system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. 645system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. 646system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 647system.cpu.l2cache.occ_blocks::cpu.inst 144.985294 # Average occupied blocks per requestor 648system.cpu.l2cache.occ_blocks::cpu.data 33.036031 # Average occupied blocks per requestor --- 109 unchanged lines hidden (view full) --- 758system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39856.710526 # average ReadExReq mshr miss latency 759system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency 760system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency 761system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency 762system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency 763system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency 764system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency 765system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 662system.cpu.dcache.replacements 0 # number of replacements 663system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use 664system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks. 665system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks. 666system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks. 667system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 668system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor 669system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy 670system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy 671system.cpu.dcache.ReadReq_hits::cpu.data 1426 # number of ReadReq hits 672system.cpu.dcache.ReadReq_hits::total 1426 # number of ReadReq hits 673system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits 674system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits 675system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits 676system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits 677system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits 678system.cpu.dcache.overall_hits::total 2284 # number of overall hits 679system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses 680system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses 681system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses 682system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses 683system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses 684system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses 685system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses 686system.cpu.dcache.overall_misses::total 202 # number of overall misses 687system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336000 # number of ReadReq miss cycles 688system.cpu.dcache.ReadReq_miss_latency::total 6336000 # number of ReadReq miss cycles 689system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles 690system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles 691system.cpu.dcache.demand_miss_latency::cpu.data 10556500 # number of demand (read+write) miss cycles 692system.cpu.dcache.demand_miss_latency::total 10556500 # number of demand (read+write) miss cycles 693system.cpu.dcache.overall_miss_latency::cpu.data 10556500 # number of overall miss cycles 694system.cpu.dcache.overall_miss_latency::total 10556500 # number of overall miss cycles 695system.cpu.dcache.ReadReq_accesses::cpu.data 1552 # number of ReadReq accesses(hits+misses) 696system.cpu.dcache.ReadReq_accesses::total 1552 # number of ReadReq accesses(hits+misses) 697system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) 698system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) 699system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses 700system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses 701system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses 702system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses 703system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081186 # miss rate for ReadReq accesses 704system.cpu.dcache.ReadReq_miss_rate::total 0.081186 # miss rate for ReadReq accesses 705system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses 706system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses 707system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses 708system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses 709system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses 710system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses 711system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50285.714286 # average ReadReq miss latency 712system.cpu.dcache.ReadReq_avg_miss_latency::total 50285.714286 # average ReadReq miss latency 713system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency 714system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency 715system.cpu.dcache.demand_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency 716system.cpu.dcache.demand_avg_miss_latency::total 52259.900990 # average overall miss latency 717system.cpu.dcache.overall_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency 718system.cpu.dcache.overall_avg_miss_latency::total 52259.900990 # average overall miss latency 719system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked 720system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 721system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 722system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 723system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked 724system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 725system.cpu.dcache.fast_writes 0 # number of fast writes performed 726system.cpu.dcache.cache_copies 0 # number of cache copies performed 727system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits 728system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits 729system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits 730system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits 731system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits 732system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits 733system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses 734system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses 735system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses 736system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses 737system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 738system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 739system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 740system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 741system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735000 # number of ReadReq MSHR miss cycles 742system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735000 # number of ReadReq MSHR miss cycles 743system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles 744system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles 745system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7803500 # number of demand (read+write) MSHR miss cycles 746system.cpu.dcache.demand_mshr_miss_latency::total 7803500 # number of demand (read+write) MSHR miss cycles 747system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7803500 # number of overall MSHR miss cycles 748system.cpu.dcache.overall_mshr_miss_latency::total 7803500 # number of overall MSHR miss cycles 749system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045747 # mshr miss rate for ReadReq accesses 750system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045747 # mshr miss rate for ReadReq accesses 751system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses 752system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses 753system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses 754system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses 755system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses 756system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses 757system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.633803 # average ReadReq mshr miss latency 758system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.633803 # average ReadReq mshr miss latency 759system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency 760system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency 761system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency 762system.cpu.dcache.demand_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency 763system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency 764system.cpu.dcache.overall_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency 765system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 766 767---------- End Simulation Statistics ---------- | 766 767---------- End Simulation Statistics ---------- |