| stats.txt (9312:e05e1b69ebf2) | stats.txt (9322:01c8c5ff2c3b) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 12009000 # Number of ticks simulated 5final_tick 12009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000015 # Number of seconds simulated 4sim_ticks 15249000 # Number of ticks simulated 5final_tick 15249000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 10920 # Simulator instruction rate (inst/s) 8host_op_rate 19780 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 24373770 # Simulator tick rate (ticks/s) 10host_mem_usage 225464 # Number of bytes of host memory used 11host_seconds 0.49 # Real time elapsed on the host | 7host_inst_rate 41998 # Simulator instruction rate (inst/s) 8host_op_rate 76065 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 119014725 # Simulator tick rate (ticks/s) 10host_mem_usage 225728 # Number of bytes of host memory used 11host_seconds 0.13 # Real time elapsed on the host |
| 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9745 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9280 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28800 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 450 # Number of read requests responded to by this memory | 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9745 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9280 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28800 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 450 # Number of read requests responded to by this memory |
| 22system.physmem.bw_read::cpu.inst 1625447581 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 772753768 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2398201349 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1625447581 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1625447581 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1625447581 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 772753768 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2398201349 # Total bandwidth to/from this memory (bytes/s) | 22system.physmem.bw_read::cpu.inst 1280083940 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 608564496 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1888648436 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1280083940 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1280083940 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1280083940 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 608564496 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1888648436 # Total bandwidth to/from this memory (bytes/s) |
| 30system.physmem.readReqs 451 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 28800 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 28800 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 40 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 20 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 55 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 23 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 52 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis | 30system.physmem.readReqs 451 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 28800 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 28800 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 40 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 20 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 55 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 23 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 52 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis |
| 49system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis | 49system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis |
| 50system.physmem.perBankRdReqs::11 40 # Track reads on a per bank basis | 50system.physmem.perBankRdReqs::11 40 # Track reads on a per bank basis |
| 51system.physmem.perBankRdReqs::12 13 # Track reads on a per bank basis | 51system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis |
| 52system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis --- 5 unchanged lines hidden (view full) --- 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 52system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis --- 5 unchanged lines hidden (view full) --- 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 11990500 # Total gap between requests | 73system.physmem.totGap 15226500 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 451 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 11 unchanged lines hidden (view full) --- 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 451 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 11 unchanged lines hidden (view full) --- 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes |
| 101system.physmem.rdQLenPdf::0 221 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::0 230 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 155 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see |
| 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 45 unchanged lines hidden (view full) --- 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 45 unchanged lines hidden (view full) --- 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 167system.physmem.totQLat 3096951 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 13440951 # Sum of mem lat for all requests | 167system.physmem.totQLat 1663951 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 11993951 # Sum of mem lat for all requests |
| 169system.physmem.totBusLat 1804000 # Total cycles spent in databus access | 169system.physmem.totBusLat 1804000 # Total cycles spent in databus access |
| 170system.physmem.totBankLat 8540000 # Total cycles spent in bank access 171system.physmem.avgQLat 6866.85 # Average queueing delay per request 172system.physmem.avgBankLat 18935.70 # Average bank access latency per request | 170system.physmem.totBankLat 8526000 # Total cycles spent in bank access 171system.physmem.avgQLat 3689.47 # Average queueing delay per request 172system.physmem.avgBankLat 18904.66 # Average bank access latency per request |
| 173system.physmem.avgBusLat 4000.00 # Average bus latency per request | 173system.physmem.avgBusLat 4000.00 # Average bus latency per request |
| 174system.physmem.avgMemAccLat 29802.55 # Average memory access latency 175system.physmem.avgRdBW 2398.20 # Average achieved read bandwidth in MB/s | 174system.physmem.avgMemAccLat 26594.13 # Average memory access latency 175system.physmem.avgRdBW 1888.65 # Average achieved read bandwidth in MB/s |
| 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s | 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 177system.physmem.avgConsumedRdBW 2398.20 # Average consumed read bandwidth in MB/s | 177system.physmem.avgConsumedRdBW 1888.65 # Average consumed read bandwidth in MB/s |
| 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s | 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s |
| 180system.physmem.busUtil 14.99 # Data bus utilization in percentage 181system.physmem.avgRdQLen 1.12 # Average read queue length over time | 180system.physmem.busUtil 11.80 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.79 # Average read queue length over time |
| 182system.physmem.avgWrQLen 0.00 # Average write queue length over time | 182system.physmem.avgWrQLen 0.00 # Average write queue length over time |
| 183system.physmem.readRowHits 353 # Number of row buffer hits during reads | 183system.physmem.readRowHits 354 # Number of row buffer hits during reads |
| 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 185system.physmem.readRowHitRate 78.27 # Row buffer hit rate for reads | 185system.physmem.readRowHitRate 78.49 # Row buffer hit rate for reads |
| 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 187system.physmem.avgGap 26586.47 # Average gap between requests | 187system.physmem.avgGap 33761.64 # Average gap between requests |
| 188system.cpu.workload.num_syscalls 11 # Number of system calls | 188system.cpu.workload.num_syscalls 11 # Number of system calls |
| 189system.cpu.numCycles 24019 # number of cpu cycles simulated | 189system.cpu.numCycles 30499 # number of cpu cycles simulated |
| 190system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 191system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 190system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 191system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 192system.cpu.BPredUnit.lookups 3185 # Number of BP lookups 193system.cpu.BPredUnit.condPredicted 3185 # Number of conditional branches predicted 194system.cpu.BPredUnit.condIncorrect 589 # Number of conditional branches incorrect 195system.cpu.BPredUnit.BTBLookups 2591 # Number of BTB lookups | 192system.cpu.BPredUnit.lookups 3124 # Number of BP lookups 193system.cpu.BPredUnit.condPredicted 3124 # Number of conditional branches predicted 194system.cpu.BPredUnit.condIncorrect 575 # Number of conditional branches incorrect 195system.cpu.BPredUnit.BTBLookups 2554 # Number of BTB lookups |
| 196system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits 197system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 198system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 199system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. | 196system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits 197system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 198system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 199system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. |
| 200system.cpu.fetch.icacheStallCycles 8560 # Number of cycles fetch is stalled on an Icache miss 201system.cpu.fetch.Insts 15317 # Number of instructions fetch has processed 202system.cpu.fetch.Branches 3185 # Number of branches that fetch encountered | 200system.cpu.fetch.icacheStallCycles 9097 # Number of cycles fetch is stalled on an Icache miss 201system.cpu.fetch.Insts 15002 # Number of instructions fetch has processed 202system.cpu.fetch.Branches 3124 # Number of branches that fetch encountered |
| 203system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken | 203system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken |
| 204system.cpu.fetch.Cycles 4169 # Number of cycles fetch has run and was not squashing or blocked 205system.cpu.fetch.SquashCycles 2596 # Number of cycles fetch has spent squashing 206system.cpu.fetch.BlockedCycles 2320 # Number of cycles fetch has spent blocked 207system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 208system.cpu.fetch.PendingTrapStallCycles 142 # Number of stall cycles due to pending traps 209system.cpu.fetch.CacheLines 1999 # Number of cache lines fetched 210system.cpu.fetch.IcacheSquashes 297 # Number of outstanding Icache misses that were squashed 211system.cpu.fetch.rateDist::samples 17196 # Number of instructions fetched each cycle (Total) 212system.cpu.fetch.rateDist::mean 1.587346 # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::stdev 3.039622 # Number of instructions fetched each cycle (Total) | 204system.cpu.fetch.Cycles 4073 # Number of cycles fetch has run and was not squashing or blocked 205system.cpu.fetch.SquashCycles 2573 # Number of cycles fetch has spent squashing 206system.cpu.fetch.BlockedCycles 3671 # Number of cycles fetch has spent blocked 207system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 208system.cpu.fetch.PendingTrapStallCycles 217 # Number of stall cycles due to pending traps 209system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR 210system.cpu.fetch.CacheLines 1972 # Number of cache lines fetched 211system.cpu.fetch.IcacheSquashes 311 # Number of outstanding Icache misses that were squashed 212system.cpu.fetch.rateDist::samples 19065 # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::mean 1.398846 # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::stdev 2.899430 # Number of instructions fetched each cycle (Total) |
| 214system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 215system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 215system.cpu.fetch.rateDist::0 13133 76.37% 76.37% # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::1 180 1.05% 77.42% # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::2 163 0.95% 78.37% # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.rateDist::3 205 1.19% 79.56% # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::4 179 1.04% 80.60% # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::5 184 1.07% 81.67% # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::6 242 1.41% 83.08% # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::7 193 1.12% 84.20% # Number of instructions fetched each cycle (Total) 223system.cpu.fetch.rateDist::8 2717 15.80% 100.00% # Number of instructions fetched each cycle (Total) | 216system.cpu.fetch.rateDist::0 15096 79.18% 79.18% # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::1 179 0.94% 80.12% # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.rateDist::2 149 0.78% 80.90% # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::3 207 1.09% 81.99% # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::4 179 0.94% 82.93% # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::5 177 0.93% 83.86% # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::6 231 1.21% 85.07% # Number of instructions fetched each cycle (Total) 223system.cpu.fetch.rateDist::7 192 1.01% 86.07% # Number of instructions fetched each cycle (Total) 224system.cpu.fetch.rateDist::8 2655 13.93% 100.00% # Number of instructions fetched each cycle (Total) |
| 224system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 225system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 227system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 227system.cpu.fetch.rateDist::total 17196 # Number of instructions fetched each cycle (Total) 228system.cpu.fetch.branchRate 0.132603 # Number of branch fetches per cycle 229system.cpu.fetch.rate 0.637703 # Number of inst fetches per cycle 230system.cpu.decode.IdleCycles 9044 # Number of cycles decode is idle 231system.cpu.decode.BlockedCycles 2277 # Number of cycles decode is blocked 232system.cpu.decode.RunCycles 3768 # Number of cycles decode is running 233system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking 234system.cpu.decode.SquashCycles 1981 # Number of cycles decode is squashing 235system.cpu.decode.DecodedInsts 26083 # Number of instructions handled by decode 236system.cpu.rename.SquashCycles 1981 # Number of cycles rename is squashing 237system.cpu.rename.IdleCycles 9405 # Number of cycles rename is idle 238system.cpu.rename.BlockCycles 1279 # Number of cycles rename is blocking 239system.cpu.rename.serializeStallCycles 293 # count of cycles rename stalled for serializing inst 240system.cpu.rename.RunCycles 3524 # Number of cycles rename is running 241system.cpu.rename.UnblockCycles 714 # Number of cycles rename is unblocking 242system.cpu.rename.RenamedInsts 24459 # Number of instructions processed by rename 243system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 244system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full 245system.cpu.rename.LSQFullEvents 613 # Number of times rename has blocked due to LSQ full 246system.cpu.rename.RenamedOperands 26793 # Number of destination operands rename has renamed 247system.cpu.rename.RenameLookups 58583 # Number of register rename lookups that rename has made 248system.cpu.rename.int_rename_lookups 58567 # Number of integer rename lookups | 228system.cpu.fetch.rateDist::total 19065 # Number of instructions fetched each cycle (Total) 229system.cpu.fetch.branchRate 0.102430 # Number of branch fetches per cycle 230system.cpu.fetch.rate 0.491885 # Number of inst fetches per cycle 231system.cpu.decode.IdleCycles 9663 # Number of cycles decode is idle 232system.cpu.decode.BlockedCycles 3644 # Number of cycles decode is blocked 233system.cpu.decode.RunCycles 3665 # Number of cycles decode is running 234system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking 235system.cpu.decode.SquashCycles 1953 # Number of cycles decode is squashing 236system.cpu.decode.DecodedInsts 25430 # Number of instructions handled by decode 237system.cpu.rename.SquashCycles 1953 # Number of cycles rename is squashing 238system.cpu.rename.IdleCycles 10013 # Number of cycles rename is idle 239system.cpu.rename.BlockCycles 2382 # Number of cycles rename is blocking 240system.cpu.rename.serializeStallCycles 508 # count of cycles rename stalled for serializing inst 241system.cpu.rename.RunCycles 3439 # Number of cycles rename is running 242system.cpu.rename.UnblockCycles 770 # Number of cycles rename is unblocking 243system.cpu.rename.RenamedInsts 23869 # Number of instructions processed by rename 244system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full 245system.cpu.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full 246system.cpu.rename.LSQFullEvents 648 # Number of times rename has blocked due to LSQ full 247system.cpu.rename.RenamedOperands 26126 # Number of destination operands rename has renamed 248system.cpu.rename.RenameLookups 57405 # Number of register rename lookups that rename has made 249system.cpu.rename.int_rename_lookups 57389 # Number of integer rename lookups |
| 249system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups 250system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed | 250system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups 251system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed |
| 251system.cpu.rename.UndoneMaps 15733 # Number of HB maps that are undone due to squashing 252system.cpu.rename.serializingInsts 29 # count of serializing insts renamed 253system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed 254system.cpu.rename.skidInsts 2012 # count of insts added to the skid buffer 255system.cpu.memDep0.insertedLoads 2439 # Number of loads inserted to the mem dependence unit. 256system.cpu.memDep0.insertedStores 1809 # Number of stores inserted to the mem dependence unit. 257system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. 258system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. 259system.cpu.iq.iqInstsAdded 21719 # Number of instructions added to the IQ (excludes non-spec) 260system.cpu.iq.iqNonSpecInstsAdded 34 # Number of non-speculative instructions added to the IQ 261system.cpu.iq.iqInstsIssued 18260 # Number of instructions issued 262system.cpu.iq.iqSquashedInstsIssued 229 # Number of squashed instructions issued 263system.cpu.iq.iqSquashedInstsExamined 11155 # Number of squashed instructions iterated over during squash; mainly for profiling 264system.cpu.iq.iqSquashedOperandsExamined 15144 # Number of squashed operands that are examined and possibly removed from graph 265system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed 266system.cpu.iq.issued_per_cycle::samples 17196 # Number of insts issued each cycle 267system.cpu.iq.issued_per_cycle::mean 1.061875 # Number of insts issued each cycle 268system.cpu.iq.issued_per_cycle::stdev 1.899452 # Number of insts issued each cycle | 252system.cpu.rename.UndoneMaps 15066 # Number of HB maps that are undone due to squashing 253system.cpu.rename.serializingInsts 31 # count of serializing insts renamed 254system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed 255system.cpu.rename.skidInsts 2094 # count of insts added to the skid buffer 256system.cpu.memDep0.insertedLoads 2405 # Number of loads inserted to the mem dependence unit. 257system.cpu.memDep0.insertedStores 1772 # Number of stores inserted to the mem dependence unit. 258system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. 259system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. 260system.cpu.iq.iqInstsAdded 21302 # Number of instructions added to the IQ (excludes non-spec) 261system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ 262system.cpu.iq.iqInstsIssued 17998 # Number of instructions issued 263system.cpu.iq.iqSquashedInstsIssued 209 # Number of squashed instructions issued 264system.cpu.iq.iqSquashedInstsExamined 10762 # Number of squashed instructions iterated over during squash; mainly for profiling 265system.cpu.iq.iqSquashedOperandsExamined 14777 # Number of squashed operands that are examined and possibly removed from graph 266system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed 267system.cpu.iq.issued_per_cycle::samples 19065 # Number of insts issued each cycle 268system.cpu.iq.issued_per_cycle::mean 0.944034 # Number of insts issued each cycle 269system.cpu.iq.issued_per_cycle::stdev 1.806602 # Number of insts issued each cycle |
| 269system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 270system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 270system.cpu.iq.issued_per_cycle::0 11700 68.04% 68.04% # Number of insts issued each cycle 271system.cpu.iq.issued_per_cycle::1 1330 7.73% 75.77% # Number of insts issued each cycle 272system.cpu.iq.issued_per_cycle::2 1020 5.93% 81.71% # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::3 704 4.09% 85.80% # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::4 773 4.50% 90.29% # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::5 702 4.08% 94.38% # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::6 638 3.71% 98.09% # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::7 284 1.65% 99.74% # Number of insts issued each cycle 278system.cpu.iq.issued_per_cycle::8 45 0.26% 100.00% # Number of insts issued each cycle | 271system.cpu.iq.issued_per_cycle::0 13533 70.98% 70.98% # Number of insts issued each cycle 272system.cpu.iq.issued_per_cycle::1 1394 7.31% 78.30% # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::2 1058 5.55% 83.84% # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::3 719 3.77% 87.62% # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::4 757 3.97% 91.59% # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::5 676 3.55% 95.13% # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::6 613 3.22% 98.35% # Number of insts issued each cycle 278system.cpu.iq.issued_per_cycle::7 275 1.44% 99.79% # Number of insts issued each cycle 279system.cpu.iq.issued_per_cycle::8 40 0.21% 100.00% # Number of insts issued each cycle |
| 279system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 280system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 281system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 280system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 281system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 282system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 282system.cpu.iq.issued_per_cycle::total 17196 # Number of insts issued each cycle | 283system.cpu.iq.issued_per_cycle::total 19065 # Number of insts issued each cycle |
| 283system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 284system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 284system.cpu.iq.fu_full::IntAlu 154 78.97% 78.97% # attempts to use FU when none available 285system.cpu.iq.fu_full::IntMult 0 0.00% 78.97% # attempts to use FU when none available 286system.cpu.iq.fu_full::IntDiv 0 0.00% 78.97% # attempts to use FU when none available 287system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.97% # attempts to use FU when none available 288system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.97% # attempts to use FU when none available 289system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.97% # attempts to use FU when none available 290system.cpu.iq.fu_full::FloatMult 0 0.00% 78.97% # attempts to use FU when none available 291system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.97% # attempts to use FU when none available 292system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.97% # attempts to use FU when none available 293system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.97% # attempts to use FU when none available 294system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.97% # attempts to use FU when none available 295system.cpu.iq.fu_full::SimdAlu 0 0.00% 78.97% # attempts to use FU when none available 296system.cpu.iq.fu_full::SimdCmp 0 0.00% 78.97% # attempts to use FU when none available 297system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.97% # attempts to use FU when none available 298system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.97% # attempts to use FU when none available 299system.cpu.iq.fu_full::SimdMult 0 0.00% 78.97% # attempts to use FU when none available 300system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.97% # attempts to use FU when none available 301system.cpu.iq.fu_full::SimdShift 0 0.00% 78.97% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.97% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.97% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.97% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.97% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.97% # attempts to use FU when none available 307system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.97% # attempts to use FU when none available 308system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.97% # attempts to use FU when none available 309system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.97% # attempts to use FU when none available 310system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.97% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.97% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.97% # attempts to use FU when none available 313system.cpu.iq.fu_full::MemRead 22 11.28% 90.26% # attempts to use FU when none available 314system.cpu.iq.fu_full::MemWrite 19 9.74% 100.00% # attempts to use FU when none available | 285system.cpu.iq.fu_full::IntAlu 132 74.58% 74.58% # attempts to use FU when none available 286system.cpu.iq.fu_full::IntMult 0 0.00% 74.58% # attempts to use FU when none available 287system.cpu.iq.fu_full::IntDiv 0 0.00% 74.58% # attempts to use FU when none available 288system.cpu.iq.fu_full::FloatAdd 0 0.00% 74.58% # attempts to use FU when none available 289system.cpu.iq.fu_full::FloatCmp 0 0.00% 74.58% # attempts to use FU when none available 290system.cpu.iq.fu_full::FloatCvt 0 0.00% 74.58% # attempts to use FU when none available 291system.cpu.iq.fu_full::FloatMult 0 0.00% 74.58% # attempts to use FU when none available 292system.cpu.iq.fu_full::FloatDiv 0 0.00% 74.58% # attempts to use FU when none available 293system.cpu.iq.fu_full::FloatSqrt 0 0.00% 74.58% # attempts to use FU when none available 294system.cpu.iq.fu_full::SimdAdd 0 0.00% 74.58% # attempts to use FU when none available 295system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 74.58% # attempts to use FU when none available 296system.cpu.iq.fu_full::SimdAlu 0 0.00% 74.58% # attempts to use FU when none available 297system.cpu.iq.fu_full::SimdCmp 0 0.00% 74.58% # attempts to use FU when none available 298system.cpu.iq.fu_full::SimdCvt 0 0.00% 74.58% # attempts to use FU when none available 299system.cpu.iq.fu_full::SimdMisc 0 0.00% 74.58% # attempts to use FU when none available 300system.cpu.iq.fu_full::SimdMult 0 0.00% 74.58% # attempts to use FU when none available 301system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 74.58% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdShift 0 0.00% 74.58% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 74.58% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdSqrt 0 0.00% 74.58% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 74.58% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 74.58% # attempts to use FU when none available 307system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 74.58% # attempts to use FU when none available 308system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 74.58% # attempts to use FU when none available 309system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 74.58% # attempts to use FU when none available 310system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 74.58% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 74.58% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 74.58% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 74.58% # attempts to use FU when none available 314system.cpu.iq.fu_full::MemRead 23 12.99% 87.57% # attempts to use FU when none available 315system.cpu.iq.fu_full::MemWrite 22 12.43% 100.00% # attempts to use FU when none available |
| 315system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 316system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 316system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 317system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 317system.cpu.iq.FU_type_0::No_OpClass 5 0.03% 0.03% # Type of FU issued 318system.cpu.iq.FU_type_0::IntAlu 14636 80.15% 80.18% # Type of FU issued 319system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.18% # Type of FU issued 320system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.18% # Type of FU issued 321system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued 322system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued 323system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued 324system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued 325system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued 326system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued 327system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued 328system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued 329system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued 330system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued 331system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued 332system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued 333system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued 334system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued 340system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued 341system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued 342system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued 343system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued 344system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued 345system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued 346system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued 347system.cpu.iq.FU_type_0::MemRead 2090 11.45% 91.63% # Type of FU issued 348system.cpu.iq.FU_type_0::MemWrite 1529 8.37% 100.00% # Type of FU issued | 318system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued 319system.cpu.iq.FU_type_0::IntAlu 14399 80.00% 80.03% # Type of FU issued 320system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.03% # Type of FU issued 321system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.03% # Type of FU issued 322system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.03% # Type of FU issued 323system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.03% # Type of FU issued 324system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.03% # Type of FU issued 325system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.03% # Type of FU issued 326system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.03% # Type of FU issued 327system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.03% # Type of FU issued 328system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.03% # Type of FU issued 329system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.03% # Type of FU issued 330system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.03% # Type of FU issued 331system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.03% # Type of FU issued 332system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.03% # Type of FU issued 333system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.03% # Type of FU issued 334system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.03% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.03% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.03% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.03% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.03% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.03% # Type of FU issued 340system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.03% # Type of FU issued 341system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.03% # Type of FU issued 342system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.03% # Type of FU issued 343system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.03% # Type of FU issued 344system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.03% # Type of FU issued 345system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.03% # Type of FU issued 346system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.03% # Type of FU issued 347system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.03% # Type of FU issued 348system.cpu.iq.FU_type_0::MemRead 2084 11.58% 91.60% # Type of FU issued 349system.cpu.iq.FU_type_0::MemWrite 1511 8.40% 100.00% # Type of FU issued |
| 349system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 350system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 350system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 351system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 351system.cpu.iq.FU_type_0::total 18260 # Type of FU issued 352system.cpu.iq.rate 0.760231 # Inst issue rate 353system.cpu.iq.fu_busy_cnt 195 # FU busy when requested 354system.cpu.iq.fu_busy_rate 0.010679 # FU busy rate (busy events/executed inst) 355system.cpu.iq.int_inst_queue_reads 54132 # Number of integer instruction queue reads 356system.cpu.iq.int_inst_queue_writes 32913 # Number of integer instruction queue writes 357system.cpu.iq.int_inst_queue_wakeup_accesses 16722 # Number of integer instruction queue wakeup accesses | 352system.cpu.iq.FU_type_0::total 17998 # Type of FU issued 353system.cpu.iq.rate 0.590118 # Inst issue rate 354system.cpu.iq.fu_busy_cnt 177 # FU busy when requested 355system.cpu.iq.fu_busy_rate 0.009834 # FU busy rate (busy events/executed inst) 356system.cpu.iq.int_inst_queue_reads 55439 # Number of integer instruction queue reads 357system.cpu.iq.int_inst_queue_writes 32107 # Number of integer instruction queue writes 358system.cpu.iq.int_inst_queue_wakeup_accesses 16514 # Number of integer instruction queue wakeup accesses |
| 358system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 359system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 360system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses | 359system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 360system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 361system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses |
| 361system.cpu.iq.int_alu_accesses 18446 # Number of integer alu accesses | 362system.cpu.iq.int_alu_accesses 18167 # Number of integer alu accesses |
| 362system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses | 363system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses |
| 363system.cpu.iew.lsq.thread0.forwLoads 141 # Number of loads that had data forwarded from stores | 364system.cpu.iew.lsq.thread0.forwLoads 180 # Number of loads that had data forwarded from stores |
| 364system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 365system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 365system.cpu.iew.lsq.thread0.squashedLoads 1387 # Number of loads squashed 366system.cpu.iew.lsq.thread0.ignoredResponses 23 # Number of memory responses ignored because the instruction is squashed 367system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations 368system.cpu.iew.lsq.thread0.squashedStores 875 # Number of stores squashed | 366system.cpu.iew.lsq.thread0.squashedLoads 1353 # Number of loads squashed 367system.cpu.iew.lsq.thread0.ignoredResponses 24 # Number of memory responses ignored because the instruction is squashed 368system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations 369system.cpu.iew.lsq.thread0.squashedStores 838 # Number of stores squashed |
| 369system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 370system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 371system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled | 370system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 371system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 372system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled |
| 372system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked | 373system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked |
| 373system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 374system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 374system.cpu.iew.iewSquashCycles 1981 # Number of cycles IEW is squashing 375system.cpu.iew.iewBlockCycles 687 # Number of cycles IEW is blocking 376system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking 377system.cpu.iew.iewDispatchedInsts 21753 # Number of instructions dispatched to IQ 378system.cpu.iew.iewDispSquashedInsts 45 # Number of squashed instructions skipped by dispatch 379system.cpu.iew.iewDispLoadInsts 2439 # Number of dispatched load instructions 380system.cpu.iew.iewDispStoreInsts 1809 # Number of dispatched store instructions 381system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions | 375system.cpu.iew.iewSquashCycles 1953 # Number of cycles IEW is squashing 376system.cpu.iew.iewBlockCycles 1731 # Number of cycles IEW is blocking 377system.cpu.iew.iewUnblockCycles 30 # Number of cycles IEW is unblocking 378system.cpu.iew.iewDispatchedInsts 21339 # Number of instructions dispatched to IQ 379system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch 380system.cpu.iew.iewDispLoadInsts 2405 # Number of dispatched load instructions 381system.cpu.iew.iewDispStoreInsts 1772 # Number of dispatched store instructions 382system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions |
| 382system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 383system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 383system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 384system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
| 384system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations 385system.cpu.iew.predictedTakenIncorrect 71 # Number of branches that were predicted taken incorrectly | 385system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations 386system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly |
| 386system.cpu.iew.predictedNotTakenIncorrect 652 # Number of branches that were predicted not taken incorrectly | 387system.cpu.iew.predictedNotTakenIncorrect 652 # Number of branches that were predicted not taken incorrectly |
| 387system.cpu.iew.branchMispredicts 723 # Number of branch mispredicts detected at execute 388system.cpu.iew.iewExecutedInsts 17199 # Number of executed instructions 389system.cpu.iew.iewExecLoadInsts 1930 # Number of load instructions executed 390system.cpu.iew.iewExecSquashedInsts 1061 # Number of squashed instructions skipped in execute | 388system.cpu.iew.branchMispredicts 717 # Number of branch mispredicts detected at execute 389system.cpu.iew.iewExecutedInsts 17023 # Number of executed instructions 390system.cpu.iew.iewExecLoadInsts 1944 # Number of load instructions executed 391system.cpu.iew.iewExecSquashedInsts 975 # Number of squashed instructions skipped in execute |
| 391system.cpu.iew.exec_swp 0 # number of swp insts executed 392system.cpu.iew.exec_nop 0 # number of nop insts executed | 392system.cpu.iew.exec_swp 0 # number of swp insts executed 393system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 393system.cpu.iew.exec_refs 3340 # number of memory reference insts executed 394system.cpu.iew.exec_branches 1687 # Number of branches executed 395system.cpu.iew.exec_stores 1410 # Number of stores executed 396system.cpu.iew.exec_rate 0.716058 # Inst execution rate 397system.cpu.iew.wb_sent 16930 # cumulative count of insts sent to commit 398system.cpu.iew.wb_count 16726 # cumulative count of insts written-back 399system.cpu.iew.wb_producers 10734 # num instructions producing a value 400system.cpu.iew.wb_consumers 16630 # num instructions consuming a value | 394system.cpu.iew.exec_refs 3334 # number of memory reference insts executed 395system.cpu.iew.exec_branches 1674 # Number of branches executed 396system.cpu.iew.exec_stores 1390 # Number of stores executed 397system.cpu.iew.exec_rate 0.558149 # Inst execution rate 398system.cpu.iew.wb_sent 16747 # cumulative count of insts sent to commit 399system.cpu.iew.wb_count 16518 # cumulative count of insts written-back 400system.cpu.iew.wb_producers 10593 # num instructions producing a value 401system.cpu.iew.wb_consumers 16382 # num instructions consuming a value |
| 401system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 402system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 402system.cpu.iew.wb_rate 0.696365 # insts written-back per cycle 403system.cpu.iew.wb_fanout 0.645460 # average fanout of values written-back | 403system.cpu.iew.wb_rate 0.541592 # insts written-back per cycle 404system.cpu.iew.wb_fanout 0.646624 # average fanout of values written-back |
| 404system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 405system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 405system.cpu.commit.commitSquashedInsts 12007 # The number of squashed insts skipped by commit | 406system.cpu.commit.commitSquashedInsts 11593 # The number of squashed insts skipped by commit |
| 406system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards | 407system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards |
| 407system.cpu.commit.branchMispredicts 606 # The number of times a branch was mispredicted 408system.cpu.commit.committed_per_cycle::samples 15215 # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::mean 0.640486 # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::stdev 1.512697 # Number of insts commited each cycle | 408system.cpu.commit.branchMispredicts 604 # The number of times a branch was mispredicted 409system.cpu.commit.committed_per_cycle::samples 17112 # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::mean 0.569483 # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::stdev 1.430880 # Number of insts commited each cycle |
| 411system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 412system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 412system.cpu.commit.committed_per_cycle::0 11677 76.75% 76.75% # Number of insts commited each cycle 413system.cpu.commit.committed_per_cycle::1 1319 8.67% 85.42% # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::2 603 3.96% 89.38% # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::3 704 4.63% 94.01% # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::4 365 2.40% 96.40% # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::5 135 0.89% 97.29% # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::6 125 0.82% 98.11% # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::7 73 0.48% 98.59% # Number of insts commited each cycle 420system.cpu.commit.committed_per_cycle::8 214 1.41% 100.00% # Number of insts commited each cycle | 413system.cpu.commit.committed_per_cycle::0 13541 79.13% 79.13% # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::1 1338 7.82% 86.95% # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::2 619 3.62% 90.57% # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::3 703 4.11% 94.68% # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::4 373 2.18% 96.86% # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::5 140 0.82% 97.67% # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::6 121 0.71% 98.38% # Number of insts commited each cycle 420system.cpu.commit.committed_per_cycle::7 74 0.43% 98.81% # Number of insts commited each cycle 421system.cpu.commit.committed_per_cycle::8 203 1.19% 100.00% # Number of insts commited each cycle |
| 421system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 422system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 423system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 422system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 423system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 424system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 424system.cpu.commit.committed_per_cycle::total 15215 # Number of insts commited each cycle | 425system.cpu.commit.committed_per_cycle::total 17112 # Number of insts commited each cycle |
| 425system.cpu.commit.committedInsts 5380 # Number of instructions committed 426system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed 427system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 428system.cpu.commit.refs 1986 # Number of memory references committed 429system.cpu.commit.loads 1052 # Number of loads committed 430system.cpu.commit.membars 0 # Number of memory barriers committed 431system.cpu.commit.branches 1208 # Number of branches committed 432system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 433system.cpu.commit.int_insts 9650 # Number of committed integer instructions. 434system.cpu.commit.function_calls 0 # Number of function calls committed. | 426system.cpu.commit.committedInsts 5380 # Number of instructions committed 427system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed 428system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 429system.cpu.commit.refs 1986 # Number of memory references committed 430system.cpu.commit.loads 1052 # Number of loads committed 431system.cpu.commit.membars 0 # Number of memory barriers committed 432system.cpu.commit.branches 1208 # Number of branches committed 433system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 434system.cpu.commit.int_insts 9650 # Number of committed integer instructions. 435system.cpu.commit.function_calls 0 # Number of function calls committed. |
| 435system.cpu.commit.bw_lim_events 214 # number cycles where commit BW limit reached | 436system.cpu.commit.bw_lim_events 203 # number cycles where commit BW limit reached |
| 436system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 437system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 437system.cpu.rob.rob_reads 36753 # The number of ROB reads 438system.cpu.rob.rob_writes 45519 # The number of ROB writes 439system.cpu.timesIdled 141 # Number of times that the entire CPU went into an idle state and unscheduled itself 440system.cpu.idleCycles 6823 # Total number of cycles that the CPU has spent unscheduled due to idling | 438system.cpu.rob.rob_reads 38247 # The number of ROB reads 439system.cpu.rob.rob_writes 44659 # The number of ROB writes 440system.cpu.timesIdled 152 # Number of times that the entire CPU went into an idle state and unscheduled itself 441system.cpu.idleCycles 11434 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 441system.cpu.committedInsts 5380 # Number of Instructions Simulated 442system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated 443system.cpu.committedInsts_total 5380 # Number of Instructions Simulated | 442system.cpu.committedInsts 5380 # Number of Instructions Simulated 443system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated 444system.cpu.committedInsts_total 5380 # Number of Instructions Simulated |
| 444system.cpu.cpi 4.464498 # CPI: Cycles Per Instruction 445system.cpu.cpi_total 4.464498 # CPI: Total CPI of All Threads 446system.cpu.ipc 0.223989 # IPC: Instructions Per Cycle 447system.cpu.ipc_total 0.223989 # IPC: Total IPC of All Threads 448system.cpu.int_regfile_reads 30259 # number of integer regfile reads 449system.cpu.int_regfile_writes 18088 # number of integer regfile writes | 445system.cpu.cpi 5.668959 # CPI: Cycles Per Instruction 446system.cpu.cpi_total 5.668959 # CPI: Total CPI of All Threads 447system.cpu.ipc 0.176399 # IPC: Instructions Per Cycle 448system.cpu.ipc_total 0.176399 # IPC: Total IPC of All Threads 449system.cpu.int_regfile_reads 29908 # number of integer regfile reads 450system.cpu.int_regfile_writes 17845 # number of integer regfile writes |
| 450system.cpu.fp_regfile_reads 4 # number of floating regfile reads | 451system.cpu.fp_regfile_reads 4 # number of floating regfile reads |
| 451system.cpu.misc_regfile_reads 7500 # number of misc regfile reads | 452system.cpu.misc_regfile_reads 7467 # number of misc regfile reads |
| 452system.cpu.icache.replacements 0 # number of replacements | 453system.cpu.icache.replacements 0 # number of replacements |
| 453system.cpu.icache.tagsinuse 149.891095 # Cycle average of tags in use 454system.cpu.icache.total_refs 1605 # Total number of references to valid blocks. 455system.cpu.icache.sampled_refs 305 # Sample count of references to valid blocks. 456system.cpu.icache.avg_refs 5.262295 # Average number of references to valid blocks. | 454system.cpu.icache.tagsinuse 145.993781 # Cycle average of tags in use 455system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. 456system.cpu.icache.sampled_refs 306 # Sample count of references to valid blocks. 457system.cpu.icache.avg_refs 5.117647 # Average number of references to valid blocks. |
| 457system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 458system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 458system.cpu.icache.occ_blocks::cpu.inst 149.891095 # Average occupied blocks per requestor 459system.cpu.icache.occ_percent::cpu.inst 0.073189 # Average percentage of cache occupancy 460system.cpu.icache.occ_percent::total 0.073189 # Average percentage of cache occupancy 461system.cpu.icache.ReadReq_hits::cpu.inst 1605 # number of ReadReq hits 462system.cpu.icache.ReadReq_hits::total 1605 # number of ReadReq hits 463system.cpu.icache.demand_hits::cpu.inst 1605 # number of demand (read+write) hits 464system.cpu.icache.demand_hits::total 1605 # number of demand (read+write) hits 465system.cpu.icache.overall_hits::cpu.inst 1605 # number of overall hits 466system.cpu.icache.overall_hits::total 1605 # number of overall hits 467system.cpu.icache.ReadReq_misses::cpu.inst 394 # number of ReadReq misses 468system.cpu.icache.ReadReq_misses::total 394 # number of ReadReq misses 469system.cpu.icache.demand_misses::cpu.inst 394 # number of demand (read+write) misses 470system.cpu.icache.demand_misses::total 394 # number of demand (read+write) misses 471system.cpu.icache.overall_misses::cpu.inst 394 # number of overall misses 472system.cpu.icache.overall_misses::total 394 # number of overall misses 473system.cpu.icache.ReadReq_miss_latency::cpu.inst 13338000 # number of ReadReq miss cycles 474system.cpu.icache.ReadReq_miss_latency::total 13338000 # number of ReadReq miss cycles 475system.cpu.icache.demand_miss_latency::cpu.inst 13338000 # number of demand (read+write) miss cycles 476system.cpu.icache.demand_miss_latency::total 13338000 # number of demand (read+write) miss cycles 477system.cpu.icache.overall_miss_latency::cpu.inst 13338000 # number of overall miss cycles 478system.cpu.icache.overall_miss_latency::total 13338000 # number of overall miss cycles 479system.cpu.icache.ReadReq_accesses::cpu.inst 1999 # number of ReadReq accesses(hits+misses) 480system.cpu.icache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses) 481system.cpu.icache.demand_accesses::cpu.inst 1999 # number of demand (read+write) accesses 482system.cpu.icache.demand_accesses::total 1999 # number of demand (read+write) accesses 483system.cpu.icache.overall_accesses::cpu.inst 1999 # number of overall (read+write) accesses 484system.cpu.icache.overall_accesses::total 1999 # number of overall (read+write) accesses 485system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197099 # miss rate for ReadReq accesses 486system.cpu.icache.ReadReq_miss_rate::total 0.197099 # miss rate for ReadReq accesses 487system.cpu.icache.demand_miss_rate::cpu.inst 0.197099 # miss rate for demand accesses 488system.cpu.icache.demand_miss_rate::total 0.197099 # miss rate for demand accesses 489system.cpu.icache.overall_miss_rate::cpu.inst 0.197099 # miss rate for overall accesses 490system.cpu.icache.overall_miss_rate::total 0.197099 # miss rate for overall accesses 491system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33852.791878 # average ReadReq miss latency 492system.cpu.icache.ReadReq_avg_miss_latency::total 33852.791878 # average ReadReq miss latency 493system.cpu.icache.demand_avg_miss_latency::cpu.inst 33852.791878 # average overall miss latency 494system.cpu.icache.demand_avg_miss_latency::total 33852.791878 # average overall miss latency 495system.cpu.icache.overall_avg_miss_latency::cpu.inst 33852.791878 # average overall miss latency 496system.cpu.icache.overall_avg_miss_latency::total 33852.791878 # average overall miss latency 497system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 459system.cpu.icache.occ_blocks::cpu.inst 145.993781 # Average occupied blocks per requestor 460system.cpu.icache.occ_percent::cpu.inst 0.071286 # Average percentage of cache occupancy 461system.cpu.icache.occ_percent::total 0.071286 # Average percentage of cache occupancy 462system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits 463system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits 464system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits 465system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits 466system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits 467system.cpu.icache.overall_hits::total 1566 # number of overall hits 468system.cpu.icache.ReadReq_misses::cpu.inst 406 # number of ReadReq misses 469system.cpu.icache.ReadReq_misses::total 406 # number of ReadReq misses 470system.cpu.icache.demand_misses::cpu.inst 406 # number of demand (read+write) misses 471system.cpu.icache.demand_misses::total 406 # number of demand (read+write) misses 472system.cpu.icache.overall_misses::cpu.inst 406 # number of overall misses 473system.cpu.icache.overall_misses::total 406 # number of overall misses 474system.cpu.icache.ReadReq_miss_latency::cpu.inst 19356000 # number of ReadReq miss cycles 475system.cpu.icache.ReadReq_miss_latency::total 19356000 # number of ReadReq miss cycles 476system.cpu.icache.demand_miss_latency::cpu.inst 19356000 # number of demand (read+write) miss cycles 477system.cpu.icache.demand_miss_latency::total 19356000 # number of demand (read+write) miss cycles 478system.cpu.icache.overall_miss_latency::cpu.inst 19356000 # number of overall miss cycles 479system.cpu.icache.overall_miss_latency::total 19356000 # number of overall miss cycles 480system.cpu.icache.ReadReq_accesses::cpu.inst 1972 # number of ReadReq accesses(hits+misses) 481system.cpu.icache.ReadReq_accesses::total 1972 # number of ReadReq accesses(hits+misses) 482system.cpu.icache.demand_accesses::cpu.inst 1972 # number of demand (read+write) accesses 483system.cpu.icache.demand_accesses::total 1972 # number of demand (read+write) accesses 484system.cpu.icache.overall_accesses::cpu.inst 1972 # number of overall (read+write) accesses 485system.cpu.icache.overall_accesses::total 1972 # number of overall (read+write) accesses 486system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.205882 # miss rate for ReadReq accesses 487system.cpu.icache.ReadReq_miss_rate::total 0.205882 # miss rate for ReadReq accesses 488system.cpu.icache.demand_miss_rate::cpu.inst 0.205882 # miss rate for demand accesses 489system.cpu.icache.demand_miss_rate::total 0.205882 # miss rate for demand accesses 490system.cpu.icache.overall_miss_rate::cpu.inst 0.205882 # miss rate for overall accesses 491system.cpu.icache.overall_miss_rate::total 0.205882 # miss rate for overall accesses 492system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47674.876847 # average ReadReq miss latency 493system.cpu.icache.ReadReq_avg_miss_latency::total 47674.876847 # average ReadReq miss latency 494system.cpu.icache.demand_avg_miss_latency::cpu.inst 47674.876847 # average overall miss latency 495system.cpu.icache.demand_avg_miss_latency::total 47674.876847 # average overall miss latency 496system.cpu.icache.overall_avg_miss_latency::cpu.inst 47674.876847 # average overall miss latency 497system.cpu.icache.overall_avg_miss_latency::total 47674.876847 # average overall miss latency 498system.cpu.icache.blocked_cycles::no_mshrs 302 # number of cycles access was blocked |
| 498system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 499system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 499system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked | 500system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked |
| 500system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 501system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 501system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 502system.cpu.icache.avg_blocked_cycles::no_mshrs 43.142857 # average number of cycles each access was blocked |
| 502system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 503system.cpu.icache.fast_writes 0 # number of fast writes performed 504system.cpu.icache.cache_copies 0 # number of cache copies performed | 503system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 504system.cpu.icache.fast_writes 0 # number of fast writes performed 505system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 505system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits 506system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits 507system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits 508system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits 509system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits 510system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits | 506system.cpu.icache.ReadReq_mshr_hits::cpu.inst 100 # number of ReadReq MSHR hits 507system.cpu.icache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits 508system.cpu.icache.demand_mshr_hits::cpu.inst 100 # number of demand (read+write) MSHR hits 509system.cpu.icache.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits 510system.cpu.icache.overall_mshr_hits::cpu.inst 100 # number of overall MSHR hits 511system.cpu.icache.overall_mshr_hits::total 100 # number of overall MSHR hits |
| 511system.cpu.icache.ReadReq_mshr_misses::cpu.inst 306 # number of ReadReq MSHR misses 512system.cpu.icache.ReadReq_mshr_misses::total 306 # number of ReadReq MSHR misses 513system.cpu.icache.demand_mshr_misses::cpu.inst 306 # number of demand (read+write) MSHR misses 514system.cpu.icache.demand_mshr_misses::total 306 # number of demand (read+write) MSHR misses 515system.cpu.icache.overall_mshr_misses::cpu.inst 306 # number of overall MSHR misses 516system.cpu.icache.overall_mshr_misses::total 306 # number of overall MSHR misses | 512system.cpu.icache.ReadReq_mshr_misses::cpu.inst 306 # number of ReadReq MSHR misses 513system.cpu.icache.ReadReq_mshr_misses::total 306 # number of ReadReq MSHR misses 514system.cpu.icache.demand_mshr_misses::cpu.inst 306 # number of demand (read+write) MSHR misses 515system.cpu.icache.demand_mshr_misses::total 306 # number of demand (read+write) MSHR misses 516system.cpu.icache.overall_mshr_misses::cpu.inst 306 # number of overall MSHR misses 517system.cpu.icache.overall_mshr_misses::total 306 # number of overall MSHR misses |
| 517system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10626000 # number of ReadReq MSHR miss cycles 518system.cpu.icache.ReadReq_mshr_miss_latency::total 10626000 # number of ReadReq MSHR miss cycles 519system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10626000 # number of demand (read+write) MSHR miss cycles 520system.cpu.icache.demand_mshr_miss_latency::total 10626000 # number of demand (read+write) MSHR miss cycles 521system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10626000 # number of overall MSHR miss cycles 522system.cpu.icache.overall_mshr_miss_latency::total 10626000 # number of overall MSHR miss cycles 523system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for ReadReq accesses 524system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153077 # mshr miss rate for ReadReq accesses 525system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for demand accesses 526system.cpu.icache.demand_mshr_miss_rate::total 0.153077 # mshr miss rate for demand accesses 527system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for overall accesses 528system.cpu.icache.overall_mshr_miss_rate::total 0.153077 # mshr miss rate for overall accesses 529system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34725.490196 # average ReadReq mshr miss latency 530system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34725.490196 # average ReadReq mshr miss latency 531system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34725.490196 # average overall mshr miss latency 532system.cpu.icache.demand_avg_mshr_miss_latency::total 34725.490196 # average overall mshr miss latency 533system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34725.490196 # average overall mshr miss latency 534system.cpu.icache.overall_avg_mshr_miss_latency::total 34725.490196 # average overall mshr miss latency | 518system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15469000 # number of ReadReq MSHR miss cycles 519system.cpu.icache.ReadReq_mshr_miss_latency::total 15469000 # number of ReadReq MSHR miss cycles 520system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15469000 # number of demand (read+write) MSHR miss cycles 521system.cpu.icache.demand_mshr_miss_latency::total 15469000 # number of demand (read+write) MSHR miss cycles 522system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15469000 # number of overall MSHR miss cycles 523system.cpu.icache.overall_mshr_miss_latency::total 15469000 # number of overall MSHR miss cycles 524system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155172 # mshr miss rate for ReadReq accesses 525system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155172 # mshr miss rate for ReadReq accesses 526system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155172 # mshr miss rate for demand accesses 527system.cpu.icache.demand_mshr_miss_rate::total 0.155172 # mshr miss rate for demand accesses 528system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155172 # mshr miss rate for overall accesses 529system.cpu.icache.overall_mshr_miss_rate::total 0.155172 # mshr miss rate for overall accesses 530system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50552.287582 # average ReadReq mshr miss latency 531system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50552.287582 # average ReadReq mshr miss latency 532system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50552.287582 # average overall mshr miss latency 533system.cpu.icache.demand_avg_mshr_miss_latency::total 50552.287582 # average overall mshr miss latency 534system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50552.287582 # average overall mshr miss latency 535system.cpu.icache.overall_avg_mshr_miss_latency::total 50552.287582 # average overall mshr miss latency |
| 535system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 536system.cpu.dcache.replacements 0 # number of replacements | 536system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 537system.cpu.dcache.replacements 0 # number of replacements |
| 537system.cpu.dcache.tagsinuse 84.879845 # Cycle average of tags in use 538system.cpu.dcache.total_refs 2447 # Total number of references to valid blocks. 539system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. 540system.cpu.dcache.avg_refs 16.875862 # Average number of references to valid blocks. | 538system.cpu.dcache.tagsinuse 83.489938 # Cycle average of tags in use 539system.cpu.dcache.total_refs 2406 # Total number of references to valid blocks. 540system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. 541system.cpu.dcache.avg_refs 16.825175 # Average number of references to valid blocks. |
| 541system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 542system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 542system.cpu.dcache.occ_blocks::cpu.data 84.879845 # Average occupied blocks per requestor 543system.cpu.dcache.occ_percent::cpu.data 0.020723 # Average percentage of cache occupancy 544system.cpu.dcache.occ_percent::total 0.020723 # Average percentage of cache occupancy 545system.cpu.dcache.ReadReq_hits::cpu.data 1589 # number of ReadReq hits 546system.cpu.dcache.ReadReq_hits::total 1589 # number of ReadReq hits | 543system.cpu.dcache.occ_blocks::cpu.data 83.489938 # Average occupied blocks per requestor 544system.cpu.dcache.occ_percent::cpu.data 0.020383 # Average percentage of cache occupancy 545system.cpu.dcache.occ_percent::total 0.020383 # Average percentage of cache occupancy 546system.cpu.dcache.ReadReq_hits::cpu.data 1548 # number of ReadReq hits 547system.cpu.dcache.ReadReq_hits::total 1548 # number of ReadReq hits |
| 547system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits 548system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits | 548system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits 549system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits |
| 549system.cpu.dcache.demand_hits::cpu.data 2447 # number of demand (read+write) hits 550system.cpu.dcache.demand_hits::total 2447 # number of demand (read+write) hits 551system.cpu.dcache.overall_hits::cpu.data 2447 # number of overall hits 552system.cpu.dcache.overall_hits::total 2447 # number of overall hits | 550system.cpu.dcache.demand_hits::cpu.data 2406 # number of demand (read+write) hits 551system.cpu.dcache.demand_hits::total 2406 # number of demand (read+write) hits 552system.cpu.dcache.overall_hits::cpu.data 2406 # number of overall hits 553system.cpu.dcache.overall_hits::total 2406 # number of overall hits |
| 553system.cpu.dcache.ReadReq_misses::cpu.data 132 # number of ReadReq misses 554system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses 555system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses 556system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses 557system.cpu.dcache.demand_misses::cpu.data 208 # number of demand (read+write) misses 558system.cpu.dcache.demand_misses::total 208 # number of demand (read+write) misses 559system.cpu.dcache.overall_misses::cpu.data 208 # number of overall misses 560system.cpu.dcache.overall_misses::total 208 # number of overall misses | 554system.cpu.dcache.ReadReq_misses::cpu.data 132 # number of ReadReq misses 555system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses 556system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses 557system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses 558system.cpu.dcache.demand_misses::cpu.data 208 # number of demand (read+write) misses 559system.cpu.dcache.demand_misses::total 208 # number of demand (read+write) misses 560system.cpu.dcache.overall_misses::cpu.data 208 # number of overall misses 561system.cpu.dcache.overall_misses::total 208 # number of overall misses |
| 561system.cpu.dcache.ReadReq_miss_latency::cpu.data 5132000 # number of ReadReq miss cycles 562system.cpu.dcache.ReadReq_miss_latency::total 5132000 # number of ReadReq miss cycles 563system.cpu.dcache.WriteReq_miss_latency::cpu.data 3133000 # number of WriteReq miss cycles 564system.cpu.dcache.WriteReq_miss_latency::total 3133000 # number of WriteReq miss cycles 565system.cpu.dcache.demand_miss_latency::cpu.data 8265000 # number of demand (read+write) miss cycles 566system.cpu.dcache.demand_miss_latency::total 8265000 # number of demand (read+write) miss cycles 567system.cpu.dcache.overall_miss_latency::cpu.data 8265000 # number of overall miss cycles 568system.cpu.dcache.overall_miss_latency::total 8265000 # number of overall miss cycles 569system.cpu.dcache.ReadReq_accesses::cpu.data 1721 # number of ReadReq accesses(hits+misses) 570system.cpu.dcache.ReadReq_accesses::total 1721 # number of ReadReq accesses(hits+misses) | 562system.cpu.dcache.ReadReq_miss_latency::cpu.data 6548500 # number of ReadReq miss cycles 563system.cpu.dcache.ReadReq_miss_latency::total 6548500 # number of ReadReq miss cycles 564system.cpu.dcache.WriteReq_miss_latency::cpu.data 4231000 # number of WriteReq miss cycles 565system.cpu.dcache.WriteReq_miss_latency::total 4231000 # number of WriteReq miss cycles 566system.cpu.dcache.demand_miss_latency::cpu.data 10779500 # number of demand (read+write) miss cycles 567system.cpu.dcache.demand_miss_latency::total 10779500 # number of demand (read+write) miss cycles 568system.cpu.dcache.overall_miss_latency::cpu.data 10779500 # number of overall miss cycles 569system.cpu.dcache.overall_miss_latency::total 10779500 # number of overall miss cycles 570system.cpu.dcache.ReadReq_accesses::cpu.data 1680 # number of ReadReq accesses(hits+misses) 571system.cpu.dcache.ReadReq_accesses::total 1680 # number of ReadReq accesses(hits+misses) |
| 571system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) 572system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) | 572system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) 573system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) |
| 573system.cpu.dcache.demand_accesses::cpu.data 2655 # number of demand (read+write) accesses 574system.cpu.dcache.demand_accesses::total 2655 # number of demand (read+write) accesses 575system.cpu.dcache.overall_accesses::cpu.data 2655 # number of overall (read+write) accesses 576system.cpu.dcache.overall_accesses::total 2655 # number of overall (read+write) accesses 577system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076700 # miss rate for ReadReq accesses 578system.cpu.dcache.ReadReq_miss_rate::total 0.076700 # miss rate for ReadReq accesses | 574system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses 575system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses 576system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses 577system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses 578system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078571 # miss rate for ReadReq accesses 579system.cpu.dcache.ReadReq_miss_rate::total 0.078571 # miss rate for ReadReq accesses |
| 579system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses 580system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses | 580system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses 581system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses |
| 581system.cpu.dcache.demand_miss_rate::cpu.data 0.078343 # miss rate for demand accesses 582system.cpu.dcache.demand_miss_rate::total 0.078343 # miss rate for demand accesses 583system.cpu.dcache.overall_miss_rate::cpu.data 0.078343 # miss rate for overall accesses 584system.cpu.dcache.overall_miss_rate::total 0.078343 # miss rate for overall accesses 585system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38878.787879 # average ReadReq miss latency 586system.cpu.dcache.ReadReq_avg_miss_latency::total 38878.787879 # average ReadReq miss latency 587system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41223.684211 # average WriteReq miss latency 588system.cpu.dcache.WriteReq_avg_miss_latency::total 41223.684211 # average WriteReq miss latency 589system.cpu.dcache.demand_avg_miss_latency::cpu.data 39735.576923 # average overall miss latency 590system.cpu.dcache.demand_avg_miss_latency::total 39735.576923 # average overall miss latency 591system.cpu.dcache.overall_avg_miss_latency::cpu.data 39735.576923 # average overall miss latency 592system.cpu.dcache.overall_avg_miss_latency::total 39735.576923 # average overall miss latency 593system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 582system.cpu.dcache.demand_miss_rate::cpu.data 0.079572 # miss rate for demand accesses 583system.cpu.dcache.demand_miss_rate::total 0.079572 # miss rate for demand accesses 584system.cpu.dcache.overall_miss_rate::cpu.data 0.079572 # miss rate for overall accesses 585system.cpu.dcache.overall_miss_rate::total 0.079572 # miss rate for overall accesses 586system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49609.848485 # average ReadReq miss latency 587system.cpu.dcache.ReadReq_avg_miss_latency::total 49609.848485 # average ReadReq miss latency 588system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55671.052632 # average WriteReq miss latency 589system.cpu.dcache.WriteReq_avg_miss_latency::total 55671.052632 # average WriteReq miss latency 590system.cpu.dcache.demand_avg_miss_latency::cpu.data 51824.519231 # average overall miss latency 591system.cpu.dcache.demand_avg_miss_latency::total 51824.519231 # average overall miss latency 592system.cpu.dcache.overall_avg_miss_latency::cpu.data 51824.519231 # average overall miss latency 593system.cpu.dcache.overall_avg_miss_latency::total 51824.519231 # average overall miss latency 594system.cpu.dcache.blocked_cycles::no_mshrs 108 # number of cycles access was blocked |
| 594system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 595system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 595system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked | 596system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked |
| 596system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 597system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 597system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 598system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.600000 # average number of cycles each access was blocked |
| 598system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 599system.cpu.dcache.fast_writes 0 # number of fast writes performed 600system.cpu.dcache.cache_copies 0 # number of cache copies performed 601system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits 602system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits 603system.cpu.dcache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits 604system.cpu.dcache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits 605system.cpu.dcache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits 606system.cpu.dcache.overall_mshr_hits::total 62 # number of overall MSHR hits 607system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses 608system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses 609system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses 610system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses 611system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses 612system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses 613system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses 614system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses | 599system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 600system.cpu.dcache.fast_writes 0 # number of fast writes performed 601system.cpu.dcache.cache_copies 0 # number of cache copies performed 602system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits 603system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits 604system.cpu.dcache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits 605system.cpu.dcache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits 606system.cpu.dcache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits 607system.cpu.dcache.overall_mshr_hits::total 62 # number of overall MSHR hits 608system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses 609system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses 610system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses 611system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses 612system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses 613system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses 614system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses 615system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses |
| 615system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3278500 # number of ReadReq MSHR miss cycles 616system.cpu.dcache.ReadReq_mshr_miss_latency::total 3278500 # number of ReadReq MSHR miss cycles 617system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2981000 # number of WriteReq MSHR miss cycles 618system.cpu.dcache.WriteReq_mshr_miss_latency::total 2981000 # number of WriteReq MSHR miss cycles 619system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6259500 # number of demand (read+write) MSHR miss cycles 620system.cpu.dcache.demand_mshr_miss_latency::total 6259500 # number of demand (read+write) MSHR miss cycles 621system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6259500 # number of overall MSHR miss cycles 622system.cpu.dcache.overall_mshr_miss_latency::total 6259500 # number of overall MSHR miss cycles 623system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040674 # mshr miss rate for ReadReq accesses 624system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040674 # mshr miss rate for ReadReq accesses | 616system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3696500 # number of ReadReq MSHR miss cycles 617system.cpu.dcache.ReadReq_mshr_miss_latency::total 3696500 # number of ReadReq MSHR miss cycles 618system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4079000 # number of WriteReq MSHR miss cycles 619system.cpu.dcache.WriteReq_mshr_miss_latency::total 4079000 # number of WriteReq MSHR miss cycles 620system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7775500 # number of demand (read+write) MSHR miss cycles 621system.cpu.dcache.demand_mshr_miss_latency::total 7775500 # number of demand (read+write) MSHR miss cycles 622system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7775500 # number of overall MSHR miss cycles 623system.cpu.dcache.overall_mshr_miss_latency::total 7775500 # number of overall MSHR miss cycles 624system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for ReadReq accesses 625system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041667 # mshr miss rate for ReadReq accesses |
| 625system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses 626system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses | 626system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses 627system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses |
| 627system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for demand accesses 628system.cpu.dcache.demand_mshr_miss_rate::total 0.054991 # mshr miss rate for demand accesses 629system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for overall accesses 630system.cpu.dcache.overall_mshr_miss_rate::total 0.054991 # mshr miss rate for overall accesses 631system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46835.714286 # average ReadReq mshr miss latency 632system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46835.714286 # average ReadReq mshr miss latency 633system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39223.684211 # average WriteReq mshr miss latency 634system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39223.684211 # average WriteReq mshr miss latency 635system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42873.287671 # average overall mshr miss latency 636system.cpu.dcache.demand_avg_mshr_miss_latency::total 42873.287671 # average overall mshr miss latency 637system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42873.287671 # average overall mshr miss latency 638system.cpu.dcache.overall_avg_mshr_miss_latency::total 42873.287671 # average overall mshr miss latency | 628system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055853 # mshr miss rate for demand accesses 629system.cpu.dcache.demand_mshr_miss_rate::total 0.055853 # mshr miss rate for demand accesses 630system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055853 # mshr miss rate for overall accesses 631system.cpu.dcache.overall_mshr_miss_rate::total 0.055853 # mshr miss rate for overall accesses 632system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52807.142857 # average ReadReq mshr miss latency 633system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52807.142857 # average ReadReq mshr miss latency 634system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53671.052632 # average WriteReq mshr miss latency 635system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53671.052632 # average WriteReq mshr miss latency 636system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53256.849315 # average overall mshr miss latency 637system.cpu.dcache.demand_avg_mshr_miss_latency::total 53256.849315 # average overall mshr miss latency 638system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53256.849315 # average overall mshr miss latency 639system.cpu.dcache.overall_avg_mshr_miss_latency::total 53256.849315 # average overall mshr miss latency |
| 639system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 640system.cpu.l2cache.replacements 0 # number of replacements | 640system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 641system.cpu.l2cache.replacements 0 # number of replacements |
| 641system.cpu.l2cache.tagsinuse 182.959089 # Cycle average of tags in use | 642system.cpu.l2cache.tagsinuse 179.176449 # Cycle average of tags in use |
| 642system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. | 643system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. |
| 643system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. 644system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. | 644system.cpu.l2cache.sampled_refs 374 # Sample count of references to valid blocks. 645system.cpu.l2cache.avg_refs 0.002674 # Average number of references to valid blocks. |
| 645system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 646system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 646system.cpu.l2cache.occ_blocks::cpu.inst 149.880234 # Average occupied blocks per requestor 647system.cpu.l2cache.occ_blocks::cpu.data 33.078855 # Average occupied blocks per requestor 648system.cpu.l2cache.occ_percent::cpu.inst 0.004574 # Average percentage of cache occupancy 649system.cpu.l2cache.occ_percent::cpu.data 0.001009 # Average percentage of cache occupancy 650system.cpu.l2cache.occ_percent::total 0.005583 # Average percentage of cache occupancy | 647system.cpu.l2cache.occ_blocks::cpu.inst 146.139957 # Average occupied blocks per requestor 648system.cpu.l2cache.occ_blocks::cpu.data 33.036492 # Average occupied blocks per requestor 649system.cpu.l2cache.occ_percent::cpu.inst 0.004460 # Average percentage of cache occupancy 650system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy 651system.cpu.l2cache.occ_percent::total 0.005468 # Average percentage of cache occupancy |
| 651system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 652system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 653system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 654system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 655system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 656system.cpu.l2cache.overall_hits::total 1 # number of overall hits 657system.cpu.l2cache.ReadReq_misses::cpu.inst 305 # number of ReadReq misses 658system.cpu.l2cache.ReadReq_misses::cpu.data 70 # number of ReadReq misses 659system.cpu.l2cache.ReadReq_misses::total 375 # number of ReadReq misses 660system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses 661system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses 662system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses 663system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses 664system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses 665system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses 666system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses 667system.cpu.l2cache.overall_misses::total 451 # number of overall misses | 652system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 653system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 654system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 655system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 656system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 657system.cpu.l2cache.overall_hits::total 1 # number of overall hits 658system.cpu.l2cache.ReadReq_misses::cpu.inst 305 # number of ReadReq misses 659system.cpu.l2cache.ReadReq_misses::cpu.data 70 # number of ReadReq misses 660system.cpu.l2cache.ReadReq_misses::total 375 # number of ReadReq misses 661system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses 662system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses 663system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses 664system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses 665system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses 666system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses 667system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses 668system.cpu.l2cache.overall_misses::total 451 # number of overall misses |
| 668system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10319000 # number of ReadReq miss cycles 669system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3209500 # number of ReadReq miss cycles 670system.cpu.l2cache.ReadReq_miss_latency::total 13528500 # number of ReadReq miss cycles 671system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2905000 # number of ReadExReq miss cycles 672system.cpu.l2cache.ReadExReq_miss_latency::total 2905000 # number of ReadExReq miss cycles 673system.cpu.l2cache.demand_miss_latency::cpu.inst 10319000 # number of demand (read+write) miss cycles 674system.cpu.l2cache.demand_miss_latency::cpu.data 6114500 # number of demand (read+write) miss cycles 675system.cpu.l2cache.demand_miss_latency::total 16433500 # number of demand (read+write) miss cycles 676system.cpu.l2cache.overall_miss_latency::cpu.inst 10319000 # number of overall miss cycles 677system.cpu.l2cache.overall_miss_latency::cpu.data 6114500 # number of overall miss cycles 678system.cpu.l2cache.overall_miss_latency::total 16433500 # number of overall miss cycles | 669system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15152000 # number of ReadReq miss cycles 670system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3773500 # number of ReadReq miss cycles 671system.cpu.l2cache.ReadReq_miss_latency::total 18925500 # number of ReadReq miss cycles 672system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4003000 # number of ReadExReq miss cycles 673system.cpu.l2cache.ReadExReq_miss_latency::total 4003000 # number of ReadExReq miss cycles 674system.cpu.l2cache.demand_miss_latency::cpu.inst 15152000 # number of demand (read+write) miss cycles 675system.cpu.l2cache.demand_miss_latency::cpu.data 7776500 # number of demand (read+write) miss cycles 676system.cpu.l2cache.demand_miss_latency::total 22928500 # number of demand (read+write) miss cycles 677system.cpu.l2cache.overall_miss_latency::cpu.inst 15152000 # number of overall miss cycles 678system.cpu.l2cache.overall_miss_latency::cpu.data 7776500 # number of overall miss cycles 679system.cpu.l2cache.overall_miss_latency::total 22928500 # number of overall miss cycles |
| 679system.cpu.l2cache.ReadReq_accesses::cpu.inst 306 # number of ReadReq accesses(hits+misses) 680system.cpu.l2cache.ReadReq_accesses::cpu.data 70 # number of ReadReq accesses(hits+misses) 681system.cpu.l2cache.ReadReq_accesses::total 376 # number of ReadReq accesses(hits+misses) 682system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) 683system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) 684system.cpu.l2cache.demand_accesses::cpu.inst 306 # number of demand (read+write) accesses 685system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses 686system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 693system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 694system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 695system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996732 # miss rate for demand accesses 696system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 697system.cpu.l2cache.demand_miss_rate::total 0.997788 # miss rate for demand accesses 698system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996732 # miss rate for overall accesses 699system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 700system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses | 680system.cpu.l2cache.ReadReq_accesses::cpu.inst 306 # number of ReadReq accesses(hits+misses) 681system.cpu.l2cache.ReadReq_accesses::cpu.data 70 # number of ReadReq accesses(hits+misses) 682system.cpu.l2cache.ReadReq_accesses::total 376 # number of ReadReq accesses(hits+misses) 683system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) 684system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) 685system.cpu.l2cache.demand_accesses::cpu.inst 306 # number of demand (read+write) accesses 686system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses 687system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 694system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 695system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 696system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996732 # miss rate for demand accesses 697system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 698system.cpu.l2cache.demand_miss_rate::total 0.997788 # miss rate for demand accesses 699system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996732 # miss rate for overall accesses 700system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 701system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses |
| 701system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 33832.786885 # average ReadReq miss latency 702system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45850 # average ReadReq miss latency 703system.cpu.l2cache.ReadReq_avg_miss_latency::total 36076 # average ReadReq miss latency 704system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38223.684211 # average ReadExReq miss latency 705system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38223.684211 # average ReadExReq miss latency 706system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 33832.786885 # average overall miss latency 707system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41880.136986 # average overall miss latency 708system.cpu.l2cache.demand_avg_miss_latency::total 36437.915743 # average overall miss latency 709system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 33832.786885 # average overall miss latency 710system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41880.136986 # average overall miss latency 711system.cpu.l2cache.overall_avg_miss_latency::total 36437.915743 # average overall miss latency | 702system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49678.688525 # average ReadReq miss latency 703system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53907.142857 # average ReadReq miss latency 704system.cpu.l2cache.ReadReq_avg_miss_latency::total 50468 # average ReadReq miss latency 705system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52671.052632 # average ReadExReq miss latency 706system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52671.052632 # average ReadExReq miss latency 707system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49678.688525 # average overall miss latency 708system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53263.698630 # average overall miss latency 709system.cpu.l2cache.demand_avg_miss_latency::total 50839.246120 # average overall miss latency 710system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49678.688525 # average overall miss latency 711system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53263.698630 # average overall miss latency 712system.cpu.l2cache.overall_avg_miss_latency::total 50839.246120 # average overall miss latency |
| 712system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 713system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 714system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 715system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 716system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 717system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 718system.cpu.l2cache.fast_writes 0 # number of fast writes performed 719system.cpu.l2cache.cache_copies 0 # number of cache copies performed 720system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 305 # number of ReadReq MSHR misses 721system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses 722system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses 723system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses 724system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses 725system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses 726system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses 727system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses 728system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses 729system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses 730system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses | 713system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 714system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 715system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 716system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 717system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 718system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 719system.cpu.l2cache.fast_writes 0 # number of fast writes performed 720system.cpu.l2cache.cache_copies 0 # number of cache copies performed 721system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 305 # number of ReadReq MSHR misses 722system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses 723system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses 724system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses 725system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses 726system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses 727system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses 728system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses 729system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses 730system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses 731system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses |
| 731system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9239430 # number of ReadReq MSHR miss cycles 732system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2977566 # number of ReadReq MSHR miss cycles 733system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12216996 # number of ReadReq MSHR miss cycles 734system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2628106 # number of ReadExReq MSHR miss cycles 735system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2628106 # number of ReadExReq MSHR miss cycles 736system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9239430 # number of demand (read+write) MSHR miss cycles 737system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5605672 # number of demand (read+write) MSHR miss cycles 738system.cpu.l2cache.demand_mshr_miss_latency::total 14845102 # number of demand (read+write) MSHR miss cycles 739system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9239430 # number of overall MSHR miss cycles 740system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5605672 # number of overall MSHR miss cycles 741system.cpu.l2cache.overall_mshr_miss_latency::total 14845102 # number of overall MSHR miss cycles | 732system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11317954 # number of ReadReq MSHR miss cycles 733system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2918074 # number of ReadReq MSHR miss cycles 734system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14236028 # number of ReadReq MSHR miss cycles 735system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3040610 # number of ReadExReq MSHR miss cycles 736system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3040610 # number of ReadExReq MSHR miss cycles 737system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11317954 # number of demand (read+write) MSHR miss cycles 738system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5958684 # number of demand (read+write) MSHR miss cycles 739system.cpu.l2cache.demand_mshr_miss_latency::total 17276638 # number of demand (read+write) MSHR miss cycles 740system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11317954 # number of overall MSHR miss cycles 741system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5958684 # number of overall MSHR miss cycles 742system.cpu.l2cache.overall_mshr_miss_latency::total 17276638 # number of overall MSHR miss cycles |
| 742system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for ReadReq accesses 743system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 744system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses 745system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 746system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 747system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for demand accesses 748system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 749system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 # mshr miss rate for demand accesses 750system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for overall accesses 751system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 752system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses | 743system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for ReadReq accesses 744system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 745system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses 746system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 747system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 748system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for demand accesses 749system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 750system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 # mshr miss rate for demand accesses 751system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for overall accesses 752system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 753system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses |
| 753system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30293.213115 # average ReadReq mshr miss latency 754system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42536.657143 # average ReadReq mshr miss latency 755system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32578.656000 # average ReadReq mshr miss latency 756system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34580.342105 # average ReadExReq mshr miss latency 757system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34580.342105 # average ReadExReq mshr miss latency 758system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30293.213115 # average overall mshr miss latency 759system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38395.013699 # average overall mshr miss latency 760system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32915.968958 # average overall mshr miss latency 761system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30293.213115 # average overall mshr miss latency 762system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38395.013699 # average overall mshr miss latency 763system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32915.968958 # average overall mshr miss latency | 754system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37108.045902 # average ReadReq mshr miss latency 755system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41686.771429 # average ReadReq mshr miss latency 756system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37962.741333 # average ReadReq mshr miss latency 757system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40008.026316 # average ReadExReq mshr miss latency 758system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40008.026316 # average ReadExReq mshr miss latency 759system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37108.045902 # average overall mshr miss latency 760system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40812.904110 # average overall mshr miss latency 761system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38307.401330 # average overall mshr miss latency 762system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37108.045902 # average overall mshr miss latency 763system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40812.904110 # average overall mshr miss latency 764system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38307.401330 # average overall mshr miss latency |
| 764system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 765 766---------- End Simulation Statistics ---------- | 765system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 766 767---------- End Simulation Statistics ---------- |