1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000012 # Number of seconds simulated
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000012 # Number of seconds simulated
|
4sim_ticks 12215000 # Number of ticks simulated
5final_tick 12215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 4sim_ticks 12009000 # Number of ticks simulated
5final_tick 12009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 33465 # Simulator instruction rate (inst/s)
8host_op_rate 60609 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 75963972 # Simulator tick rate (ticks/s)
10host_mem_usage 227744 # Number of bytes of host memory used
11host_seconds 0.16 # Real time elapsed on the host
| 7host_inst_rate 10920 # Simulator instruction rate (inst/s)
8host_op_rate 19780 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 24373770 # Simulator tick rate (ticks/s)
10host_mem_usage 225464 # Number of bytes of host memory used
11host_seconds 0.49 # Real time elapsed on the host
|
12sim_insts 5380 # Number of instructions simulated
13sim_ops 9745 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
| 12sim_insts 5380 # Number of instructions simulated
13sim_ops 9745 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
|
15system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory
16system.physmem.bytes_read::total 28928 # Number of bytes read from this memory
| 15system.physmem.bytes_read::cpu.data 9280 # Number of bytes read from this memory
16system.physmem.bytes_read::total 28800 # Number of bytes read from this memory
|
17system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
| 17system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
|
20system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 452 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1598035203 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 770200573 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 2368235776 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1598035203 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1598035203 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1598035203 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 770200573 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 2368235776 # Total bandwidth to/from this memory (bytes/s)
| 20system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 450 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1625447581 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 772753768 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 2398201349 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1625447581 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1625447581 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1625447581 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 772753768 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 2398201349 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 451 # Total number of read requests seen
31system.physmem.writeReqs 0 # Total number of write requests seen
32system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady
33system.physmem.bytesRead 28800 # Total number of bytes read from memory
34system.physmem.bytesWritten 0 # Total number of bytes written to memory
35system.physmem.bytesConsumedRd 28800 # bytesRead derated as per pkt->getSize()
36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
39system.physmem.perBankRdReqs::0 40 # Track reads on a per bank basis
40system.physmem.perBankRdReqs::1 20 # Track reads on a per bank basis
41system.physmem.perBankRdReqs::2 55 # Track reads on a per bank basis
42system.physmem.perBankRdReqs::3 23 # Track reads on a per bank basis
43system.physmem.perBankRdReqs::4 52 # Track reads on a per bank basis
44system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis
45system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis
46system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::11 40 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::12 13 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis
55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
73system.physmem.totGap 11990500 # Total gap between requests
74system.physmem.readPktSize::0 0 # Categorize read packet sizes
75system.physmem.readPktSize::1 0 # Categorize read packet sizes
76system.physmem.readPktSize::2 0 # Categorize read packet sizes
77system.physmem.readPktSize::3 0 # Categorize read packet sizes
78system.physmem.readPktSize::4 0 # Categorize read packet sizes
79system.physmem.readPktSize::5 0 # Categorize read packet sizes
80system.physmem.readPktSize::6 451 # Categorize read packet sizes
81system.physmem.readPktSize::7 0 # Categorize read packet sizes
82system.physmem.readPktSize::8 0 # Categorize read packet sizes
83system.physmem.writePktSize::0 0 # categorize write packet sizes
84system.physmem.writePktSize::1 0 # categorize write packet sizes
85system.physmem.writePktSize::2 0 # categorize write packet sizes
86system.physmem.writePktSize::3 0 # categorize write packet sizes
87system.physmem.writePktSize::4 0 # categorize write packet sizes
88system.physmem.writePktSize::5 0 # categorize write packet sizes
89system.physmem.writePktSize::6 0 # categorize write packet sizes
90system.physmem.writePktSize::7 0 # categorize write packet sizes
91system.physmem.writePktSize::8 0 # categorize write packet sizes
92system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
101system.physmem.rdQLenPdf::0 221 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
134system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
167system.physmem.totQLat 3096951 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 13440951 # Sum of mem lat for all requests
169system.physmem.totBusLat 1804000 # Total cycles spent in databus access
170system.physmem.totBankLat 8540000 # Total cycles spent in bank access
171system.physmem.avgQLat 6866.85 # Average queueing delay per request
172system.physmem.avgBankLat 18935.70 # Average bank access latency per request
173system.physmem.avgBusLat 4000.00 # Average bus latency per request
174system.physmem.avgMemAccLat 29802.55 # Average memory access latency
175system.physmem.avgRdBW 2398.20 # Average achieved read bandwidth in MB/s
176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
177system.physmem.avgConsumedRdBW 2398.20 # Average consumed read bandwidth in MB/s
178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
180system.physmem.busUtil 14.99 # Data bus utilization in percentage
181system.physmem.avgRdQLen 1.12 # Average read queue length over time
182system.physmem.avgWrQLen 0.00 # Average write queue length over time
183system.physmem.readRowHits 353 # Number of row buffer hits during reads
184system.physmem.writeRowHits 0 # Number of row buffer hits during writes
185system.physmem.readRowHitRate 78.27 # Row buffer hit rate for reads
186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
187system.physmem.avgGap 26586.47 # Average gap between requests
|
30system.cpu.workload.num_syscalls 11 # Number of system calls
| 188system.cpu.workload.num_syscalls 11 # Number of system calls
|
31system.cpu.numCycles 24431 # number of cpu cycles simulated
| 189system.cpu.numCycles 24019 # number of cpu cycles simulated
|
32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
| 190system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
191system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
34system.cpu.BPredUnit.lookups 3187 # Number of BP lookups
35system.cpu.BPredUnit.condPredicted 3187 # Number of conditional branches predicted
36system.cpu.BPredUnit.condIncorrect 588 # Number of conditional branches incorrect
37system.cpu.BPredUnit.BTBLookups 2597 # Number of BTB lookups
38system.cpu.BPredUnit.BTBHits 772 # Number of BTB hits
| 192system.cpu.BPredUnit.lookups 3185 # Number of BP lookups
193system.cpu.BPredUnit.condPredicted 3185 # Number of conditional branches predicted
194system.cpu.BPredUnit.condIncorrect 589 # Number of conditional branches incorrect
195system.cpu.BPredUnit.BTBLookups 2591 # Number of BTB lookups
196system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits
|
39system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
40system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
41system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
| 197system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
198system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
199system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
42system.cpu.fetch.icacheStallCycles 7858 # Number of cycles fetch is stalled on an Icache miss
43system.cpu.fetch.Insts 15336 # Number of instructions fetch has processed
44system.cpu.fetch.Branches 3187 # Number of branches that fetch encountered
45system.cpu.fetch.predictedBranches 772 # Number of branches that fetch has predicted taken
46system.cpu.fetch.Cycles 4160 # Number of cycles fetch has run and was not squashing or blocked
47system.cpu.fetch.SquashCycles 2551 # Number of cycles fetch has spent squashing
48system.cpu.fetch.BlockedCycles 3088 # Number of cycles fetch has spent blocked
49system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
50system.cpu.fetch.PendingTrapStallCycles 59 # Number of stall cycles due to pending traps
51system.cpu.fetch.CacheLines 1994 # Number of cache lines fetched
52system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed
53system.cpu.fetch.rateDist::samples 17124 # Number of instructions fetched each cycle (Total)
54system.cpu.fetch.rateDist::mean 1.595013 # Number of instructions fetched each cycle (Total)
55system.cpu.fetch.rateDist::stdev 3.047737 # Number of instructions fetched each cycle (Total)
| 200system.cpu.fetch.icacheStallCycles 8560 # Number of cycles fetch is stalled on an Icache miss
201system.cpu.fetch.Insts 15317 # Number of instructions fetch has processed
202system.cpu.fetch.Branches 3185 # Number of branches that fetch encountered
203system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken
204system.cpu.fetch.Cycles 4169 # Number of cycles fetch has run and was not squashing or blocked
205system.cpu.fetch.SquashCycles 2596 # Number of cycles fetch has spent squashing
206system.cpu.fetch.BlockedCycles 2320 # Number of cycles fetch has spent blocked
207system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
208system.cpu.fetch.PendingTrapStallCycles 142 # Number of stall cycles due to pending traps
209system.cpu.fetch.CacheLines 1999 # Number of cache lines fetched
210system.cpu.fetch.IcacheSquashes 297 # Number of outstanding Icache misses that were squashed
211system.cpu.fetch.rateDist::samples 17196 # Number of instructions fetched each cycle (Total)
212system.cpu.fetch.rateDist::mean 1.587346 # Number of instructions fetched each cycle (Total)
213system.cpu.fetch.rateDist::stdev 3.039622 # Number of instructions fetched each cycle (Total)
|
56system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
| 214system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
57system.cpu.fetch.rateDist::0 13067 76.31% 76.31% # Number of instructions fetched each cycle (Total)
58system.cpu.fetch.rateDist::1 184 1.07% 77.38% # Number of instructions fetched each cycle (Total)
59system.cpu.fetch.rateDist::2 158 0.92% 78.31% # Number of instructions fetched each cycle (Total)
60system.cpu.fetch.rateDist::3 198 1.16% 79.46% # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::4 177 1.03% 80.50% # Number of instructions fetched each cycle (Total)
62system.cpu.fetch.rateDist::5 181 1.06% 81.55% # Number of instructions fetched each cycle (Total)
63system.cpu.fetch.rateDist::6 237 1.38% 82.94% # Number of instructions fetched each cycle (Total)
64system.cpu.fetch.rateDist::7 192 1.12% 84.06% # Number of instructions fetched each cycle (Total)
65system.cpu.fetch.rateDist::8 2730 15.94% 100.00% # Number of instructions fetched each cycle (Total)
| 215system.cpu.fetch.rateDist::0 13133 76.37% 76.37% # Number of instructions fetched each cycle (Total)
216system.cpu.fetch.rateDist::1 180 1.05% 77.42% # Number of instructions fetched each cycle (Total)
217system.cpu.fetch.rateDist::2 163 0.95% 78.37% # Number of instructions fetched each cycle (Total)
218system.cpu.fetch.rateDist::3 205 1.19% 79.56% # Number of instructions fetched each cycle (Total)
219system.cpu.fetch.rateDist::4 179 1.04% 80.60% # Number of instructions fetched each cycle (Total)
220system.cpu.fetch.rateDist::5 184 1.07% 81.67% # Number of instructions fetched each cycle (Total)
221system.cpu.fetch.rateDist::6 242 1.41% 83.08% # Number of instructions fetched each cycle (Total)
222system.cpu.fetch.rateDist::7 193 1.12% 84.20% # Number of instructions fetched each cycle (Total)
223system.cpu.fetch.rateDist::8 2717 15.80% 100.00% # Number of instructions fetched each cycle (Total)
|
66system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
67system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
68system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
| 224system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
225system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
226system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
69system.cpu.fetch.rateDist::total 17124 # Number of instructions fetched each cycle (Total)
70system.cpu.fetch.branchRate 0.130449 # Number of branch fetches per cycle
71system.cpu.fetch.rate 0.627727 # Number of inst fetches per cycle
72system.cpu.decode.IdleCycles 8263 # Number of cycles decode is idle
73system.cpu.decode.BlockedCycles 3049 # Number of cycles decode is blocked
74system.cpu.decode.RunCycles 3749 # Number of cycles decode is running
75system.cpu.decode.UnblockCycles 116 # Number of cycles decode is unblocking
76system.cpu.decode.SquashCycles 1947 # Number of cycles decode is squashing
77system.cpu.decode.DecodedInsts 26028 # Number of instructions handled by decode
78system.cpu.rename.SquashCycles 1947 # Number of cycles rename is squashing
79system.cpu.rename.IdleCycles 8634 # Number of cycles rename is idle
80system.cpu.rename.BlockCycles 1940 # Number of cycles rename is blocking
81system.cpu.rename.serializeStallCycles 422 # count of cycles rename stalled for serializing inst
82system.cpu.rename.RunCycles 3487 # Number of cycles rename is running
83system.cpu.rename.UnblockCycles 694 # Number of cycles rename is unblocking
84system.cpu.rename.RenamedInsts 24257 # Number of instructions processed by rename
85system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
86system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full
87system.cpu.rename.LSQFullEvents 601 # Number of times rename has blocked due to LSQ full
88system.cpu.rename.RenamedOperands 26511 # Number of destination operands rename has renamed
89system.cpu.rename.RenameLookups 58176 # Number of register rename lookups that rename has made
90system.cpu.rename.int_rename_lookups 58160 # Number of integer rename lookups
| 227system.cpu.fetch.rateDist::total 17196 # Number of instructions fetched each cycle (Total)
228system.cpu.fetch.branchRate 0.132603 # Number of branch fetches per cycle
229system.cpu.fetch.rate 0.637703 # Number of inst fetches per cycle
230system.cpu.decode.IdleCycles 9044 # Number of cycles decode is idle
231system.cpu.decode.BlockedCycles 2277 # Number of cycles decode is blocked
232system.cpu.decode.RunCycles 3768 # Number of cycles decode is running
233system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking
234system.cpu.decode.SquashCycles 1981 # Number of cycles decode is squashing
235system.cpu.decode.DecodedInsts 26083 # Number of instructions handled by decode
236system.cpu.rename.SquashCycles 1981 # Number of cycles rename is squashing
237system.cpu.rename.IdleCycles 9405 # Number of cycles rename is idle
238system.cpu.rename.BlockCycles 1279 # Number of cycles rename is blocking
239system.cpu.rename.serializeStallCycles 293 # count of cycles rename stalled for serializing inst
240system.cpu.rename.RunCycles 3524 # Number of cycles rename is running
241system.cpu.rename.UnblockCycles 714 # Number of cycles rename is unblocking
242system.cpu.rename.RenamedInsts 24459 # Number of instructions processed by rename
243system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
244system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full
245system.cpu.rename.LSQFullEvents 613 # Number of times rename has blocked due to LSQ full
246system.cpu.rename.RenamedOperands 26793 # Number of destination operands rename has renamed
247system.cpu.rename.RenameLookups 58583 # Number of register rename lookups that rename has made
248system.cpu.rename.int_rename_lookups 58567 # Number of integer rename lookups
|
91system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
92system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed
| 249system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
250system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed
|
93system.cpu.rename.UndoneMaps 15451 # Number of HB maps that are undone due to squashing
94system.cpu.rename.serializingInsts 33 # count of serializing insts renamed
95system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed
96system.cpu.rename.skidInsts 1918 # count of insts added to the skid buffer
97system.cpu.memDep0.insertedLoads 2379 # Number of loads inserted to the mem dependence unit.
98system.cpu.memDep0.insertedStores 1816 # Number of stores inserted to the mem dependence unit.
99system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads.
100system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
101system.cpu.iq.iqInstsAdded 21504 # Number of instructions added to the IQ (excludes non-spec)
102system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ
103system.cpu.iq.iqInstsIssued 18146 # Number of instructions issued
104system.cpu.iq.iqSquashedInstsIssued 221 # Number of squashed instructions issued
105system.cpu.iq.iqSquashedInstsExamined 10979 # Number of squashed instructions iterated over during squash; mainly for profiling
106system.cpu.iq.iqSquashedOperandsExamined 14783 # Number of squashed operands that are examined and possibly removed from graph
107system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
108system.cpu.iq.issued_per_cycle::samples 17124 # Number of insts issued each cycle
109system.cpu.iq.issued_per_cycle::mean 1.059682 # Number of insts issued each cycle
110system.cpu.iq.issued_per_cycle::stdev 1.899800 # Number of insts issued each cycle
| 251system.cpu.rename.UndoneMaps 15733 # Number of HB maps that are undone due to squashing
252system.cpu.rename.serializingInsts 29 # count of serializing insts renamed
253system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed
254system.cpu.rename.skidInsts 2012 # count of insts added to the skid buffer
255system.cpu.memDep0.insertedLoads 2439 # Number of loads inserted to the mem dependence unit.
256system.cpu.memDep0.insertedStores 1809 # Number of stores inserted to the mem dependence unit.
257system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads.
258system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
259system.cpu.iq.iqInstsAdded 21719 # Number of instructions added to the IQ (excludes non-spec)
260system.cpu.iq.iqNonSpecInstsAdded 34 # Number of non-speculative instructions added to the IQ
261system.cpu.iq.iqInstsIssued 18260 # Number of instructions issued
262system.cpu.iq.iqSquashedInstsIssued 229 # Number of squashed instructions issued
263system.cpu.iq.iqSquashedInstsExamined 11155 # Number of squashed instructions iterated over during squash; mainly for profiling
264system.cpu.iq.iqSquashedOperandsExamined 15144 # Number of squashed operands that are examined and possibly removed from graph
265system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed
266system.cpu.iq.issued_per_cycle::samples 17196 # Number of insts issued each cycle
267system.cpu.iq.issued_per_cycle::mean 1.061875 # Number of insts issued each cycle
268system.cpu.iq.issued_per_cycle::stdev 1.899452 # Number of insts issued each cycle
|
111system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
| 269system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
112system.cpu.iq.issued_per_cycle::0 11674 68.17% 68.17% # Number of insts issued each cycle
113system.cpu.iq.issued_per_cycle::1 1321 7.71% 75.89% # Number of insts issued each cycle
114system.cpu.iq.issued_per_cycle::2 996 5.82% 81.70% # Number of insts issued each cycle
115system.cpu.iq.issued_per_cycle::3 705 4.12% 85.82% # Number of insts issued each cycle
116system.cpu.iq.issued_per_cycle::4 752 4.39% 90.21% # Number of insts issued each cycle
117system.cpu.iq.issued_per_cycle::5 712 4.16% 94.37% # Number of insts issued each cycle
118system.cpu.iq.issued_per_cycle::6 641 3.74% 98.11% # Number of insts issued each cycle
119system.cpu.iq.issued_per_cycle::7 280 1.64% 99.75% # Number of insts issued each cycle
120system.cpu.iq.issued_per_cycle::8 43 0.25% 100.00% # Number of insts issued each cycle
| 270system.cpu.iq.issued_per_cycle::0 11700 68.04% 68.04% # Number of insts issued each cycle
271system.cpu.iq.issued_per_cycle::1 1330 7.73% 75.77% # Number of insts issued each cycle
272system.cpu.iq.issued_per_cycle::2 1020 5.93% 81.71% # Number of insts issued each cycle
273system.cpu.iq.issued_per_cycle::3 704 4.09% 85.80% # Number of insts issued each cycle
274system.cpu.iq.issued_per_cycle::4 773 4.50% 90.29% # Number of insts issued each cycle
275system.cpu.iq.issued_per_cycle::5 702 4.08% 94.38% # Number of insts issued each cycle
276system.cpu.iq.issued_per_cycle::6 638 3.71% 98.09% # Number of insts issued each cycle
277system.cpu.iq.issued_per_cycle::7 284 1.65% 99.74% # Number of insts issued each cycle
278system.cpu.iq.issued_per_cycle::8 45 0.26% 100.00% # Number of insts issued each cycle
|
121system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
122system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
123system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
| 279system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
280system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
281system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
124system.cpu.iq.issued_per_cycle::total 17124 # Number of insts issued each cycle
| 282system.cpu.iq.issued_per_cycle::total 17196 # Number of insts issued each cycle
|
125system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
| 283system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
126system.cpu.iq.fu_full::IntAlu 166 80.19% 80.19% # attempts to use FU when none available
127system.cpu.iq.fu_full::IntMult 0 0.00% 80.19% # attempts to use FU when none available
128system.cpu.iq.fu_full::IntDiv 0 0.00% 80.19% # attempts to use FU when none available
129system.cpu.iq.fu_full::FloatAdd 0 0.00% 80.19% # attempts to use FU when none available
130system.cpu.iq.fu_full::FloatCmp 0 0.00% 80.19% # attempts to use FU when none available
131system.cpu.iq.fu_full::FloatCvt 0 0.00% 80.19% # attempts to use FU when none available
132system.cpu.iq.fu_full::FloatMult 0 0.00% 80.19% # attempts to use FU when none available
133system.cpu.iq.fu_full::FloatDiv 0 0.00% 80.19% # attempts to use FU when none available
134system.cpu.iq.fu_full::FloatSqrt 0 0.00% 80.19% # attempts to use FU when none available
135system.cpu.iq.fu_full::SimdAdd 0 0.00% 80.19% # attempts to use FU when none available
136system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 80.19% # attempts to use FU when none available
137system.cpu.iq.fu_full::SimdAlu 0 0.00% 80.19% # attempts to use FU when none available
138system.cpu.iq.fu_full::SimdCmp 0 0.00% 80.19% # attempts to use FU when none available
139system.cpu.iq.fu_full::SimdCvt 0 0.00% 80.19% # attempts to use FU when none available
140system.cpu.iq.fu_full::SimdMisc 0 0.00% 80.19% # attempts to use FU when none available
141system.cpu.iq.fu_full::SimdMult 0 0.00% 80.19% # attempts to use FU when none available
142system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 80.19% # attempts to use FU when none available
143system.cpu.iq.fu_full::SimdShift 0 0.00% 80.19% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 80.19% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdSqrt 0 0.00% 80.19% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 80.19% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 80.19% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 80.19% # attempts to use FU when none available
149system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 80.19% # attempts to use FU when none available
150system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 80.19% # attempts to use FU when none available
151system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 80.19% # attempts to use FU when none available
152system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 80.19% # attempts to use FU when none available
153system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 80.19% # attempts to use FU when none available
154system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 80.19% # attempts to use FU when none available
155system.cpu.iq.fu_full::MemRead 21 10.14% 90.34% # attempts to use FU when none available
156system.cpu.iq.fu_full::MemWrite 20 9.66% 100.00% # attempts to use FU when none available
| 284system.cpu.iq.fu_full::IntAlu 154 78.97% 78.97% # attempts to use FU when none available
285system.cpu.iq.fu_full::IntMult 0 0.00% 78.97% # attempts to use FU when none available
286system.cpu.iq.fu_full::IntDiv 0 0.00% 78.97% # attempts to use FU when none available
287system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.97% # attempts to use FU when none available
288system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.97% # attempts to use FU when none available
289system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.97% # attempts to use FU when none available
290system.cpu.iq.fu_full::FloatMult 0 0.00% 78.97% # attempts to use FU when none available
291system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.97% # attempts to use FU when none available
292system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.97% # attempts to use FU when none available
293system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.97% # attempts to use FU when none available
294system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.97% # attempts to use FU when none available
295system.cpu.iq.fu_full::SimdAlu 0 0.00% 78.97% # attempts to use FU when none available
296system.cpu.iq.fu_full::SimdCmp 0 0.00% 78.97% # attempts to use FU when none available
297system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.97% # attempts to use FU when none available
298system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.97% # attempts to use FU when none available
299system.cpu.iq.fu_full::SimdMult 0 0.00% 78.97% # attempts to use FU when none available
300system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.97% # attempts to use FU when none available
301system.cpu.iq.fu_full::SimdShift 0 0.00% 78.97% # attempts to use FU when none available
302system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.97% # attempts to use FU when none available
303system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.97% # attempts to use FU when none available
304system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.97% # attempts to use FU when none available
305system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.97% # attempts to use FU when none available
306system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.97% # attempts to use FU when none available
307system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.97% # attempts to use FU when none available
308system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.97% # attempts to use FU when none available
309system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.97% # attempts to use FU when none available
310system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.97% # attempts to use FU when none available
311system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.97% # attempts to use FU when none available
312system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.97% # attempts to use FU when none available
313system.cpu.iq.fu_full::MemRead 22 11.28% 90.26% # attempts to use FU when none available
314system.cpu.iq.fu_full::MemWrite 19 9.74% 100.00% # attempts to use FU when none available
|
157system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
158system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
| 315system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
316system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
159system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
160system.cpu.iq.FU_type_0::IntAlu 14557 80.22% 80.24% # Type of FU issued
161system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.24% # Type of FU issued
162system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.24% # Type of FU issued
163system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.24% # Type of FU issued
164system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.24% # Type of FU issued
165system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.24% # Type of FU issued
166system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.24% # Type of FU issued
167system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.24% # Type of FU issued
168system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.24% # Type of FU issued
169system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.24% # Type of FU issued
170system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.24% # Type of FU issued
171system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.24% # Type of FU issued
172system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.24% # Type of FU issued
173system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.24% # Type of FU issued
174system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.24% # Type of FU issued
175system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.24% # Type of FU issued
176system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.24% # Type of FU issued
177system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.24% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.24% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.24% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.24% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.24% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.24% # Type of FU issued
183system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.24% # Type of FU issued
184system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.24% # Type of FU issued
185system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.24% # Type of FU issued
186system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.24% # Type of FU issued
187system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.24% # Type of FU issued
188system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.24% # Type of FU issued
189system.cpu.iq.FU_type_0::MemRead 2050 11.30% 91.54% # Type of FU issued
190system.cpu.iq.FU_type_0::MemWrite 1535 8.46% 100.00% # Type of FU issued
| 317system.cpu.iq.FU_type_0::No_OpClass 5 0.03% 0.03% # Type of FU issued
318system.cpu.iq.FU_type_0::IntAlu 14636 80.15% 80.18% # Type of FU issued
319system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.18% # Type of FU issued
320system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.18% # Type of FU issued
321system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued
322system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued
323system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued
324system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued
325system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued
326system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued
327system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued
328system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued
329system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued
330system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued
331system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued
332system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued
333system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued
334system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued
335system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued
336system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued
337system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued
338system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued
339system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued
340system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued
341system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued
342system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued
343system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued
344system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued
345system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued
346system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued
347system.cpu.iq.FU_type_0::MemRead 2090 11.45% 91.63% # Type of FU issued
348system.cpu.iq.FU_type_0::MemWrite 1529 8.37% 100.00% # Type of FU issued
|
191system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
192system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
| 349system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
350system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
193system.cpu.iq.FU_type_0::total 18146 # Type of FU issued
194system.cpu.iq.rate 0.742745 # Inst issue rate
195system.cpu.iq.fu_busy_cnt 207 # FU busy when requested
196system.cpu.iq.fu_busy_rate 0.011407 # FU busy rate (busy events/executed inst)
197system.cpu.iq.int_inst_queue_reads 53836 # Number of integer instruction queue reads
198system.cpu.iq.int_inst_queue_writes 32525 # Number of integer instruction queue writes
199system.cpu.iq.int_inst_queue_wakeup_accesses 16639 # Number of integer instruction queue wakeup accesses
| 351system.cpu.iq.FU_type_0::total 18260 # Type of FU issued
352system.cpu.iq.rate 0.760231 # Inst issue rate
353system.cpu.iq.fu_busy_cnt 195 # FU busy when requested
354system.cpu.iq.fu_busy_rate 0.010679 # FU busy rate (busy events/executed inst)
355system.cpu.iq.int_inst_queue_reads 54132 # Number of integer instruction queue reads
356system.cpu.iq.int_inst_queue_writes 32913 # Number of integer instruction queue writes
357system.cpu.iq.int_inst_queue_wakeup_accesses 16722 # Number of integer instruction queue wakeup accesses
|
200system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
201system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
202system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
| 358system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
359system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
360system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
|
203system.cpu.iq.int_alu_accesses 18345 # Number of integer alu accesses
| 361system.cpu.iq.int_alu_accesses 18446 # Number of integer alu accesses
|
204system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
| 362system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
|
205system.cpu.iew.lsq.thread0.forwLoads 130 # Number of loads that had data forwarded from stores
| 363system.cpu.iew.lsq.thread0.forwLoads 141 # Number of loads that had data forwarded from stores
|
206system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
| 364system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
207system.cpu.iew.lsq.thread0.squashedLoads 1327 # Number of loads squashed
208system.cpu.iew.lsq.thread0.ignoredResponses 21 # Number of memory responses ignored because the instruction is squashed
| 365system.cpu.iew.lsq.thread0.squashedLoads 1387 # Number of loads squashed
366system.cpu.iew.lsq.thread0.ignoredResponses 23 # Number of memory responses ignored because the instruction is squashed
|
209system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations
| 367system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations
|
210system.cpu.iew.lsq.thread0.squashedStores 882 # Number of stores squashed
| 368system.cpu.iew.lsq.thread0.squashedStores 875 # Number of stores squashed
|
211system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
212system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
213system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
214system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
215system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
| 369system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
370system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
371system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
372system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
373system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
216system.cpu.iew.iewSquashCycles 1947 # Number of cycles IEW is squashing
217system.cpu.iew.iewBlockCycles 1327 # Number of cycles IEW is blocking
| 374system.cpu.iew.iewSquashCycles 1981 # Number of cycles IEW is squashing
375system.cpu.iew.iewBlockCycles 687 # Number of cycles IEW is blocking
|
218system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking
| 376system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking
|
219system.cpu.iew.iewDispatchedInsts 21541 # Number of instructions dispatched to IQ
220system.cpu.iew.iewDispSquashedInsts 44 # Number of squashed instructions skipped by dispatch
221system.cpu.iew.iewDispLoadInsts 2379 # Number of dispatched load instructions
222system.cpu.iew.iewDispStoreInsts 1816 # Number of dispatched store instructions
223system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions
224system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall
| 377system.cpu.iew.iewDispatchedInsts 21753 # Number of instructions dispatched to IQ
378system.cpu.iew.iewDispSquashedInsts 45 # Number of squashed instructions skipped by dispatch
379system.cpu.iew.iewDispLoadInsts 2439 # Number of dispatched load instructions
380system.cpu.iew.iewDispStoreInsts 1809 # Number of dispatched store instructions
381system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions
382system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
|
225system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
226system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations
| 383system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
384system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations
|
227system.cpu.iew.predictedTakenIncorrect 70 # Number of branches that were predicted taken incorrectly
228system.cpu.iew.predictedNotTakenIncorrect 643 # Number of branches that were predicted not taken incorrectly
229system.cpu.iew.branchMispredicts 713 # Number of branch mispredicts detected at execute
230system.cpu.iew.iewExecutedInsts 17109 # Number of executed instructions
231system.cpu.iew.iewExecLoadInsts 1898 # Number of load instructions executed
232system.cpu.iew.iewExecSquashedInsts 1037 # Number of squashed instructions skipped in execute
| 385system.cpu.iew.predictedTakenIncorrect 71 # Number of branches that were predicted taken incorrectly
386system.cpu.iew.predictedNotTakenIncorrect 652 # Number of branches that were predicted not taken incorrectly
387system.cpu.iew.branchMispredicts 723 # Number of branch mispredicts detected at execute
388system.cpu.iew.iewExecutedInsts 17199 # Number of executed instructions
389system.cpu.iew.iewExecLoadInsts 1930 # Number of load instructions executed
390system.cpu.iew.iewExecSquashedInsts 1061 # Number of squashed instructions skipped in execute
|
233system.cpu.iew.exec_swp 0 # number of swp insts executed
234system.cpu.iew.exec_nop 0 # number of nop insts executed
| 391system.cpu.iew.exec_swp 0 # number of swp insts executed
392system.cpu.iew.exec_nop 0 # number of nop insts executed
|
235system.cpu.iew.exec_refs 3313 # number of memory reference insts executed
236system.cpu.iew.exec_branches 1690 # Number of branches executed
237system.cpu.iew.exec_stores 1415 # Number of stores executed
238system.cpu.iew.exec_rate 0.700299 # Inst execution rate
239system.cpu.iew.wb_sent 16835 # cumulative count of insts sent to commit
240system.cpu.iew.wb_count 16643 # cumulative count of insts written-back
241system.cpu.iew.wb_producers 10619 # num instructions producing a value
242system.cpu.iew.wb_consumers 16444 # num instructions consuming a value
| 393system.cpu.iew.exec_refs 3340 # number of memory reference insts executed
394system.cpu.iew.exec_branches 1687 # Number of branches executed
395system.cpu.iew.exec_stores 1410 # Number of stores executed
396system.cpu.iew.exec_rate 0.716058 # Inst execution rate
397system.cpu.iew.wb_sent 16930 # cumulative count of insts sent to commit
398system.cpu.iew.wb_count 16726 # cumulative count of insts written-back
399system.cpu.iew.wb_producers 10734 # num instructions producing a value
400system.cpu.iew.wb_consumers 16630 # num instructions consuming a value
|
243system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
| 401system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
244system.cpu.iew.wb_rate 0.681225 # insts written-back per cycle
245system.cpu.iew.wb_fanout 0.645767 # average fanout of values written-back
| 402system.cpu.iew.wb_rate 0.696365 # insts written-back per cycle
403system.cpu.iew.wb_fanout 0.645460 # average fanout of values written-back
|
246system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
| 404system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
247system.cpu.commit.commitSquashedInsts 11795 # The number of squashed insts skipped by commit
| 405system.cpu.commit.commitSquashedInsts 12007 # The number of squashed insts skipped by commit
|
248system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
| 406system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
|
249system.cpu.commit.branchMispredicts 595 # The number of times a branch was mispredicted
250system.cpu.commit.committed_per_cycle::samples 15177 # Number of insts commited each cycle
251system.cpu.commit.committed_per_cycle::mean 0.642090 # Number of insts commited each cycle
252system.cpu.commit.committed_per_cycle::stdev 1.514380 # Number of insts commited each cycle
| 407system.cpu.commit.branchMispredicts 606 # The number of times a branch was mispredicted
408system.cpu.commit.committed_per_cycle::samples 15215 # Number of insts commited each cycle
409system.cpu.commit.committed_per_cycle::mean 0.640486 # Number of insts commited each cycle
410system.cpu.commit.committed_per_cycle::stdev 1.512697 # Number of insts commited each cycle
|
253system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
| 411system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
254system.cpu.commit.committed_per_cycle::0 11633 76.65% 76.65% # Number of insts commited each cycle
255system.cpu.commit.committed_per_cycle::1 1329 8.76% 85.41% # Number of insts commited each cycle
256system.cpu.commit.committed_per_cycle::2 606 3.99% 89.40% # Number of insts commited each cycle
257system.cpu.commit.committed_per_cycle::3 700 4.61% 94.01% # Number of insts commited each cycle
258system.cpu.commit.committed_per_cycle::4 357 2.35% 96.36% # Number of insts commited each cycle
259system.cpu.commit.committed_per_cycle::5 136 0.90% 97.26% # Number of insts commited each cycle
260system.cpu.commit.committed_per_cycle::6 126 0.83% 98.09% # Number of insts commited each cycle
261system.cpu.commit.committed_per_cycle::7 80 0.53% 98.62% # Number of insts commited each cycle
262system.cpu.commit.committed_per_cycle::8 210 1.38% 100.00% # Number of insts commited each cycle
| 412system.cpu.commit.committed_per_cycle::0 11677 76.75% 76.75% # Number of insts commited each cycle
413system.cpu.commit.committed_per_cycle::1 1319 8.67% 85.42% # Number of insts commited each cycle
414system.cpu.commit.committed_per_cycle::2 603 3.96% 89.38% # Number of insts commited each cycle
415system.cpu.commit.committed_per_cycle::3 704 4.63% 94.01% # Number of insts commited each cycle
416system.cpu.commit.committed_per_cycle::4 365 2.40% 96.40% # Number of insts commited each cycle
417system.cpu.commit.committed_per_cycle::5 135 0.89% 97.29% # Number of insts commited each cycle
418system.cpu.commit.committed_per_cycle::6 125 0.82% 98.11% # Number of insts commited each cycle
419system.cpu.commit.committed_per_cycle::7 73 0.48% 98.59% # Number of insts commited each cycle
420system.cpu.commit.committed_per_cycle::8 214 1.41% 100.00% # Number of insts commited each cycle
|
263system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
264system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
265system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
| 421system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
422system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
423system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
266system.cpu.commit.committed_per_cycle::total 15177 # Number of insts commited each cycle
| 424system.cpu.commit.committed_per_cycle::total 15215 # Number of insts commited each cycle
|
267system.cpu.commit.committedInsts 5380 # Number of instructions committed
268system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed
269system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
270system.cpu.commit.refs 1986 # Number of memory references committed
271system.cpu.commit.loads 1052 # Number of loads committed
272system.cpu.commit.membars 0 # Number of memory barriers committed
273system.cpu.commit.branches 1208 # Number of branches committed
274system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
275system.cpu.commit.int_insts 9650 # Number of committed integer instructions.
276system.cpu.commit.function_calls 0 # Number of function calls committed.
| 425system.cpu.commit.committedInsts 5380 # Number of instructions committed
426system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed
427system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
428system.cpu.commit.refs 1986 # Number of memory references committed
429system.cpu.commit.loads 1052 # Number of loads committed
430system.cpu.commit.membars 0 # Number of memory barriers committed
431system.cpu.commit.branches 1208 # Number of branches committed
432system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
433system.cpu.commit.int_insts 9650 # Number of committed integer instructions.
434system.cpu.commit.function_calls 0 # Number of function calls committed.
|
277system.cpu.commit.bw_lim_events 210 # number cycles where commit BW limit reached
| 435system.cpu.commit.bw_lim_events 214 # number cycles where commit BW limit reached
|
278system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
| 436system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
279system.cpu.rob.rob_reads 36507 # The number of ROB reads
280system.cpu.rob.rob_writes 45058 # The number of ROB writes
281system.cpu.timesIdled 145 # Number of times that the entire CPU went into an idle state and unscheduled itself
282system.cpu.idleCycles 7307 # Total number of cycles that the CPU has spent unscheduled due to idling
| 437system.cpu.rob.rob_reads 36753 # The number of ROB reads
438system.cpu.rob.rob_writes 45519 # The number of ROB writes
439system.cpu.timesIdled 141 # Number of times that the entire CPU went into an idle state and unscheduled itself
440system.cpu.idleCycles 6823 # Total number of cycles that the CPU has spent unscheduled due to idling
|
283system.cpu.committedInsts 5380 # Number of Instructions Simulated
284system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated
285system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
| 441system.cpu.committedInsts 5380 # Number of Instructions Simulated
442system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated
443system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
|
286system.cpu.cpi 4.541078 # CPI: Cycles Per Instruction
287system.cpu.cpi_total 4.541078 # CPI: Total CPI of All Threads
288system.cpu.ipc 0.220212 # IPC: Instructions Per Cycle
289system.cpu.ipc_total 0.220212 # IPC: Total IPC of All Threads
290system.cpu.int_regfile_reads 30201 # number of integer regfile reads
291system.cpu.int_regfile_writes 17927 # number of integer regfile writes
| 444system.cpu.cpi 4.464498 # CPI: Cycles Per Instruction
445system.cpu.cpi_total 4.464498 # CPI: Total CPI of All Threads
446system.cpu.ipc 0.223989 # IPC: Instructions Per Cycle
447system.cpu.ipc_total 0.223989 # IPC: Total IPC of All Threads
448system.cpu.int_regfile_reads 30259 # number of integer regfile reads
449system.cpu.int_regfile_writes 18088 # number of integer regfile writes
|
292system.cpu.fp_regfile_reads 4 # number of floating regfile reads
| 450system.cpu.fp_regfile_reads 4 # number of floating regfile reads
|
293system.cpu.misc_regfile_reads 7454 # number of misc regfile reads
| 451system.cpu.misc_regfile_reads 7500 # number of misc regfile reads
|
294system.cpu.icache.replacements 0 # number of replacements
| 452system.cpu.icache.replacements 0 # number of replacements
|
295system.cpu.icache.tagsinuse 147.121871 # Cycle average of tags in use
296system.cpu.icache.total_refs 1595 # Total number of references to valid blocks.
297system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks.
298system.cpu.icache.avg_refs 5.195440 # Average number of references to valid blocks.
| 453system.cpu.icache.tagsinuse 149.891095 # Cycle average of tags in use
454system.cpu.icache.total_refs 1605 # Total number of references to valid blocks.
455system.cpu.icache.sampled_refs 305 # Sample count of references to valid blocks.
456system.cpu.icache.avg_refs 5.262295 # Average number of references to valid blocks.
|
299system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 457system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
300system.cpu.icache.occ_blocks::cpu.inst 147.121871 # Average occupied blocks per requestor
301system.cpu.icache.occ_percent::cpu.inst 0.071837 # Average percentage of cache occupancy
302system.cpu.icache.occ_percent::total 0.071837 # Average percentage of cache occupancy
303system.cpu.icache.ReadReq_hits::cpu.inst 1595 # number of ReadReq hits
304system.cpu.icache.ReadReq_hits::total 1595 # number of ReadReq hits
305system.cpu.icache.demand_hits::cpu.inst 1595 # number of demand (read+write) hits
306system.cpu.icache.demand_hits::total 1595 # number of demand (read+write) hits
307system.cpu.icache.overall_hits::cpu.inst 1595 # number of overall hits
308system.cpu.icache.overall_hits::total 1595 # number of overall hits
309system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses
310system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses
311system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses
312system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses
313system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses
314system.cpu.icache.overall_misses::total 399 # number of overall misses
315system.cpu.icache.ReadReq_miss_latency::cpu.inst 14232000 # number of ReadReq miss cycles
316system.cpu.icache.ReadReq_miss_latency::total 14232000 # number of ReadReq miss cycles
317system.cpu.icache.demand_miss_latency::cpu.inst 14232000 # number of demand (read+write) miss cycles
318system.cpu.icache.demand_miss_latency::total 14232000 # number of demand (read+write) miss cycles
319system.cpu.icache.overall_miss_latency::cpu.inst 14232000 # number of overall miss cycles
320system.cpu.icache.overall_miss_latency::total 14232000 # number of overall miss cycles
321system.cpu.icache.ReadReq_accesses::cpu.inst 1994 # number of ReadReq accesses(hits+misses)
322system.cpu.icache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses)
323system.cpu.icache.demand_accesses::cpu.inst 1994 # number of demand (read+write) accesses
324system.cpu.icache.demand_accesses::total 1994 # number of demand (read+write) accesses
325system.cpu.icache.overall_accesses::cpu.inst 1994 # number of overall (read+write) accesses
326system.cpu.icache.overall_accesses::total 1994 # number of overall (read+write) accesses
327system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200100 # miss rate for ReadReq accesses
328system.cpu.icache.ReadReq_miss_rate::total 0.200100 # miss rate for ReadReq accesses
329system.cpu.icache.demand_miss_rate::cpu.inst 0.200100 # miss rate for demand accesses
330system.cpu.icache.demand_miss_rate::total 0.200100 # miss rate for demand accesses
331system.cpu.icache.overall_miss_rate::cpu.inst 0.200100 # miss rate for overall accesses
332system.cpu.icache.overall_miss_rate::total 0.200100 # miss rate for overall accesses
333system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35669.172932 # average ReadReq miss latency
334system.cpu.icache.ReadReq_avg_miss_latency::total 35669.172932 # average ReadReq miss latency
335system.cpu.icache.demand_avg_miss_latency::cpu.inst 35669.172932 # average overall miss latency
336system.cpu.icache.demand_avg_miss_latency::total 35669.172932 # average overall miss latency
337system.cpu.icache.overall_avg_miss_latency::cpu.inst 35669.172932 # average overall miss latency
338system.cpu.icache.overall_avg_miss_latency::total 35669.172932 # average overall miss latency
| 458system.cpu.icache.occ_blocks::cpu.inst 149.891095 # Average occupied blocks per requestor
459system.cpu.icache.occ_percent::cpu.inst 0.073189 # Average percentage of cache occupancy
460system.cpu.icache.occ_percent::total 0.073189 # Average percentage of cache occupancy
461system.cpu.icache.ReadReq_hits::cpu.inst 1605 # number of ReadReq hits
462system.cpu.icache.ReadReq_hits::total 1605 # number of ReadReq hits
463system.cpu.icache.demand_hits::cpu.inst 1605 # number of demand (read+write) hits
464system.cpu.icache.demand_hits::total 1605 # number of demand (read+write) hits
465system.cpu.icache.overall_hits::cpu.inst 1605 # number of overall hits
466system.cpu.icache.overall_hits::total 1605 # number of overall hits
467system.cpu.icache.ReadReq_misses::cpu.inst 394 # number of ReadReq misses
468system.cpu.icache.ReadReq_misses::total 394 # number of ReadReq misses
469system.cpu.icache.demand_misses::cpu.inst 394 # number of demand (read+write) misses
470system.cpu.icache.demand_misses::total 394 # number of demand (read+write) misses
471system.cpu.icache.overall_misses::cpu.inst 394 # number of overall misses
472system.cpu.icache.overall_misses::total 394 # number of overall misses
473system.cpu.icache.ReadReq_miss_latency::cpu.inst 13338000 # number of ReadReq miss cycles
474system.cpu.icache.ReadReq_miss_latency::total 13338000 # number of ReadReq miss cycles
475system.cpu.icache.demand_miss_latency::cpu.inst 13338000 # number of demand (read+write) miss cycles
476system.cpu.icache.demand_miss_latency::total 13338000 # number of demand (read+write) miss cycles
477system.cpu.icache.overall_miss_latency::cpu.inst 13338000 # number of overall miss cycles
478system.cpu.icache.overall_miss_latency::total 13338000 # number of overall miss cycles
479system.cpu.icache.ReadReq_accesses::cpu.inst 1999 # number of ReadReq accesses(hits+misses)
480system.cpu.icache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses)
481system.cpu.icache.demand_accesses::cpu.inst 1999 # number of demand (read+write) accesses
482system.cpu.icache.demand_accesses::total 1999 # number of demand (read+write) accesses
483system.cpu.icache.overall_accesses::cpu.inst 1999 # number of overall (read+write) accesses
484system.cpu.icache.overall_accesses::total 1999 # number of overall (read+write) accesses
485system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197099 # miss rate for ReadReq accesses
486system.cpu.icache.ReadReq_miss_rate::total 0.197099 # miss rate for ReadReq accesses
487system.cpu.icache.demand_miss_rate::cpu.inst 0.197099 # miss rate for demand accesses
488system.cpu.icache.demand_miss_rate::total 0.197099 # miss rate for demand accesses
489system.cpu.icache.overall_miss_rate::cpu.inst 0.197099 # miss rate for overall accesses
490system.cpu.icache.overall_miss_rate::total 0.197099 # miss rate for overall accesses
491system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33852.791878 # average ReadReq miss latency
492system.cpu.icache.ReadReq_avg_miss_latency::total 33852.791878 # average ReadReq miss latency
493system.cpu.icache.demand_avg_miss_latency::cpu.inst 33852.791878 # average overall miss latency
494system.cpu.icache.demand_avg_miss_latency::total 33852.791878 # average overall miss latency
495system.cpu.icache.overall_avg_miss_latency::cpu.inst 33852.791878 # average overall miss latency
496system.cpu.icache.overall_avg_miss_latency::total 33852.791878 # average overall miss latency
|
339system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
340system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
341system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
342system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
343system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
344system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
345system.cpu.icache.fast_writes 0 # number of fast writes performed
346system.cpu.icache.cache_copies 0 # number of cache copies performed
| 497system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
498system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
499system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
500system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
501system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
502system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
503system.cpu.icache.fast_writes 0 # number of fast writes performed
504system.cpu.icache.cache_copies 0 # number of cache copies performed
|
347system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits
348system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits
349system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits
350system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits
351system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits
352system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits
353system.cpu.icache.ReadReq_mshr_misses::cpu.inst 307 # number of ReadReq MSHR misses
354system.cpu.icache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses
355system.cpu.icache.demand_mshr_misses::cpu.inst 307 # number of demand (read+write) MSHR misses
356system.cpu.icache.demand_mshr_misses::total 307 # number of demand (read+write) MSHR misses
357system.cpu.icache.overall_mshr_misses::cpu.inst 307 # number of overall MSHR misses
358system.cpu.icache.overall_mshr_misses::total 307 # number of overall MSHR misses
359system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11314000 # number of ReadReq MSHR miss cycles
360system.cpu.icache.ReadReq_mshr_miss_latency::total 11314000 # number of ReadReq MSHR miss cycles
361system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11314000 # number of demand (read+write) MSHR miss cycles
362system.cpu.icache.demand_mshr_miss_latency::total 11314000 # number of demand (read+write) MSHR miss cycles
363system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11314000 # number of overall MSHR miss cycles
364system.cpu.icache.overall_mshr_miss_latency::total 11314000 # number of overall MSHR miss cycles
365system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153962 # mshr miss rate for ReadReq accesses
366system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153962 # mshr miss rate for ReadReq accesses
367system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153962 # mshr miss rate for demand accesses
368system.cpu.icache.demand_mshr_miss_rate::total 0.153962 # mshr miss rate for demand accesses
369system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153962 # mshr miss rate for overall accesses
370system.cpu.icache.overall_mshr_miss_rate::total 0.153962 # mshr miss rate for overall accesses
371system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36853.420195 # average ReadReq mshr miss latency
372system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36853.420195 # average ReadReq mshr miss latency
373system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36853.420195 # average overall mshr miss latency
374system.cpu.icache.demand_avg_mshr_miss_latency::total 36853.420195 # average overall mshr miss latency
375system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36853.420195 # average overall mshr miss latency
376system.cpu.icache.overall_avg_mshr_miss_latency::total 36853.420195 # average overall mshr miss latency
| 505system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits
506system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits
507system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits
508system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits
509system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits
510system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits
511system.cpu.icache.ReadReq_mshr_misses::cpu.inst 306 # number of ReadReq MSHR misses
512system.cpu.icache.ReadReq_mshr_misses::total 306 # number of ReadReq MSHR misses
513system.cpu.icache.demand_mshr_misses::cpu.inst 306 # number of demand (read+write) MSHR misses
514system.cpu.icache.demand_mshr_misses::total 306 # number of demand (read+write) MSHR misses
515system.cpu.icache.overall_mshr_misses::cpu.inst 306 # number of overall MSHR misses
516system.cpu.icache.overall_mshr_misses::total 306 # number of overall MSHR misses
517system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10626000 # number of ReadReq MSHR miss cycles
518system.cpu.icache.ReadReq_mshr_miss_latency::total 10626000 # number of ReadReq MSHR miss cycles
519system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10626000 # number of demand (read+write) MSHR miss cycles
520system.cpu.icache.demand_mshr_miss_latency::total 10626000 # number of demand (read+write) MSHR miss cycles
521system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10626000 # number of overall MSHR miss cycles
522system.cpu.icache.overall_mshr_miss_latency::total 10626000 # number of overall MSHR miss cycles
523system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for ReadReq accesses
524system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153077 # mshr miss rate for ReadReq accesses
525system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for demand accesses
526system.cpu.icache.demand_mshr_miss_rate::total 0.153077 # mshr miss rate for demand accesses
527system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for overall accesses
528system.cpu.icache.overall_mshr_miss_rate::total 0.153077 # mshr miss rate for overall accesses
529system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34725.490196 # average ReadReq mshr miss latency
530system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34725.490196 # average ReadReq mshr miss latency
531system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34725.490196 # average overall mshr miss latency
532system.cpu.icache.demand_avg_mshr_miss_latency::total 34725.490196 # average overall mshr miss latency
533system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34725.490196 # average overall mshr miss latency
534system.cpu.icache.overall_avg_mshr_miss_latency::total 34725.490196 # average overall mshr miss latency
|
377system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
378system.cpu.dcache.replacements 0 # number of replacements
| 535system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
536system.cpu.dcache.replacements 0 # number of replacements
|
379system.cpu.dcache.tagsinuse 85.059195 # Cycle average of tags in use
380system.cpu.dcache.total_refs 2428 # Total number of references to valid blocks.
381system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
382system.cpu.dcache.avg_refs 16.630137 # Average number of references to valid blocks.
| 537system.cpu.dcache.tagsinuse 84.879845 # Cycle average of tags in use
538system.cpu.dcache.total_refs 2447 # Total number of references to valid blocks.
539system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks.
540system.cpu.dcache.avg_refs 16.875862 # Average number of references to valid blocks.
|
383system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 541system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
384system.cpu.dcache.occ_blocks::cpu.data 85.059195 # Average occupied blocks per requestor
385system.cpu.dcache.occ_percent::cpu.data 0.020766 # Average percentage of cache occupancy
386system.cpu.dcache.occ_percent::total 0.020766 # Average percentage of cache occupancy
387system.cpu.dcache.ReadReq_hits::cpu.data 1570 # number of ReadReq hits
388system.cpu.dcache.ReadReq_hits::total 1570 # number of ReadReq hits
| 542system.cpu.dcache.occ_blocks::cpu.data 84.879845 # Average occupied blocks per requestor
543system.cpu.dcache.occ_percent::cpu.data 0.020723 # Average percentage of cache occupancy
544system.cpu.dcache.occ_percent::total 0.020723 # Average percentage of cache occupancy
545system.cpu.dcache.ReadReq_hits::cpu.data 1589 # number of ReadReq hits
546system.cpu.dcache.ReadReq_hits::total 1589 # number of ReadReq hits
|
389system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
390system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
| 547system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
548system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
|
391system.cpu.dcache.demand_hits::cpu.data 2428 # number of demand (read+write) hits
392system.cpu.dcache.demand_hits::total 2428 # number of demand (read+write) hits
393system.cpu.dcache.overall_hits::cpu.data 2428 # number of overall hits
394system.cpu.dcache.overall_hits::total 2428 # number of overall hits
395system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses
396system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses
| 549system.cpu.dcache.demand_hits::cpu.data 2447 # number of demand (read+write) hits
550system.cpu.dcache.demand_hits::total 2447 # number of demand (read+write) hits
551system.cpu.dcache.overall_hits::cpu.data 2447 # number of overall hits
552system.cpu.dcache.overall_hits::total 2447 # number of overall hits
553system.cpu.dcache.ReadReq_misses::cpu.data 132 # number of ReadReq misses
554system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses
|
397system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
398system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
| 555system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
556system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
|
399system.cpu.dcache.demand_misses::cpu.data 209 # number of demand (read+write) misses
400system.cpu.dcache.demand_misses::total 209 # number of demand (read+write) misses
401system.cpu.dcache.overall_misses::cpu.data 209 # number of overall misses
402system.cpu.dcache.overall_misses::total 209 # number of overall misses
403system.cpu.dcache.ReadReq_miss_latency::cpu.data 4790000 # number of ReadReq miss cycles
404system.cpu.dcache.ReadReq_miss_latency::total 4790000 # number of ReadReq miss cycles
405system.cpu.dcache.WriteReq_miss_latency::cpu.data 3017000 # number of WriteReq miss cycles
406system.cpu.dcache.WriteReq_miss_latency::total 3017000 # number of WriteReq miss cycles
407system.cpu.dcache.demand_miss_latency::cpu.data 7807000 # number of demand (read+write) miss cycles
408system.cpu.dcache.demand_miss_latency::total 7807000 # number of demand (read+write) miss cycles
409system.cpu.dcache.overall_miss_latency::cpu.data 7807000 # number of overall miss cycles
410system.cpu.dcache.overall_miss_latency::total 7807000 # number of overall miss cycles
411system.cpu.dcache.ReadReq_accesses::cpu.data 1703 # number of ReadReq accesses(hits+misses)
412system.cpu.dcache.ReadReq_accesses::total 1703 # number of ReadReq accesses(hits+misses)
| 557system.cpu.dcache.demand_misses::cpu.data 208 # number of demand (read+write) misses
558system.cpu.dcache.demand_misses::total 208 # number of demand (read+write) misses
559system.cpu.dcache.overall_misses::cpu.data 208 # number of overall misses
560system.cpu.dcache.overall_misses::total 208 # number of overall misses
561system.cpu.dcache.ReadReq_miss_latency::cpu.data 5132000 # number of ReadReq miss cycles
562system.cpu.dcache.ReadReq_miss_latency::total 5132000 # number of ReadReq miss cycles
563system.cpu.dcache.WriteReq_miss_latency::cpu.data 3133000 # number of WriteReq miss cycles
564system.cpu.dcache.WriteReq_miss_latency::total 3133000 # number of WriteReq miss cycles
565system.cpu.dcache.demand_miss_latency::cpu.data 8265000 # number of demand (read+write) miss cycles
566system.cpu.dcache.demand_miss_latency::total 8265000 # number of demand (read+write) miss cycles
567system.cpu.dcache.overall_miss_latency::cpu.data 8265000 # number of overall miss cycles
568system.cpu.dcache.overall_miss_latency::total 8265000 # number of overall miss cycles
569system.cpu.dcache.ReadReq_accesses::cpu.data 1721 # number of ReadReq accesses(hits+misses)
570system.cpu.dcache.ReadReq_accesses::total 1721 # number of ReadReq accesses(hits+misses)
|
413system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
414system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
| 571system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
572system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
|
415system.cpu.dcache.demand_accesses::cpu.data 2637 # number of demand (read+write) accesses
416system.cpu.dcache.demand_accesses::total 2637 # number of demand (read+write) accesses
417system.cpu.dcache.overall_accesses::cpu.data 2637 # number of overall (read+write) accesses
418system.cpu.dcache.overall_accesses::total 2637 # number of overall (read+write) accesses
419system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078097 # miss rate for ReadReq accesses
420system.cpu.dcache.ReadReq_miss_rate::total 0.078097 # miss rate for ReadReq accesses
| 573system.cpu.dcache.demand_accesses::cpu.data 2655 # number of demand (read+write) accesses
574system.cpu.dcache.demand_accesses::total 2655 # number of demand (read+write) accesses
575system.cpu.dcache.overall_accesses::cpu.data 2655 # number of overall (read+write) accesses
576system.cpu.dcache.overall_accesses::total 2655 # number of overall (read+write) accesses
577system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076700 # miss rate for ReadReq accesses
578system.cpu.dcache.ReadReq_miss_rate::total 0.076700 # miss rate for ReadReq accesses
|
421system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses
422system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses
| 579system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses
580system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses
|
423system.cpu.dcache.demand_miss_rate::cpu.data 0.079257 # miss rate for demand accesses
424system.cpu.dcache.demand_miss_rate::total 0.079257 # miss rate for demand accesses
425system.cpu.dcache.overall_miss_rate::cpu.data 0.079257 # miss rate for overall accesses
426system.cpu.dcache.overall_miss_rate::total 0.079257 # miss rate for overall accesses
427system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36015.037594 # average ReadReq miss latency
428system.cpu.dcache.ReadReq_avg_miss_latency::total 36015.037594 # average ReadReq miss latency
429system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39697.368421 # average WriteReq miss latency
430system.cpu.dcache.WriteReq_avg_miss_latency::total 39697.368421 # average WriteReq miss latency
431system.cpu.dcache.demand_avg_miss_latency::cpu.data 37354.066986 # average overall miss latency
432system.cpu.dcache.demand_avg_miss_latency::total 37354.066986 # average overall miss latency
433system.cpu.dcache.overall_avg_miss_latency::cpu.data 37354.066986 # average overall miss latency
434system.cpu.dcache.overall_avg_miss_latency::total 37354.066986 # average overall miss latency
| 581system.cpu.dcache.demand_miss_rate::cpu.data 0.078343 # miss rate for demand accesses
582system.cpu.dcache.demand_miss_rate::total 0.078343 # miss rate for demand accesses
583system.cpu.dcache.overall_miss_rate::cpu.data 0.078343 # miss rate for overall accesses
584system.cpu.dcache.overall_miss_rate::total 0.078343 # miss rate for overall accesses
585system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38878.787879 # average ReadReq miss latency
586system.cpu.dcache.ReadReq_avg_miss_latency::total 38878.787879 # average ReadReq miss latency
587system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41223.684211 # average WriteReq miss latency
588system.cpu.dcache.WriteReq_avg_miss_latency::total 41223.684211 # average WriteReq miss latency
589system.cpu.dcache.demand_avg_miss_latency::cpu.data 39735.576923 # average overall miss latency
590system.cpu.dcache.demand_avg_miss_latency::total 39735.576923 # average overall miss latency
591system.cpu.dcache.overall_avg_miss_latency::cpu.data 39735.576923 # average overall miss latency
592system.cpu.dcache.overall_avg_miss_latency::total 39735.576923 # average overall miss latency
|
435system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
436system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
437system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
438system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
439system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
440system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
441system.cpu.dcache.fast_writes 0 # number of fast writes performed
442system.cpu.dcache.cache_copies 0 # number of cache copies performed
443system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
444system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits
445system.cpu.dcache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
446system.cpu.dcache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits
447system.cpu.dcache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
448system.cpu.dcache.overall_mshr_hits::total 62 # number of overall MSHR hits
| 593system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
594system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
595system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
596system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
597system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
598system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
599system.cpu.dcache.fast_writes 0 # number of fast writes performed
600system.cpu.dcache.cache_copies 0 # number of cache copies performed
601system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
602system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits
603system.cpu.dcache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
604system.cpu.dcache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits
605system.cpu.dcache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
606system.cpu.dcache.overall_mshr_hits::total 62 # number of overall MSHR hits
|
449system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses
450system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses
| 607system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses
608system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses
|
451system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
452system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
| 609system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
610system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
|
453system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
454system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
455system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
456system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
457system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2826000 # number of ReadReq MSHR miss cycles
458system.cpu.dcache.ReadReq_mshr_miss_latency::total 2826000 # number of ReadReq MSHR miss cycles
459system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2865000 # number of WriteReq MSHR miss cycles
460system.cpu.dcache.WriteReq_mshr_miss_latency::total 2865000 # number of WriteReq MSHR miss cycles
461system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5691000 # number of demand (read+write) MSHR miss cycles
462system.cpu.dcache.demand_mshr_miss_latency::total 5691000 # number of demand (read+write) MSHR miss cycles
463system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5691000 # number of overall MSHR miss cycles
464system.cpu.dcache.overall_mshr_miss_latency::total 5691000 # number of overall MSHR miss cycles
465system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041691 # mshr miss rate for ReadReq accesses
466system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041691 # mshr miss rate for ReadReq accesses
| 611system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
612system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
613system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
614system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
615system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3278500 # number of ReadReq MSHR miss cycles
616system.cpu.dcache.ReadReq_mshr_miss_latency::total 3278500 # number of ReadReq MSHR miss cycles
617system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2981000 # number of WriteReq MSHR miss cycles
618system.cpu.dcache.WriteReq_mshr_miss_latency::total 2981000 # number of WriteReq MSHR miss cycles
619system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6259500 # number of demand (read+write) MSHR miss cycles
620system.cpu.dcache.demand_mshr_miss_latency::total 6259500 # number of demand (read+write) MSHR miss cycles
621system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6259500 # number of overall MSHR miss cycles
622system.cpu.dcache.overall_mshr_miss_latency::total 6259500 # number of overall MSHR miss cycles
623system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040674 # mshr miss rate for ReadReq accesses
624system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040674 # mshr miss rate for ReadReq accesses
|
467system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses
468system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses
| 625system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses
626system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses
|
469system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055745 # mshr miss rate for demand accesses
470system.cpu.dcache.demand_mshr_miss_rate::total 0.055745 # mshr miss rate for demand accesses
471system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055745 # mshr miss rate for overall accesses
472system.cpu.dcache.overall_mshr_miss_rate::total 0.055745 # mshr miss rate for overall accesses
473system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39802.816901 # average ReadReq mshr miss latency
474system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39802.816901 # average ReadReq mshr miss latency
475system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37697.368421 # average WriteReq mshr miss latency
476system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37697.368421 # average WriteReq mshr miss latency
477system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38714.285714 # average overall mshr miss latency
478system.cpu.dcache.demand_avg_mshr_miss_latency::total 38714.285714 # average overall mshr miss latency
479system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38714.285714 # average overall mshr miss latency
480system.cpu.dcache.overall_avg_mshr_miss_latency::total 38714.285714 # average overall mshr miss latency
| 627system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for demand accesses
628system.cpu.dcache.demand_mshr_miss_rate::total 0.054991 # mshr miss rate for demand accesses
629system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for overall accesses
630system.cpu.dcache.overall_mshr_miss_rate::total 0.054991 # mshr miss rate for overall accesses
631system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46835.714286 # average ReadReq mshr miss latency
632system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46835.714286 # average ReadReq mshr miss latency
633system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39223.684211 # average WriteReq mshr miss latency
634system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39223.684211 # average WriteReq mshr miss latency
635system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42873.287671 # average overall mshr miss latency
636system.cpu.dcache.demand_avg_mshr_miss_latency::total 42873.287671 # average overall mshr miss latency
637system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42873.287671 # average overall mshr miss latency
638system.cpu.dcache.overall_avg_mshr_miss_latency::total 42873.287671 # average overall mshr miss latency
|
481system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
482system.cpu.l2cache.replacements 0 # number of replacements
| 639system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
640system.cpu.l2cache.replacements 0 # number of replacements
|
483system.cpu.l2cache.tagsinuse 180.768252 # Cycle average of tags in use
484system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
485system.cpu.l2cache.sampled_refs 375 # Sample count of references to valid blocks.
486system.cpu.l2cache.avg_refs 0.005333 # Average number of references to valid blocks.
| 641system.cpu.l2cache.tagsinuse 182.959089 # Cycle average of tags in use
642system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
643system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
644system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
|
487system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 645system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
488system.cpu.l2cache.occ_blocks::cpu.inst 146.715527 # Average occupied blocks per requestor
489system.cpu.l2cache.occ_blocks::cpu.data 34.052725 # Average occupied blocks per requestor
490system.cpu.l2cache.occ_percent::cpu.inst 0.004477 # Average percentage of cache occupancy
491system.cpu.l2cache.occ_percent::cpu.data 0.001039 # Average percentage of cache occupancy
492system.cpu.l2cache.occ_percent::total 0.005517 # Average percentage of cache occupancy
493system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
494system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
495system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
496system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
497system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
498system.cpu.l2cache.overall_hits::total 2 # number of overall hits
| 646system.cpu.l2cache.occ_blocks::cpu.inst 149.880234 # Average occupied blocks per requestor
647system.cpu.l2cache.occ_blocks::cpu.data 33.078855 # Average occupied blocks per requestor
648system.cpu.l2cache.occ_percent::cpu.inst 0.004574 # Average percentage of cache occupancy
649system.cpu.l2cache.occ_percent::cpu.data 0.001009 # Average percentage of cache occupancy
650system.cpu.l2cache.occ_percent::total 0.005583 # Average percentage of cache occupancy
651system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
652system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
653system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
654system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
655system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
656system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
499system.cpu.l2cache.ReadReq_misses::cpu.inst 305 # number of ReadReq misses
| 657system.cpu.l2cache.ReadReq_misses::cpu.inst 305 # number of ReadReq misses
|
500system.cpu.l2cache.ReadReq_misses::cpu.data 71 # number of ReadReq misses
501system.cpu.l2cache.ReadReq_misses::total 376 # number of ReadReq misses
| 658system.cpu.l2cache.ReadReq_misses::cpu.data 70 # number of ReadReq misses
659system.cpu.l2cache.ReadReq_misses::total 375 # number of ReadReq misses
|
502system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses
503system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses
504system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses
| 660system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses
661system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses
662system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses
|
505system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses
506system.cpu.l2cache.demand_misses::total 452 # number of demand (read+write) misses
| 663system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses
664system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses
|
507system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses
| 665system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses
|
508system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses
509system.cpu.l2cache.overall_misses::total 452 # number of overall misses
510system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11004000 # number of ReadReq miss cycles
511system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2755500 # number of ReadReq miss cycles
512system.cpu.l2cache.ReadReq_miss_latency::total 13759500 # number of ReadReq miss cycles
513system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2789000 # number of ReadExReq miss cycles
514system.cpu.l2cache.ReadExReq_miss_latency::total 2789000 # number of ReadExReq miss cycles
515system.cpu.l2cache.demand_miss_latency::cpu.inst 11004000 # number of demand (read+write) miss cycles
516system.cpu.l2cache.demand_miss_latency::cpu.data 5544500 # number of demand (read+write) miss cycles
517system.cpu.l2cache.demand_miss_latency::total 16548500 # number of demand (read+write) miss cycles
518system.cpu.l2cache.overall_miss_latency::cpu.inst 11004000 # number of overall miss cycles
519system.cpu.l2cache.overall_miss_latency::cpu.data 5544500 # number of overall miss cycles
520system.cpu.l2cache.overall_miss_latency::total 16548500 # number of overall miss cycles
521system.cpu.l2cache.ReadReq_accesses::cpu.inst 307 # number of ReadReq accesses(hits+misses)
522system.cpu.l2cache.ReadReq_accesses::cpu.data 71 # number of ReadReq accesses(hits+misses)
523system.cpu.l2cache.ReadReq_accesses::total 378 # number of ReadReq accesses(hits+misses)
| 666system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses
667system.cpu.l2cache.overall_misses::total 451 # number of overall misses
668system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10319000 # number of ReadReq miss cycles
669system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3209500 # number of ReadReq miss cycles
670system.cpu.l2cache.ReadReq_miss_latency::total 13528500 # number of ReadReq miss cycles
671system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2905000 # number of ReadExReq miss cycles
672system.cpu.l2cache.ReadExReq_miss_latency::total 2905000 # number of ReadExReq miss cycles
673system.cpu.l2cache.demand_miss_latency::cpu.inst 10319000 # number of demand (read+write) miss cycles
674system.cpu.l2cache.demand_miss_latency::cpu.data 6114500 # number of demand (read+write) miss cycles
675system.cpu.l2cache.demand_miss_latency::total 16433500 # number of demand (read+write) miss cycles
676system.cpu.l2cache.overall_miss_latency::cpu.inst 10319000 # number of overall miss cycles
677system.cpu.l2cache.overall_miss_latency::cpu.data 6114500 # number of overall miss cycles
678system.cpu.l2cache.overall_miss_latency::total 16433500 # number of overall miss cycles
679system.cpu.l2cache.ReadReq_accesses::cpu.inst 306 # number of ReadReq accesses(hits+misses)
680system.cpu.l2cache.ReadReq_accesses::cpu.data 70 # number of ReadReq accesses(hits+misses)
681system.cpu.l2cache.ReadReq_accesses::total 376 # number of ReadReq accesses(hits+misses)
|
524system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses)
525system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses)
| 682system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses)
683system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses)
|
526system.cpu.l2cache.demand_accesses::cpu.inst 307 # number of demand (read+write) accesses
527system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
528system.cpu.l2cache.demand_accesses::total 454 # number of demand (read+write) accesses
529system.cpu.l2cache.overall_accesses::cpu.inst 307 # number of overall (read+write) accesses
530system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
531system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses
532system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993485 # miss rate for ReadReq accesses
| 684system.cpu.l2cache.demand_accesses::cpu.inst 306 # number of demand (read+write) accesses
685system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses
686system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses
687system.cpu.l2cache.overall_accesses::cpu.inst 306 # number of overall (read+write) accesses
688system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses
689system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses
690system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996732 # miss rate for ReadReq accesses
|
533system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
| 691system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
534system.cpu.l2cache.ReadReq_miss_rate::total 0.994709 # miss rate for ReadReq accesses
| 692system.cpu.l2cache.ReadReq_miss_rate::total 0.997340 # miss rate for ReadReq accesses
|
535system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
536system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
| 693system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
694system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
537system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993485 # miss rate for demand accesses
| 695system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996732 # miss rate for demand accesses
|
538system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
| 696system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
539system.cpu.l2cache.demand_miss_rate::total 0.995595 # miss rate for demand accesses
540system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993485 # miss rate for overall accesses
| 697system.cpu.l2cache.demand_miss_rate::total 0.997788 # miss rate for demand accesses
698system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996732 # miss rate for overall accesses
|
541system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
| 699system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
542system.cpu.l2cache.overall_miss_rate::total 0.995595 # miss rate for overall accesses
543system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36078.688525 # average ReadReq miss latency
544system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38809.859155 # average ReadReq miss latency
545system.cpu.l2cache.ReadReq_avg_miss_latency::total 36594.414894 # average ReadReq miss latency
546system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36697.368421 # average ReadExReq miss latency
547system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36697.368421 # average ReadExReq miss latency
548system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36078.688525 # average overall miss latency
549system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37717.687075 # average overall miss latency
550system.cpu.l2cache.demand_avg_miss_latency::total 36611.725664 # average overall miss latency
551system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36078.688525 # average overall miss latency
552system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37717.687075 # average overall miss latency
553system.cpu.l2cache.overall_avg_miss_latency::total 36611.725664 # average overall miss latency
| 700system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses
701system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 33832.786885 # average ReadReq miss latency
702system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45850 # average ReadReq miss latency
703system.cpu.l2cache.ReadReq_avg_miss_latency::total 36076 # average ReadReq miss latency
704system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38223.684211 # average ReadExReq miss latency
705system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38223.684211 # average ReadExReq miss latency
706system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 33832.786885 # average overall miss latency
707system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41880.136986 # average overall miss latency
708system.cpu.l2cache.demand_avg_miss_latency::total 36437.915743 # average overall miss latency
709system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 33832.786885 # average overall miss latency
710system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41880.136986 # average overall miss latency
711system.cpu.l2cache.overall_avg_miss_latency::total 36437.915743 # average overall miss latency
|
554system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
555system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
556system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
557system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
558system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
559system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
560system.cpu.l2cache.fast_writes 0 # number of fast writes performed
561system.cpu.l2cache.cache_copies 0 # number of cache copies performed
562system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 305 # number of ReadReq MSHR misses
| 712system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
713system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
714system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
715system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
716system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
717system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
718system.cpu.l2cache.fast_writes 0 # number of fast writes performed
719system.cpu.l2cache.cache_copies 0 # number of cache copies performed
720system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 305 # number of ReadReq MSHR misses
|
563system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses
564system.cpu.l2cache.ReadReq_mshr_misses::total 376 # number of ReadReq MSHR misses
| 721system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses
722system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses
|
565system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses
566system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses
567system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses
| 723system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses
724system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses
725system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses
|
568system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
569system.cpu.l2cache.demand_mshr_misses::total 452 # number of demand (read+write) MSHR misses
| 726system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
727system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses
|
570system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses
| 728system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses
|
571system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
572system.cpu.l2cache.overall_mshr_misses::total 452 # number of overall MSHR misses
573system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10035000 # number of ReadReq MSHR miss cycles
574system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2539500 # number of ReadReq MSHR miss cycles
575system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12574500 # number of ReadReq MSHR miss cycles
576system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2558000 # number of ReadExReq MSHR miss cycles
577system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2558000 # number of ReadExReq MSHR miss cycles
578system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10035000 # number of demand (read+write) MSHR miss cycles
579system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5097500 # number of demand (read+write) MSHR miss cycles
580system.cpu.l2cache.demand_mshr_miss_latency::total 15132500 # number of demand (read+write) MSHR miss cycles
581system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10035000 # number of overall MSHR miss cycles
582system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5097500 # number of overall MSHR miss cycles
583system.cpu.l2cache.overall_mshr_miss_latency::total 15132500 # number of overall MSHR miss cycles
584system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993485 # mshr miss rate for ReadReq accesses
| 729system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
730system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses
731system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9239430 # number of ReadReq MSHR miss cycles
732system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2977566 # number of ReadReq MSHR miss cycles
733system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12216996 # number of ReadReq MSHR miss cycles
734system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2628106 # number of ReadExReq MSHR miss cycles
735system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2628106 # number of ReadExReq MSHR miss cycles
736system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9239430 # number of demand (read+write) MSHR miss cycles
737system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5605672 # number of demand (read+write) MSHR miss cycles
738system.cpu.l2cache.demand_mshr_miss_latency::total 14845102 # number of demand (read+write) MSHR miss cycles
739system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9239430 # number of overall MSHR miss cycles
740system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5605672 # number of overall MSHR miss cycles
741system.cpu.l2cache.overall_mshr_miss_latency::total 14845102 # number of overall MSHR miss cycles
742system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for ReadReq accesses
|
585system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
| 743system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
586system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994709 # mshr miss rate for ReadReq accesses
| 744system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses
|
587system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
588system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
| 745system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
746system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
589system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993485 # mshr miss rate for demand accesses
| 747system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for demand accesses
|
590system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
| 748system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
591system.cpu.l2cache.demand_mshr_miss_rate::total 0.995595 # mshr miss rate for demand accesses
592system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993485 # mshr miss rate for overall accesses
| 749system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 # mshr miss rate for demand accesses
750system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for overall accesses
|
593system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
| 751system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
594system.cpu.l2cache.overall_mshr_miss_rate::total 0.995595 # mshr miss rate for overall accesses
595system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32901.639344 # average ReadReq mshr miss latency
596system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35767.605634 # average ReadReq mshr miss latency
597system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33442.819149 # average ReadReq mshr miss latency
598system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33657.894737 # average ReadExReq mshr miss latency
599system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33657.894737 # average ReadExReq mshr miss latency
600system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32901.639344 # average overall mshr miss latency
601system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34676.870748 # average overall mshr miss latency
602system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33478.982301 # average overall mshr miss latency
603system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32901.639344 # average overall mshr miss latency
604system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34676.870748 # average overall mshr miss latency
605system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33478.982301 # average overall mshr miss latency
| 752system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses
753system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30293.213115 # average ReadReq mshr miss latency
754system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42536.657143 # average ReadReq mshr miss latency
755system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32578.656000 # average ReadReq mshr miss latency
756system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34580.342105 # average ReadExReq mshr miss latency
757system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34580.342105 # average ReadExReq mshr miss latency
758system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30293.213115 # average overall mshr miss latency
759system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38395.013699 # average overall mshr miss latency
760system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32915.968958 # average overall mshr miss latency
761system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30293.213115 # average overall mshr miss latency
762system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38395.013699 # average overall mshr miss latency
763system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32915.968958 # average overall mshr miss latency
|
606system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
607
608---------- End Simulation Statistics ----------
| 764system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
765
766---------- End Simulation Statistics ----------
|