1
2---------- Begin Simulation Statistics ----------
| 1
2---------- Begin Simulation Statistics ----------
|
3sim_seconds 0.000012 # Number of seconds simulated
4sim_ticks 12198000 # Number of ticks simulated
5final_tick 12198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 3sim_seconds 0.000013 # Number of seconds simulated
4sim_ticks 12803000 # Number of ticks simulated
5final_tick 12803000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 39950 # Simulator instruction rate (inst/s)
8host_op_rate 72345 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 89952499 # Simulator tick rate (ticks/s)
10host_mem_usage 224288 # Number of bytes of host memory used
11host_seconds 0.14 # Real time elapsed on the host
| 7host_inst_rate 24032 # Simulator instruction rate (inst/s)
8host_op_rate 43521 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 56800152 # Simulator tick rate (ticks/s)
10host_mem_usage 227452 # Number of bytes of host memory used
11host_seconds 0.23 # Real time elapsed on the host
|
12sim_insts 5416 # Number of instructions simulated
13sim_ops 9809 # Number of ops (including micro ops) simulated
| 12sim_insts 5416 # Number of instructions simulated
13sim_ops 9809 # Number of ops (including micro ops) simulated
|
14system.physmem.bytes_read::cpu.inst 19328 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 9536 # Number of bytes read from this memory
16system.physmem.bytes_read::total 28864 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 19328 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 19328 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 302 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 149 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 451 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1584522053 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 781767503 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 2366289556 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1584522053 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1584522053 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1584522053 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 781767503 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 2366289556 # Total bandwidth to/from this memory (bytes/s)
| 14system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 9280 # Number of bytes read from this memory
16system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1504647348 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 724830118 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 2229477466 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1504647348 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1504647348 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1504647348 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 724830118 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 2229477466 # Total bandwidth to/from this memory (bytes/s)
|
30system.cpu.workload.num_syscalls 11 # Number of system calls
| 30system.cpu.workload.num_syscalls 11 # Number of system calls
|
31system.cpu.numCycles 24397 # number of cpu cycles simulated
| 31system.cpu.numCycles 25607 # number of cpu cycles simulated
|
32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
| 32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
34system.cpu.BPredUnit.lookups 3206 # Number of BP lookups
35system.cpu.BPredUnit.condPredicted 3206 # Number of conditional branches predicted
36system.cpu.BPredUnit.condIncorrect 560 # Number of conditional branches incorrect
37system.cpu.BPredUnit.BTBLookups 2627 # Number of BTB lookups
38system.cpu.BPredUnit.BTBHits 792 # Number of BTB hits
| 34system.cpu.BPredUnit.lookups 3125 # Number of BP lookups
35system.cpu.BPredUnit.condPredicted 3125 # Number of conditional branches predicted
36system.cpu.BPredUnit.condIncorrect 558 # Number of conditional branches incorrect
37system.cpu.BPredUnit.BTBLookups 2605 # Number of BTB lookups
38system.cpu.BPredUnit.BTBHits 830 # Number of BTB hits
|
39system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
40system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
41system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
| 39system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
40system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
41system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
42system.cpu.fetch.icacheStallCycles 7375 # Number of cycles fetch is stalled on an Icache miss
43system.cpu.fetch.Insts 15410 # Number of instructions fetch has processed
44system.cpu.fetch.Branches 3206 # Number of branches that fetch encountered
45system.cpu.fetch.predictedBranches 792 # Number of branches that fetch has predicted taken
46system.cpu.fetch.Cycles 4170 # Number of cycles fetch has run and was not squashing or blocked
47system.cpu.fetch.SquashCycles 2487 # Number of cycles fetch has spent squashing
48system.cpu.fetch.BlockedCycles 3163 # Number of cycles fetch has spent blocked
49system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
50system.cpu.fetch.PendingTrapStallCycles 98 # Number of stall cycles due to pending traps
51system.cpu.fetch.CacheLines 1951 # Number of cache lines fetched
| 42system.cpu.fetch.icacheStallCycles 8034 # Number of cycles fetch is stalled on an Icache miss
43system.cpu.fetch.Insts 14981 # Number of instructions fetch has processed
44system.cpu.fetch.Branches 3125 # Number of branches that fetch encountered
45system.cpu.fetch.predictedBranches 830 # Number of branches that fetch has predicted taken
46system.cpu.fetch.Cycles 4070 # Number of cycles fetch has run and was not squashing or blocked
47system.cpu.fetch.SquashCycles 2483 # Number of cycles fetch has spent squashing
48system.cpu.fetch.BlockedCycles 3408 # Number of cycles fetch has spent blocked
49system.cpu.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
50system.cpu.fetch.PendingTrapStallCycles 244 # Number of stall cycles due to pending traps
51system.cpu.fetch.CacheLines 1957 # Number of cache lines fetched
|
52system.cpu.fetch.IcacheSquashes 281 # Number of outstanding Icache misses that were squashed
| 52system.cpu.fetch.IcacheSquashes 281 # Number of outstanding Icache misses that were squashed
|
53system.cpu.fetch.rateDist::samples 16727 # Number of instructions fetched each cycle (Total)
54system.cpu.fetch.rateDist::mean 1.635918 # Number of instructions fetched each cycle (Total)
55system.cpu.fetch.rateDist::stdev 3.075272 # Number of instructions fetched each cycle (Total)
| 53system.cpu.fetch.rateDist::samples 17679 # Number of instructions fetched each cycle (Total)
54system.cpu.fetch.rateDist::mean 1.502687 # Number of instructions fetched each cycle (Total)
55system.cpu.fetch.rateDist::stdev 2.975668 # Number of instructions fetched each cycle (Total)
|
56system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
| 56system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
57system.cpu.fetch.rateDist::0 12659 75.68% 75.68% # Number of instructions fetched each cycle (Total)
58system.cpu.fetch.rateDist::1 177 1.06% 76.74% # Number of instructions fetched each cycle (Total)
59system.cpu.fetch.rateDist::2 166 0.99% 77.73% # Number of instructions fetched each cycle (Total)
60system.cpu.fetch.rateDist::3 214 1.28% 79.01% # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::4 171 1.02% 80.03% # Number of instructions fetched each cycle (Total)
62system.cpu.fetch.rateDist::5 175 1.05% 81.08% # Number of instructions fetched each cycle (Total)
63system.cpu.fetch.rateDist::6 250 1.49% 82.57% # Number of instructions fetched each cycle (Total)
64system.cpu.fetch.rateDist::7 166 0.99% 83.57% # Number of instructions fetched each cycle (Total)
65system.cpu.fetch.rateDist::8 2749 16.43% 100.00% # Number of instructions fetched each cycle (Total)
| 57system.cpu.fetch.rateDist::0 13710 77.55% 77.55% # Number of instructions fetched each cycle (Total)
58system.cpu.fetch.rateDist::1 177 1.00% 78.55% # Number of instructions fetched each cycle (Total)
59system.cpu.fetch.rateDist::2 164 0.93% 79.48% # Number of instructions fetched each cycle (Total)
60system.cpu.fetch.rateDist::3 211 1.19% 80.67% # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::4 170 0.96% 81.63% # Number of instructions fetched each cycle (Total)
62system.cpu.fetch.rateDist::5 182 1.03% 82.66% # Number of instructions fetched each cycle (Total)
63system.cpu.fetch.rateDist::6 260 1.47% 84.13% # Number of instructions fetched each cycle (Total)
64system.cpu.fetch.rateDist::7 162 0.92% 85.05% # Number of instructions fetched each cycle (Total)
65system.cpu.fetch.rateDist::8 2643 14.95% 100.00% # Number of instructions fetched each cycle (Total)
|
66system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
67system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
68system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
| 66system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
67system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
68system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
69system.cpu.fetch.rateDist::total 16727 # Number of instructions fetched each cycle (Total)
70system.cpu.fetch.branchRate 0.131410 # Number of branch fetches per cycle
71system.cpu.fetch.rate 0.631635 # Number of inst fetches per cycle
72system.cpu.decode.IdleCycles 7836 # Number of cycles decode is idle
73system.cpu.decode.BlockedCycles 3109 # Number of cycles decode is blocked
74system.cpu.decode.RunCycles 3749 # Number of cycles decode is running
75system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking
76system.cpu.decode.SquashCycles 1905 # Number of cycles decode is squashing
77system.cpu.decode.DecodedInsts 26025 # Number of instructions handled by decode
78system.cpu.rename.SquashCycles 1905 # Number of cycles rename is squashing
79system.cpu.rename.IdleCycles 8180 # Number of cycles rename is idle
80system.cpu.rename.BlockCycles 1960 # Number of cycles rename is blocking
81system.cpu.rename.serializeStallCycles 442 # count of cycles rename stalled for serializing inst
82system.cpu.rename.RunCycles 3522 # Number of cycles rename is running
83system.cpu.rename.UnblockCycles 718 # Number of cycles rename is unblocking
84system.cpu.rename.RenamedInsts 24463 # Number of instructions processed by rename
| 69system.cpu.fetch.rateDist::total 17679 # Number of instructions fetched each cycle (Total)
70system.cpu.fetch.branchRate 0.122037 # Number of branch fetches per cycle
71system.cpu.fetch.rate 0.585035 # Number of inst fetches per cycle
72system.cpu.decode.IdleCycles 8588 # Number of cycles decode is idle
73system.cpu.decode.BlockedCycles 3390 # Number of cycles decode is blocked
74system.cpu.decode.RunCycles 3692 # Number of cycles decode is running
75system.cpu.decode.UnblockCycles 127 # Number of cycles decode is unblocking
76system.cpu.decode.SquashCycles 1882 # Number of cycles decode is squashing
77system.cpu.decode.DecodedInsts 25327 # Number of instructions handled by decode
78system.cpu.rename.SquashCycles 1882 # Number of cycles rename is squashing
79system.cpu.rename.IdleCycles 8910 # Number of cycles rename is idle
80system.cpu.rename.BlockCycles 2031 # Number of cycles rename is blocking
81system.cpu.rename.serializeStallCycles 505 # count of cycles rename stalled for serializing inst
82system.cpu.rename.RunCycles 3461 # Number of cycles rename is running
83system.cpu.rename.UnblockCycles 890 # Number of cycles rename is unblocking
84system.cpu.rename.RenamedInsts 23802 # Number of instructions processed by rename
|
85system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
| 85system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
|
86system.cpu.rename.IQFullEvents 50 # Number of times rename has blocked due to IQ full
87system.cpu.rename.LSQFullEvents 591 # Number of times rename has blocked due to LSQ full
| 86system.cpu.rename.IQFullEvents 47 # Number of times rename has blocked due to IQ full
87system.cpu.rename.LSQFullEvents 747 # Number of times rename has blocked due to LSQ full
|
88system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
| 88system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
|
89system.cpu.rename.RenamedOperands 35223 # Number of destination operands rename has renamed
90system.cpu.rename.RenameLookups 70488 # Number of register rename lookups that rename has made
91system.cpu.rename.int_rename_lookups 70472 # Number of integer rename lookups
| 89system.cpu.rename.RenamedOperands 34224 # Number of destination operands rename has renamed
90system.cpu.rename.RenameLookups 68607 # Number of register rename lookups that rename has made
91system.cpu.rename.int_rename_lookups 68591 # Number of integer rename lookups
|
92system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
93system.cpu.rename.CommittedMaps 14707 # Number of HB maps that are committed
| 92system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
93system.cpu.rename.CommittedMaps 14707 # Number of HB maps that are committed
|
94system.cpu.rename.UndoneMaps 20516 # Number of HB maps that are undone due to squashing
95system.cpu.rename.serializingInsts 33 # count of serializing insts renamed
96system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed
97system.cpu.rename.skidInsts 1918 # count of insts added to the skid buffer
98system.cpu.memDep0.insertedLoads 2376 # Number of loads inserted to the mem dependence unit.
99system.cpu.memDep0.insertedStores 1791 # Number of stores inserted to the mem dependence unit.
| 94system.cpu.rename.UndoneMaps 19517 # Number of HB maps that are undone due to squashing
95system.cpu.rename.serializingInsts 35 # count of serializing insts renamed
96system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed
97system.cpu.rename.skidInsts 1875 # count of insts added to the skid buffer
98system.cpu.memDep0.insertedLoads 2306 # Number of loads inserted to the mem dependence unit.
99system.cpu.memDep0.insertedStores 1775 # Number of stores inserted to the mem dependence unit.
|
100system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
101system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
| 100system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
101system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
|
102system.cpu.iq.iqInstsAdded 21692 # Number of instructions added to the IQ (excludes non-spec)
103system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ
104system.cpu.iq.iqInstsIssued 17854 # Number of instructions issued
105system.cpu.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued
106system.cpu.iq.iqSquashedInstsExamined 11255 # Number of squashed instructions iterated over during squash; mainly for profiling
107system.cpu.iq.iqSquashedOperandsExamined 20549 # Number of squashed operands that are examined and possibly removed from graph
108system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed
109system.cpu.iq.issued_per_cycle::samples 16727 # Number of insts issued each cycle
110system.cpu.iq.issued_per_cycle::mean 1.067376 # Number of insts issued each cycle
111system.cpu.iq.issued_per_cycle::stdev 1.893384 # Number of insts issued each cycle
| 102system.cpu.iq.iqInstsAdded 21232 # Number of instructions added to the IQ (excludes non-spec)
103system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ
104system.cpu.iq.iqInstsIssued 17582 # Number of instructions issued
105system.cpu.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued
106system.cpu.iq.iqSquashedInstsExamined 10865 # Number of squashed instructions iterated over during squash; mainly for profiling
107system.cpu.iq.iqSquashedOperandsExamined 19620 # Number of squashed operands that are examined and possibly removed from graph
108system.cpu.iq.iqSquashedNonSpecRemoved 27 # Number of squashed non-spec instructions that were removed
109system.cpu.iq.issued_per_cycle::samples 17679 # Number of insts issued each cycle
110system.cpu.iq.issued_per_cycle::mean 0.994513 # Number of insts issued each cycle
111system.cpu.iq.issued_per_cycle::stdev 1.826049 # Number of insts issued each cycle
|
112system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
| 112system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
113system.cpu.iq.issued_per_cycle::0 11276 67.41% 67.41% # Number of insts issued each cycle
114system.cpu.iq.issued_per_cycle::1 1383 8.27% 75.68% # Number of insts issued each cycle
115system.cpu.iq.issued_per_cycle::2 1035 6.19% 81.87% # Number of insts issued each cycle
116system.cpu.iq.issued_per_cycle::3 667 3.99% 85.86% # Number of insts issued each cycle
117system.cpu.iq.issued_per_cycle::4 692 4.14% 89.99% # Number of insts issued each cycle
118system.cpu.iq.issued_per_cycle::5 723 4.32% 94.31% # Number of insts issued each cycle
119system.cpu.iq.issued_per_cycle::6 673 4.02% 98.34% # Number of insts issued each cycle
120system.cpu.iq.issued_per_cycle::7 245 1.46% 99.80% # Number of insts issued each cycle
121system.cpu.iq.issued_per_cycle::8 33 0.20% 100.00% # Number of insts issued each cycle
| 113system.cpu.iq.issued_per_cycle::0 12114 68.52% 68.52% # Number of insts issued each cycle
114system.cpu.iq.issued_per_cycle::1 1582 8.95% 77.47% # Number of insts issued each cycle
115system.cpu.iq.issued_per_cycle::2 1012 5.72% 83.19% # Number of insts issued each cycle
116system.cpu.iq.issued_per_cycle::3 689 3.90% 87.09% # Number of insts issued each cycle
117system.cpu.iq.issued_per_cycle::4 696 3.94% 91.03% # Number of insts issued each cycle
118system.cpu.iq.issued_per_cycle::5 692 3.91% 94.94% # Number of insts issued each cycle
119system.cpu.iq.issued_per_cycle::6 627 3.55% 98.49% # Number of insts issued each cycle
120system.cpu.iq.issued_per_cycle::7 233 1.32% 99.81% # Number of insts issued each cycle
121system.cpu.iq.issued_per_cycle::8 34 0.19% 100.00% # Number of insts issued each cycle
|
122system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
123system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
124system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
| 122system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
123system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
124system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
125system.cpu.iq.issued_per_cycle::total 16727 # Number of insts issued each cycle
| 125system.cpu.iq.issued_per_cycle::total 17679 # Number of insts issued each cycle
|
126system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
| 126system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
127system.cpu.iq.fu_full::IntAlu 140 73.30% 73.30% # attempts to use FU when none available
128system.cpu.iq.fu_full::IntMult 0 0.00% 73.30% # attempts to use FU when none available
129system.cpu.iq.fu_full::IntDiv 0 0.00% 73.30% # attempts to use FU when none available
130system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.30% # attempts to use FU when none available
131system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.30% # attempts to use FU when none available
132system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.30% # attempts to use FU when none available
133system.cpu.iq.fu_full::FloatMult 0 0.00% 73.30% # attempts to use FU when none available
134system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.30% # attempts to use FU when none available
135system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.30% # attempts to use FU when none available
136system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.30% # attempts to use FU when none available
137system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.30% # attempts to use FU when none available
138system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.30% # attempts to use FU when none available
139system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.30% # attempts to use FU when none available
140system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.30% # attempts to use FU when none available
141system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.30% # attempts to use FU when none available
142system.cpu.iq.fu_full::SimdMult 0 0.00% 73.30% # attempts to use FU when none available
143system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.30% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdShift 0 0.00% 73.30% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.30% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.30% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.30% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.30% # attempts to use FU when none available
149system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.30% # attempts to use FU when none available
150system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.30% # attempts to use FU when none available
151system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.30% # attempts to use FU when none available
152system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.30% # attempts to use FU when none available
153system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.30% # attempts to use FU when none available
154system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.30% # attempts to use FU when none available
155system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.30% # attempts to use FU when none available
156system.cpu.iq.fu_full::MemRead 30 15.71% 89.01% # attempts to use FU when none available
157system.cpu.iq.fu_full::MemWrite 21 10.99% 100.00% # attempts to use FU when none available
| 127system.cpu.iq.fu_full::IntAlu 133 73.08% 73.08% # attempts to use FU when none available
128system.cpu.iq.fu_full::IntMult 0 0.00% 73.08% # attempts to use FU when none available
129system.cpu.iq.fu_full::IntDiv 0 0.00% 73.08% # attempts to use FU when none available
130system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.08% # attempts to use FU when none available
131system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.08% # attempts to use FU when none available
132system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.08% # attempts to use FU when none available
133system.cpu.iq.fu_full::FloatMult 0 0.00% 73.08% # attempts to use FU when none available
134system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.08% # attempts to use FU when none available
135system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.08% # attempts to use FU when none available
136system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.08% # attempts to use FU when none available
137system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.08% # attempts to use FU when none available
138system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.08% # attempts to use FU when none available
139system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.08% # attempts to use FU when none available
140system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.08% # attempts to use FU when none available
141system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.08% # attempts to use FU when none available
142system.cpu.iq.fu_full::SimdMult 0 0.00% 73.08% # attempts to use FU when none available
143system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.08% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdShift 0 0.00% 73.08% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.08% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.08% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.08% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.08% # attempts to use FU when none available
149system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.08% # attempts to use FU when none available
150system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.08% # attempts to use FU when none available
151system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.08% # attempts to use FU when none available
152system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.08% # attempts to use FU when none available
153system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.08% # attempts to use FU when none available
154system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.08% # attempts to use FU when none available
155system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.08% # attempts to use FU when none available
156system.cpu.iq.fu_full::MemRead 29 15.93% 89.01% # attempts to use FU when none available
157system.cpu.iq.fu_full::MemWrite 20 10.99% 100.00% # attempts to use FU when none available
|
158system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
159system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
160system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
| 158system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
159system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
160system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
|
161system.cpu.iq.FU_type_0::IntAlu 14397 80.64% 80.66% # Type of FU issued
162system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.66% # Type of FU issued
163system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.66% # Type of FU issued
164system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.66% # Type of FU issued
165system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.66% # Type of FU issued
166system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.66% # Type of FU issued
167system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.66% # Type of FU issued
168system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.66% # Type of FU issued
169system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.66% # Type of FU issued
170system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.66% # Type of FU issued
171system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.66% # Type of FU issued
172system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.66% # Type of FU issued
173system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.66% # Type of FU issued
174system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.66% # Type of FU issued
175system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.66% # Type of FU issued
176system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.66% # Type of FU issued
177system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.66% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.66% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.66% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.66% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.66% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.66% # Type of FU issued
183system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.66% # Type of FU issued
184system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.66% # Type of FU issued
185system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.66% # Type of FU issued
186system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.66% # Type of FU issued
187system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.66% # Type of FU issued
188system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.66% # Type of FU issued
189system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.66% # Type of FU issued
190system.cpu.iq.FU_type_0::MemRead 1982 11.10% 91.76% # Type of FU issued
191system.cpu.iq.FU_type_0::MemWrite 1471 8.24% 100.00% # Type of FU issued
| 161system.cpu.iq.FU_type_0::IntAlu 14185 80.68% 80.70% # Type of FU issued
162system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.70% # Type of FU issued
163system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.70% # Type of FU issued
164system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.70% # Type of FU issued
165system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.70% # Type of FU issued
166system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.70% # Type of FU issued
167system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.70% # Type of FU issued
168system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.70% # Type of FU issued
169system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.70% # Type of FU issued
170system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.70% # Type of FU issued
171system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.70% # Type of FU issued
172system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.70% # Type of FU issued
173system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.70% # Type of FU issued
174system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.70% # Type of FU issued
175system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.70% # Type of FU issued
176system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.70% # Type of FU issued
177system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.70% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.70% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.70% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.70% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.70% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.70% # Type of FU issued
183system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.70% # Type of FU issued
184system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.70% # Type of FU issued
185system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.70% # Type of FU issued
186system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.70% # Type of FU issued
187system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.70% # Type of FU issued
188system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.70% # Type of FU issued
189system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.70% # Type of FU issued
190system.cpu.iq.FU_type_0::MemRead 1924 10.94% 91.64% # Type of FU issued
191system.cpu.iq.FU_type_0::MemWrite 1469 8.36% 100.00% # Type of FU issued
|
192system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
193system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
| 192system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
193system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
194system.cpu.iq.FU_type_0::total 17854 # Type of FU issued
195system.cpu.iq.rate 0.731811 # Inst issue rate
196system.cpu.iq.fu_busy_cnt 191 # FU busy when requested
197system.cpu.iq.fu_busy_rate 0.010698 # FU busy rate (busy events/executed inst)
198system.cpu.iq.int_inst_queue_reads 52700 # Number of integer instruction queue reads
199system.cpu.iq.int_inst_queue_writes 32991 # Number of integer instruction queue writes
200system.cpu.iq.int_inst_queue_wakeup_accesses 16402 # Number of integer instruction queue wakeup accesses
| 194system.cpu.iq.FU_type_0::total 17582 # Type of FU issued
195system.cpu.iq.rate 0.686609 # Inst issue rate
196system.cpu.iq.fu_busy_cnt 182 # FU busy when requested
197system.cpu.iq.fu_busy_rate 0.010351 # FU busy rate (busy events/executed inst)
198system.cpu.iq.int_inst_queue_reads 53109 # Number of integer instruction queue reads
199system.cpu.iq.int_inst_queue_writes 32144 # Number of integer instruction queue writes
200system.cpu.iq.int_inst_queue_wakeup_accesses 16183 # Number of integer instruction queue wakeup accesses
|
201system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
202system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
203system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
| 201system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
202system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
203system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
|
204system.cpu.iq.int_alu_accesses 18037 # Number of integer alu accesses
| 204system.cpu.iq.int_alu_accesses 17756 # Number of integer alu accesses
|
205system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
| 205system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
|
206system.cpu.iew.lsq.thread0.forwLoads 151 # Number of loads that had data forwarded from stores
| 206system.cpu.iew.lsq.thread0.forwLoads 148 # Number of loads that had data forwarded from stores
|
207system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
| 207system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
208system.cpu.iew.lsq.thread0.squashedLoads 1320 # Number of loads squashed
209system.cpu.iew.lsq.thread0.ignoredResponses 20 # Number of memory responses ignored because the instruction is squashed
| 208system.cpu.iew.lsq.thread0.squashedLoads 1250 # Number of loads squashed
209system.cpu.iew.lsq.thread0.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed
|
210system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations
| 210system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations
|
211system.cpu.iew.lsq.thread0.squashedStores 857 # Number of stores squashed
| 211system.cpu.iew.lsq.thread0.squashedStores 841 # Number of stores squashed
|
212system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
213system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
214system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
215system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
216system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
| 212system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
213system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
214system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
215system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
216system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
217system.cpu.iew.iewSquashCycles 1905 # Number of cycles IEW is squashing
218system.cpu.iew.iewBlockCycles 1329 # Number of cycles IEW is blocking
219system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking
220system.cpu.iew.iewDispatchedInsts 21730 # Number of instructions dispatched to IQ
221system.cpu.iew.iewDispSquashedInsts 24 # Number of squashed instructions skipped by dispatch
222system.cpu.iew.iewDispLoadInsts 2376 # Number of dispatched load instructions
223system.cpu.iew.iewDispStoreInsts 1791 # Number of dispatched store instructions
224system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions
225system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
| 217system.cpu.iew.iewSquashCycles 1882 # Number of cycles IEW is squashing
218system.cpu.iew.iewBlockCycles 1425 # Number of cycles IEW is blocking
219system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking
220system.cpu.iew.iewDispatchedInsts 21272 # Number of instructions dispatched to IQ
221system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch
222system.cpu.iew.iewDispLoadInsts 2306 # Number of dispatched load instructions
223system.cpu.iew.iewDispStoreInsts 1775 # Number of dispatched store instructions
224system.cpu.iew.iewDispNonSpecInsts 36 # Number of dispatched non-speculative instructions
225system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
|
226system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
227system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations
| 226system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
227system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations
|
228system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly
229system.cpu.iew.predictedNotTakenIncorrect 631 # Number of branches that were predicted not taken incorrectly
230system.cpu.iew.branchMispredicts 690 # Number of branch mispredicts detected at execute
231system.cpu.iew.iewExecutedInsts 16824 # Number of executed instructions
232system.cpu.iew.iewExecLoadInsts 1844 # Number of load instructions executed
233system.cpu.iew.iewExecSquashedInsts 1030 # Number of squashed instructions skipped in execute
| 228system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly
229system.cpu.iew.predictedNotTakenIncorrect 640 # Number of branches that were predicted not taken incorrectly
230system.cpu.iew.branchMispredicts 705 # Number of branch mispredicts detected at execute
231system.cpu.iew.iewExecutedInsts 16602 # Number of executed instructions
232system.cpu.iew.iewExecLoadInsts 1794 # Number of load instructions executed
233system.cpu.iew.iewExecSquashedInsts 980 # Number of squashed instructions skipped in execute
|
234system.cpu.iew.exec_swp 0 # number of swp insts executed
235system.cpu.iew.exec_nop 0 # number of nop insts executed
| 234system.cpu.iew.exec_swp 0 # number of swp insts executed
235system.cpu.iew.exec_nop 0 # number of nop insts executed
|
236system.cpu.iew.exec_refs 3203 # number of memory reference insts executed
237system.cpu.iew.exec_branches 1645 # Number of branches executed
238system.cpu.iew.exec_stores 1359 # Number of stores executed
239system.cpu.iew.exec_rate 0.689593 # Inst execution rate
240system.cpu.iew.wb_sent 16593 # cumulative count of insts sent to commit
241system.cpu.iew.wb_count 16406 # cumulative count of insts written-back
242system.cpu.iew.wb_producers 10679 # num instructions producing a value
243system.cpu.iew.wb_consumers 24448 # num instructions consuming a value
| 236system.cpu.iew.exec_refs 3144 # number of memory reference insts executed
237system.cpu.iew.exec_branches 1642 # Number of branches executed
238system.cpu.iew.exec_stores 1350 # Number of stores executed
239system.cpu.iew.exec_rate 0.648338 # Inst execution rate
240system.cpu.iew.wb_sent 16384 # cumulative count of insts sent to commit
241system.cpu.iew.wb_count 16187 # cumulative count of insts written-back
242system.cpu.iew.wb_producers 10480 # num instructions producing a value
243system.cpu.iew.wb_consumers 24095 # num instructions consuming a value
|
244system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
| 244system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
245system.cpu.iew.wb_rate 0.672460 # insts written-back per cycle
246system.cpu.iew.wb_fanout 0.436805 # average fanout of values written-back
| 245system.cpu.iew.wb_rate 0.632132 # insts written-back per cycle
246system.cpu.iew.wb_fanout 0.434945 # average fanout of values written-back
|
247system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
248system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions
249system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions
| 247system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
248system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions
249system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions
|
250system.cpu.commit.commitSquashedInsts 11920 # The number of squashed insts skipped by commit
| 250system.cpu.commit.commitSquashedInsts 11462 # The number of squashed insts skipped by commit
|
251system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
| 251system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
|
252system.cpu.commit.branchMispredicts 571 # The number of times a branch was mispredicted
253system.cpu.commit.committed_per_cycle::samples 14822 # Number of insts commited each cycle
254system.cpu.commit.committed_per_cycle::mean 0.661787 # Number of insts commited each cycle
255system.cpu.commit.committed_per_cycle::stdev 1.507902 # Number of insts commited each cycle
| 252system.cpu.commit.branchMispredicts 589 # The number of times a branch was mispredicted
253system.cpu.commit.committed_per_cycle::samples 15797 # Number of insts commited each cycle
254system.cpu.commit.committed_per_cycle::mean 0.620941 # Number of insts commited each cycle
255system.cpu.commit.committed_per_cycle::stdev 1.463366 # Number of insts commited each cycle
|
256system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
| 256system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
257system.cpu.commit.committed_per_cycle::0 11181 75.44% 75.44% # Number of insts commited each cycle
258system.cpu.commit.committed_per_cycle::1 1365 9.21% 84.64% # Number of insts commited each cycle
259system.cpu.commit.committed_per_cycle::2 653 4.41% 89.05% # Number of insts commited each cycle
260system.cpu.commit.committed_per_cycle::3 730 4.93% 93.98% # Number of insts commited each cycle
261system.cpu.commit.committed_per_cycle::4 365 2.46% 96.44% # Number of insts commited each cycle
262system.cpu.commit.committed_per_cycle::5 129 0.87% 97.31% # Number of insts commited each cycle
263system.cpu.commit.committed_per_cycle::6 139 0.94% 98.25% # Number of insts commited each cycle
264system.cpu.commit.committed_per_cycle::7 71 0.48% 98.72% # Number of insts commited each cycle
265system.cpu.commit.committed_per_cycle::8 189 1.28% 100.00% # Number of insts commited each cycle
| 257system.cpu.commit.committed_per_cycle::0 12065 76.38% 76.38% # Number of insts commited each cycle
258system.cpu.commit.committed_per_cycle::1 1534 9.71% 86.09% # Number of insts commited each cycle
259system.cpu.commit.committed_per_cycle::2 576 3.65% 89.73% # Number of insts commited each cycle
260system.cpu.commit.committed_per_cycle::3 731 4.63% 94.36% # Number of insts commited each cycle
261system.cpu.commit.committed_per_cycle::4 367 2.32% 96.68% # Number of insts commited each cycle
262system.cpu.commit.committed_per_cycle::5 129 0.82% 97.50% # Number of insts commited each cycle
263system.cpu.commit.committed_per_cycle::6 134 0.85% 98.35% # Number of insts commited each cycle
264system.cpu.commit.committed_per_cycle::7 75 0.47% 98.82% # Number of insts commited each cycle
265system.cpu.commit.committed_per_cycle::8 186 1.18% 100.00% # Number of insts commited each cycle
|
266system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
267system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
268system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
| 266system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
267system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
268system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
269system.cpu.commit.committed_per_cycle::total 14822 # Number of insts commited each cycle
| 269system.cpu.commit.committed_per_cycle::total 15797 # Number of insts commited each cycle
|
270system.cpu.commit.committedInsts 5416 # Number of instructions committed
271system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed
272system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
273system.cpu.commit.refs 1990 # Number of memory references committed
274system.cpu.commit.loads 1056 # Number of loads committed
275system.cpu.commit.membars 0 # Number of memory barriers committed
276system.cpu.commit.branches 1214 # Number of branches committed
277system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
278system.cpu.commit.int_insts 9714 # Number of committed integer instructions.
279system.cpu.commit.function_calls 0 # Number of function calls committed.
| 270system.cpu.commit.committedInsts 5416 # Number of instructions committed
271system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed
272system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
273system.cpu.commit.refs 1990 # Number of memory references committed
274system.cpu.commit.loads 1056 # Number of loads committed
275system.cpu.commit.membars 0 # Number of memory barriers committed
276system.cpu.commit.branches 1214 # Number of branches committed
277system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
278system.cpu.commit.int_insts 9714 # Number of committed integer instructions.
279system.cpu.commit.function_calls 0 # Number of function calls committed.
|
280system.cpu.commit.bw_lim_events 189 # number cycles where commit BW limit reached
| 280system.cpu.commit.bw_lim_events 186 # number cycles where commit BW limit reached
|
281system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
| 281system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
282system.cpu.rob.rob_reads 36362 # The number of ROB reads
283system.cpu.rob.rob_writes 45397 # The number of ROB writes
284system.cpu.timesIdled 150 # Number of times that the entire CPU went into an idle state and unscheduled itself
285system.cpu.idleCycles 7670 # Total number of cycles that the CPU has spent unscheduled due to idling
| 282system.cpu.rob.rob_reads 36882 # The number of ROB reads
283system.cpu.rob.rob_writes 44457 # The number of ROB writes
284system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself
285system.cpu.idleCycles 7928 # Total number of cycles that the CPU has spent unscheduled due to idling
|
286system.cpu.committedInsts 5416 # Number of Instructions Simulated
287system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated
288system.cpu.committedInsts_total 5416 # Number of Instructions Simulated
| 286system.cpu.committedInsts 5416 # Number of Instructions Simulated
287system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated
288system.cpu.committedInsts_total 5416 # Number of Instructions Simulated
|
289system.cpu.cpi 4.504616 # CPI: Cycles Per Instruction
290system.cpu.cpi_total 4.504616 # CPI: Total CPI of All Threads
291system.cpu.ipc 0.221995 # IPC: Instructions Per Cycle
292system.cpu.ipc_total 0.221995 # IPC: Total IPC of All Threads
293system.cpu.int_regfile_reads 35460 # number of integer regfile reads
294system.cpu.int_regfile_writes 22063 # number of integer regfile writes
| 289system.cpu.cpi 4.728028 # CPI: Cycles Per Instruction
290system.cpu.cpi_total 4.728028 # CPI: Total CPI of All Threads
291system.cpu.ipc 0.211505 # IPC: Instructions Per Cycle
292system.cpu.ipc_total 0.211505 # IPC: Total IPC of All Threads
293system.cpu.int_regfile_reads 35136 # number of integer regfile reads
294system.cpu.int_regfile_writes 21832 # number of integer regfile writes
|
295system.cpu.fp_regfile_reads 4 # number of floating regfile reads
| 295system.cpu.fp_regfile_reads 4 # number of floating regfile reads
|
296system.cpu.misc_regfile_reads 7402 # number of misc regfile reads
| 296system.cpu.misc_regfile_reads 7303 # number of misc regfile reads
|
297system.cpu.icache.replacements 0 # number of replacements
| 297system.cpu.icache.replacements 0 # number of replacements
|
298system.cpu.icache.tagsinuse 145.636183 # Cycle average of tags in use
299system.cpu.icache.total_refs 1561 # Total number of references to valid blocks.
300system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks.
301system.cpu.icache.avg_refs 5.134868 # Average number of references to valid blocks.
| 298system.cpu.icache.tagsinuse 144.987593 # Cycle average of tags in use
299system.cpu.icache.total_refs 1569 # Total number of references to valid blocks.
300system.cpu.icache.sampled_refs 302 # Sample count of references to valid blocks.
301system.cpu.icache.avg_refs 5.195364 # Average number of references to valid blocks.
|
302system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 302system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
303system.cpu.icache.occ_blocks::cpu.inst 145.636183 # Average occupied blocks per requestor
304system.cpu.icache.occ_percent::cpu.inst 0.071111 # Average percentage of cache occupancy
305system.cpu.icache.occ_percent::total 0.071111 # Average percentage of cache occupancy
306system.cpu.icache.ReadReq_hits::cpu.inst 1561 # number of ReadReq hits
307system.cpu.icache.ReadReq_hits::total 1561 # number of ReadReq hits
308system.cpu.icache.demand_hits::cpu.inst 1561 # number of demand (read+write) hits
309system.cpu.icache.demand_hits::total 1561 # number of demand (read+write) hits
310system.cpu.icache.overall_hits::cpu.inst 1561 # number of overall hits
311system.cpu.icache.overall_hits::total 1561 # number of overall hits
312system.cpu.icache.ReadReq_misses::cpu.inst 390 # number of ReadReq misses
313system.cpu.icache.ReadReq_misses::total 390 # number of ReadReq misses
314system.cpu.icache.demand_misses::cpu.inst 390 # number of demand (read+write) misses
315system.cpu.icache.demand_misses::total 390 # number of demand (read+write) misses
316system.cpu.icache.overall_misses::cpu.inst 390 # number of overall misses
317system.cpu.icache.overall_misses::total 390 # number of overall misses
318system.cpu.icache.ReadReq_miss_latency::cpu.inst 13866500 # number of ReadReq miss cycles
319system.cpu.icache.ReadReq_miss_latency::total 13866500 # number of ReadReq miss cycles
320system.cpu.icache.demand_miss_latency::cpu.inst 13866500 # number of demand (read+write) miss cycles
321system.cpu.icache.demand_miss_latency::total 13866500 # number of demand (read+write) miss cycles
322system.cpu.icache.overall_miss_latency::cpu.inst 13866500 # number of overall miss cycles
323system.cpu.icache.overall_miss_latency::total 13866500 # number of overall miss cycles
324system.cpu.icache.ReadReq_accesses::cpu.inst 1951 # number of ReadReq accesses(hits+misses)
325system.cpu.icache.ReadReq_accesses::total 1951 # number of ReadReq accesses(hits+misses)
326system.cpu.icache.demand_accesses::cpu.inst 1951 # number of demand (read+write) accesses
327system.cpu.icache.demand_accesses::total 1951 # number of demand (read+write) accesses
328system.cpu.icache.overall_accesses::cpu.inst 1951 # number of overall (read+write) accesses
329system.cpu.icache.overall_accesses::total 1951 # number of overall (read+write) accesses
330system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199897 # miss rate for ReadReq accesses
331system.cpu.icache.ReadReq_miss_rate::total 0.199897 # miss rate for ReadReq accesses
332system.cpu.icache.demand_miss_rate::cpu.inst 0.199897 # miss rate for demand accesses
333system.cpu.icache.demand_miss_rate::total 0.199897 # miss rate for demand accesses
334system.cpu.icache.overall_miss_rate::cpu.inst 0.199897 # miss rate for overall accesses
335system.cpu.icache.overall_miss_rate::total 0.199897 # miss rate for overall accesses
336system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35555.128205 # average ReadReq miss latency
337system.cpu.icache.ReadReq_avg_miss_latency::total 35555.128205 # average ReadReq miss latency
338system.cpu.icache.demand_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency
339system.cpu.icache.demand_avg_miss_latency::total 35555.128205 # average overall miss latency
340system.cpu.icache.overall_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency
341system.cpu.icache.overall_avg_miss_latency::total 35555.128205 # average overall miss latency
| 303system.cpu.icache.occ_blocks::cpu.inst 144.987593 # Average occupied blocks per requestor
304system.cpu.icache.occ_percent::cpu.inst 0.070795 # Average percentage of cache occupancy
305system.cpu.icache.occ_percent::total 0.070795 # Average percentage of cache occupancy
306system.cpu.icache.ReadReq_hits::cpu.inst 1569 # number of ReadReq hits
307system.cpu.icache.ReadReq_hits::total 1569 # number of ReadReq hits
308system.cpu.icache.demand_hits::cpu.inst 1569 # number of demand (read+write) hits
309system.cpu.icache.demand_hits::total 1569 # number of demand (read+write) hits
310system.cpu.icache.overall_hits::cpu.inst 1569 # number of overall hits
311system.cpu.icache.overall_hits::total 1569 # number of overall hits
312system.cpu.icache.ReadReq_misses::cpu.inst 388 # number of ReadReq misses
313system.cpu.icache.ReadReq_misses::total 388 # number of ReadReq misses
314system.cpu.icache.demand_misses::cpu.inst 388 # number of demand (read+write) misses
315system.cpu.icache.demand_misses::total 388 # number of demand (read+write) misses
316system.cpu.icache.overall_misses::cpu.inst 388 # number of overall misses
317system.cpu.icache.overall_misses::total 388 # number of overall misses
318system.cpu.icache.ReadReq_miss_latency::cpu.inst 14367500 # number of ReadReq miss cycles
319system.cpu.icache.ReadReq_miss_latency::total 14367500 # number of ReadReq miss cycles
320system.cpu.icache.demand_miss_latency::cpu.inst 14367500 # number of demand (read+write) miss cycles
321system.cpu.icache.demand_miss_latency::total 14367500 # number of demand (read+write) miss cycles
322system.cpu.icache.overall_miss_latency::cpu.inst 14367500 # number of overall miss cycles
323system.cpu.icache.overall_miss_latency::total 14367500 # number of overall miss cycles
324system.cpu.icache.ReadReq_accesses::cpu.inst 1957 # number of ReadReq accesses(hits+misses)
325system.cpu.icache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses)
326system.cpu.icache.demand_accesses::cpu.inst 1957 # number of demand (read+write) accesses
327system.cpu.icache.demand_accesses::total 1957 # number of demand (read+write) accesses
328system.cpu.icache.overall_accesses::cpu.inst 1957 # number of overall (read+write) accesses
329system.cpu.icache.overall_accesses::total 1957 # number of overall (read+write) accesses
330system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.198263 # miss rate for ReadReq accesses
331system.cpu.icache.ReadReq_miss_rate::total 0.198263 # miss rate for ReadReq accesses
332system.cpu.icache.demand_miss_rate::cpu.inst 0.198263 # miss rate for demand accesses
333system.cpu.icache.demand_miss_rate::total 0.198263 # miss rate for demand accesses
334system.cpu.icache.overall_miss_rate::cpu.inst 0.198263 # miss rate for overall accesses
335system.cpu.icache.overall_miss_rate::total 0.198263 # miss rate for overall accesses
336system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37029.639175 # average ReadReq miss latency
337system.cpu.icache.ReadReq_avg_miss_latency::total 37029.639175 # average ReadReq miss latency
338system.cpu.icache.demand_avg_miss_latency::cpu.inst 37029.639175 # average overall miss latency
339system.cpu.icache.demand_avg_miss_latency::total 37029.639175 # average overall miss latency
340system.cpu.icache.overall_avg_miss_latency::cpu.inst 37029.639175 # average overall miss latency
341system.cpu.icache.overall_avg_miss_latency::total 37029.639175 # average overall miss latency
|
342system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
343system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
344system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
345system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
346system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
347system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
348system.cpu.icache.fast_writes 0 # number of fast writes performed
349system.cpu.icache.cache_copies 0 # number of cache copies performed
350system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits
351system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits
352system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits
353system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits
354system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits
355system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits
| 342system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
343system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
344system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
345system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
346system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
347system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
348system.cpu.icache.fast_writes 0 # number of fast writes performed
349system.cpu.icache.cache_copies 0 # number of cache copies performed
350system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits
351system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits
352system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits
353system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits
354system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits
355system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits
|
356system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses
357system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses
358system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses
359system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses
360system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses
361system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses
362system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10687000 # number of ReadReq MSHR miss cycles
363system.cpu.icache.ReadReq_mshr_miss_latency::total 10687000 # number of ReadReq MSHR miss cycles
364system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10687000 # number of demand (read+write) MSHR miss cycles
365system.cpu.icache.demand_mshr_miss_latency::total 10687000 # number of demand (read+write) MSHR miss cycles
366system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10687000 # number of overall MSHR miss cycles
367system.cpu.icache.overall_mshr_miss_latency::total 10687000 # number of overall MSHR miss cycles
368system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for ReadReq accesses
369system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155818 # mshr miss rate for ReadReq accesses
370system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for demand accesses
371system.cpu.icache.demand_mshr_miss_rate::total 0.155818 # mshr miss rate for demand accesses
372system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for overall accesses
373system.cpu.icache.overall_mshr_miss_rate::total 0.155818 # mshr miss rate for overall accesses
374system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35154.605263 # average ReadReq mshr miss latency
375system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35154.605263 # average ReadReq mshr miss latency
376system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency
377system.cpu.icache.demand_avg_mshr_miss_latency::total 35154.605263 # average overall mshr miss latency
378system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency
379system.cpu.icache.overall_avg_mshr_miss_latency::total 35154.605263 # average overall mshr miss latency
| 356system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
357system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses
358system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
359system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
360system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
361system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
362system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11138000 # number of ReadReq MSHR miss cycles
363system.cpu.icache.ReadReq_mshr_miss_latency::total 11138000 # number of ReadReq MSHR miss cycles
364system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11138000 # number of demand (read+write) MSHR miss cycles
365system.cpu.icache.demand_mshr_miss_latency::total 11138000 # number of demand (read+write) MSHR miss cycles
366system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11138000 # number of overall MSHR miss cycles
367system.cpu.icache.overall_mshr_miss_latency::total 11138000 # number of overall MSHR miss cycles
368system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154318 # mshr miss rate for ReadReq accesses
369system.cpu.icache.ReadReq_mshr_miss_rate::total 0.154318 # mshr miss rate for ReadReq accesses
370system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154318 # mshr miss rate for demand accesses
371system.cpu.icache.demand_mshr_miss_rate::total 0.154318 # mshr miss rate for demand accesses
372system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154318 # mshr miss rate for overall accesses
373system.cpu.icache.overall_mshr_miss_rate::total 0.154318 # mshr miss rate for overall accesses
374system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36880.794702 # average ReadReq mshr miss latency
375system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36880.794702 # average ReadReq mshr miss latency
376system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36880.794702 # average overall mshr miss latency
377system.cpu.icache.demand_avg_mshr_miss_latency::total 36880.794702 # average overall mshr miss latency
378system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36880.794702 # average overall mshr miss latency
379system.cpu.icache.overall_avg_mshr_miss_latency::total 36880.794702 # average overall mshr miss latency
|
380system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
381system.cpu.dcache.replacements 0 # number of replacements
| 380system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
381system.cpu.dcache.replacements 0 # number of replacements
|
382system.cpu.dcache.tagsinuse 84.751522 # Cycle average of tags in use
383system.cpu.dcache.total_refs 2365 # Total number of references to valid blocks.
384system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks.
385system.cpu.dcache.avg_refs 15.979730 # Average number of references to valid blocks.
| 382system.cpu.dcache.tagsinuse 83.196834 # Cycle average of tags in use
383system.cpu.dcache.total_refs 2330 # Total number of references to valid blocks.
384system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks.
385system.cpu.dcache.avg_refs 16.180556 # Average number of references to valid blocks.
|
386system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 386system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
387system.cpu.dcache.occ_blocks::cpu.data 84.751522 # Average occupied blocks per requestor
388system.cpu.dcache.occ_percent::cpu.data 0.020691 # Average percentage of cache occupancy
389system.cpu.dcache.occ_percent::total 0.020691 # Average percentage of cache occupancy
390system.cpu.dcache.ReadReq_hits::cpu.data 1507 # number of ReadReq hits
391system.cpu.dcache.ReadReq_hits::total 1507 # number of ReadReq hits
| 387system.cpu.dcache.occ_blocks::cpu.data 83.196834 # Average occupied blocks per requestor
388system.cpu.dcache.occ_percent::cpu.data 0.020312 # Average percentage of cache occupancy
389system.cpu.dcache.occ_percent::total 0.020312 # Average percentage of cache occupancy
390system.cpu.dcache.ReadReq_hits::cpu.data 1472 # number of ReadReq hits
391system.cpu.dcache.ReadReq_hits::total 1472 # number of ReadReq hits
|
392system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
393system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
| 392system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
393system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
|
394system.cpu.dcache.demand_hits::cpu.data 2365 # number of demand (read+write) hits
395system.cpu.dcache.demand_hits::total 2365 # number of demand (read+write) hits
396system.cpu.dcache.overall_hits::cpu.data 2365 # number of overall hits
397system.cpu.dcache.overall_hits::total 2365 # number of overall hits
398system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses
399system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
| 394system.cpu.dcache.demand_hits::cpu.data 2330 # number of demand (read+write) hits
395system.cpu.dcache.demand_hits::total 2330 # number of demand (read+write) hits
396system.cpu.dcache.overall_hits::cpu.data 2330 # number of overall hits
397system.cpu.dcache.overall_hits::total 2330 # number of overall hits
398system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses
399system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses
|
400system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
401system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
| 400system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
401system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
|
402system.cpu.dcache.demand_misses::cpu.data 191 # number of demand (read+write) misses
403system.cpu.dcache.demand_misses::total 191 # number of demand (read+write) misses
404system.cpu.dcache.overall_misses::cpu.data 191 # number of overall misses
405system.cpu.dcache.overall_misses::total 191 # number of overall misses
406system.cpu.dcache.ReadReq_miss_latency::cpu.data 4030500 # number of ReadReq miss cycles
407system.cpu.dcache.ReadReq_miss_latency::total 4030500 # number of ReadReq miss cycles
408system.cpu.dcache.WriteReq_miss_latency::cpu.data 2917500 # number of WriteReq miss cycles
409system.cpu.dcache.WriteReq_miss_latency::total 2917500 # number of WriteReq miss cycles
410system.cpu.dcache.demand_miss_latency::cpu.data 6948000 # number of demand (read+write) miss cycles
411system.cpu.dcache.demand_miss_latency::total 6948000 # number of demand (read+write) miss cycles
412system.cpu.dcache.overall_miss_latency::cpu.data 6948000 # number of overall miss cycles
413system.cpu.dcache.overall_miss_latency::total 6948000 # number of overall miss cycles
414system.cpu.dcache.ReadReq_accesses::cpu.data 1622 # number of ReadReq accesses(hits+misses)
415system.cpu.dcache.ReadReq_accesses::total 1622 # number of ReadReq accesses(hits+misses)
| 402system.cpu.dcache.demand_misses::cpu.data 188 # number of demand (read+write) misses
403system.cpu.dcache.demand_misses::total 188 # number of demand (read+write) misses
404system.cpu.dcache.overall_misses::cpu.data 188 # number of overall misses
405system.cpu.dcache.overall_misses::total 188 # number of overall misses
406system.cpu.dcache.ReadReq_miss_latency::cpu.data 4401500 # number of ReadReq miss cycles
407system.cpu.dcache.ReadReq_miss_latency::total 4401500 # number of ReadReq miss cycles
408system.cpu.dcache.WriteReq_miss_latency::cpu.data 3078500 # number of WriteReq miss cycles
409system.cpu.dcache.WriteReq_miss_latency::total 3078500 # number of WriteReq miss cycles
410system.cpu.dcache.demand_miss_latency::cpu.data 7480000 # number of demand (read+write) miss cycles
411system.cpu.dcache.demand_miss_latency::total 7480000 # number of demand (read+write) miss cycles
412system.cpu.dcache.overall_miss_latency::cpu.data 7480000 # number of overall miss cycles
413system.cpu.dcache.overall_miss_latency::total 7480000 # number of overall miss cycles
414system.cpu.dcache.ReadReq_accesses::cpu.data 1584 # number of ReadReq accesses(hits+misses)
415system.cpu.dcache.ReadReq_accesses::total 1584 # number of ReadReq accesses(hits+misses)
|
416system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
417system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
| 416system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
417system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
|
418system.cpu.dcache.demand_accesses::cpu.data 2556 # number of demand (read+write) accesses
419system.cpu.dcache.demand_accesses::total 2556 # number of demand (read+write) accesses
420system.cpu.dcache.overall_accesses::cpu.data 2556 # number of overall (read+write) accesses
421system.cpu.dcache.overall_accesses::total 2556 # number of overall (read+write) accesses
422system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070900 # miss rate for ReadReq accesses
423system.cpu.dcache.ReadReq_miss_rate::total 0.070900 # miss rate for ReadReq accesses
| 418system.cpu.dcache.demand_accesses::cpu.data 2518 # number of demand (read+write) accesses
419system.cpu.dcache.demand_accesses::total 2518 # number of demand (read+write) accesses
420system.cpu.dcache.overall_accesses::cpu.data 2518 # number of overall (read+write) accesses
421system.cpu.dcache.overall_accesses::total 2518 # number of overall (read+write) accesses
422system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070707 # miss rate for ReadReq accesses
423system.cpu.dcache.ReadReq_miss_rate::total 0.070707 # miss rate for ReadReq accesses
|
424system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses
425system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses
| 424system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses
425system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses
|
426system.cpu.dcache.demand_miss_rate::cpu.data 0.074726 # miss rate for demand accesses
427system.cpu.dcache.demand_miss_rate::total 0.074726 # miss rate for demand accesses
428system.cpu.dcache.overall_miss_rate::cpu.data 0.074726 # miss rate for overall accesses
429system.cpu.dcache.overall_miss_rate::total 0.074726 # miss rate for overall accesses
430system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35047.826087 # average ReadReq miss latency
431system.cpu.dcache.ReadReq_avg_miss_latency::total 35047.826087 # average ReadReq miss latency
432system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency
433system.cpu.dcache.WriteReq_avg_miss_latency::total 38388.157895 # average WriteReq miss latency
434system.cpu.dcache.demand_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency
435system.cpu.dcache.demand_avg_miss_latency::total 36376.963351 # average overall miss latency
436system.cpu.dcache.overall_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency
437system.cpu.dcache.overall_avg_miss_latency::total 36376.963351 # average overall miss latency
| 426system.cpu.dcache.demand_miss_rate::cpu.data 0.074662 # miss rate for demand accesses
427system.cpu.dcache.demand_miss_rate::total 0.074662 # miss rate for demand accesses
428system.cpu.dcache.overall_miss_rate::cpu.data 0.074662 # miss rate for overall accesses
429system.cpu.dcache.overall_miss_rate::total 0.074662 # miss rate for overall accesses
430system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39299.107143 # average ReadReq miss latency
431system.cpu.dcache.ReadReq_avg_miss_latency::total 39299.107143 # average ReadReq miss latency
432system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40506.578947 # average WriteReq miss latency
433system.cpu.dcache.WriteReq_avg_miss_latency::total 40506.578947 # average WriteReq miss latency
434system.cpu.dcache.demand_avg_miss_latency::cpu.data 39787.234043 # average overall miss latency
435system.cpu.dcache.demand_avg_miss_latency::total 39787.234043 # average overall miss latency
436system.cpu.dcache.overall_avg_miss_latency::cpu.data 39787.234043 # average overall miss latency
437system.cpu.dcache.overall_avg_miss_latency::total 39787.234043 # average overall miss latency
|
438system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
439system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
440system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
441system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
442system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
443system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
444system.cpu.dcache.fast_writes 0 # number of fast writes performed
445system.cpu.dcache.cache_copies 0 # number of cache copies performed
| 438system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
439system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
440system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
441system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
442system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
443system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
444system.cpu.dcache.fast_writes 0 # number of fast writes performed
445system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
446system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits
447system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits
448system.cpu.dcache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits
449system.cpu.dcache.demand_mshr_hits::total 42 # number of demand (read+write) MSHR hits
450system.cpu.dcache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits
451system.cpu.dcache.overall_mshr_hits::total 42 # number of overall MSHR hits
452system.cpu.dcache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses
453system.cpu.dcache.ReadReq_mshr_misses::total 73 # number of ReadReq MSHR misses
| 446system.cpu.dcache.ReadReq_mshr_hits::cpu.data 43 # number of ReadReq MSHR hits
447system.cpu.dcache.ReadReq_mshr_hits::total 43 # number of ReadReq MSHR hits
448system.cpu.dcache.demand_mshr_hits::cpu.data 43 # number of demand (read+write) MSHR hits
449system.cpu.dcache.demand_mshr_hits::total 43 # number of demand (read+write) MSHR hits
450system.cpu.dcache.overall_mshr_hits::cpu.data 43 # number of overall MSHR hits
451system.cpu.dcache.overall_mshr_hits::total 43 # number of overall MSHR hits
452system.cpu.dcache.ReadReq_mshr_misses::cpu.data 69 # number of ReadReq MSHR misses
453system.cpu.dcache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses
|
454system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
455system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
| 454system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
455system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
|
456system.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses
457system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses
458system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses
459system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses
460system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2574000 # number of ReadReq MSHR miss cycles
461system.cpu.dcache.ReadReq_mshr_miss_latency::total 2574000 # number of ReadReq MSHR miss cycles
462system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689500 # number of WriteReq MSHR miss cycles
463system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689500 # number of WriteReq MSHR miss cycles
464system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5263500 # number of demand (read+write) MSHR miss cycles
465system.cpu.dcache.demand_mshr_miss_latency::total 5263500 # number of demand (read+write) MSHR miss cycles
466system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5263500 # number of overall MSHR miss cycles
467system.cpu.dcache.overall_mshr_miss_latency::total 5263500 # number of overall MSHR miss cycles
468system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045006 # mshr miss rate for ReadReq accesses
469system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045006 # mshr miss rate for ReadReq accesses
| 456system.cpu.dcache.demand_mshr_misses::cpu.data 145 # number of demand (read+write) MSHR misses
457system.cpu.dcache.demand_mshr_misses::total 145 # number of demand (read+write) MSHR misses
458system.cpu.dcache.overall_mshr_misses::cpu.data 145 # number of overall MSHR misses
459system.cpu.dcache.overall_mshr_misses::total 145 # number of overall MSHR misses
460system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2699500 # number of ReadReq MSHR miss cycles
461system.cpu.dcache.ReadReq_mshr_miss_latency::total 2699500 # number of ReadReq MSHR miss cycles
462system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2850500 # number of WriteReq MSHR miss cycles
463system.cpu.dcache.WriteReq_mshr_miss_latency::total 2850500 # number of WriteReq MSHR miss cycles
464system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5550000 # number of demand (read+write) MSHR miss cycles
465system.cpu.dcache.demand_mshr_miss_latency::total 5550000 # number of demand (read+write) MSHR miss cycles
466system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5550000 # number of overall MSHR miss cycles
467system.cpu.dcache.overall_mshr_miss_latency::total 5550000 # number of overall MSHR miss cycles
468system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043561 # mshr miss rate for ReadReq accesses
469system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043561 # mshr miss rate for ReadReq accesses
|
470system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses
471system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses
| 470system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses
471system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses
|
472system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for demand accesses
473system.cpu.dcache.demand_mshr_miss_rate::total 0.058294 # mshr miss rate for demand accesses
474system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for overall accesses
475system.cpu.dcache.overall_mshr_miss_rate::total 0.058294 # mshr miss rate for overall accesses
476system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35260.273973 # average ReadReq mshr miss latency
477system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35260.273973 # average ReadReq mshr miss latency
478system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35388.157895 # average WriteReq mshr miss latency
479system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35388.157895 # average WriteReq mshr miss latency
480system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency
481system.cpu.dcache.demand_avg_mshr_miss_latency::total 35325.503356 # average overall mshr miss latency
482system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency
483system.cpu.dcache.overall_avg_mshr_miss_latency::total 35325.503356 # average overall mshr miss latency
| 472system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057585 # mshr miss rate for demand accesses
473system.cpu.dcache.demand_mshr_miss_rate::total 0.057585 # mshr miss rate for demand accesses
474system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057585 # mshr miss rate for overall accesses
475system.cpu.dcache.overall_mshr_miss_rate::total 0.057585 # mshr miss rate for overall accesses
476system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39123.188406 # average ReadReq mshr miss latency
477system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39123.188406 # average ReadReq mshr miss latency
478system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37506.578947 # average WriteReq mshr miss latency
479system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37506.578947 # average WriteReq mshr miss latency
480system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38275.862069 # average overall mshr miss latency
481system.cpu.dcache.demand_avg_mshr_miss_latency::total 38275.862069 # average overall mshr miss latency
482system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38275.862069 # average overall mshr miss latency
483system.cpu.dcache.overall_avg_mshr_miss_latency::total 38275.862069 # average overall mshr miss latency
|
484system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
485system.cpu.l2cache.replacements 0 # number of replacements
| 484system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
485system.cpu.l2cache.replacements 0 # number of replacements
|
486system.cpu.l2cache.tagsinuse 179.622577 # Cycle average of tags in use
487system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
488system.cpu.l2cache.sampled_refs 374 # Sample count of references to valid blocks.
489system.cpu.l2cache.avg_refs 0.005348 # Average number of references to valid blocks.
| 486system.cpu.l2cache.tagsinuse 177.887385 # Cycle average of tags in use
487system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
488system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks.
489system.cpu.l2cache.avg_refs 0.002710 # Average number of references to valid blocks.
|
490system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 490system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
491system.cpu.l2cache.occ_blocks::cpu.inst 145.234150 # Average occupied blocks per requestor
492system.cpu.l2cache.occ_blocks::cpu.data 34.388427 # Average occupied blocks per requestor
493system.cpu.l2cache.occ_percent::cpu.inst 0.004432 # Average percentage of cache occupancy
494system.cpu.l2cache.occ_percent::cpu.data 0.001049 # Average percentage of cache occupancy
495system.cpu.l2cache.occ_percent::total 0.005482 # Average percentage of cache occupancy
496system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
497system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
498system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
499system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
500system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
501system.cpu.l2cache.overall_hits::total 2 # number of overall hits
502system.cpu.l2cache.ReadReq_misses::cpu.inst 302 # number of ReadReq misses
503system.cpu.l2cache.ReadReq_misses::cpu.data 73 # number of ReadReq misses
504system.cpu.l2cache.ReadReq_misses::total 375 # number of ReadReq misses
| 491system.cpu.l2cache.occ_blocks::cpu.inst 144.949907 # Average occupied blocks per requestor
492system.cpu.l2cache.occ_blocks::cpu.data 32.937478 # Average occupied blocks per requestor
493system.cpu.l2cache.occ_percent::cpu.inst 0.004424 # Average percentage of cache occupancy
494system.cpu.l2cache.occ_percent::cpu.data 0.001005 # Average percentage of cache occupancy
495system.cpu.l2cache.occ_percent::total 0.005429 # Average percentage of cache occupancy
496system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
497system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
498system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
499system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
500system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
501system.cpu.l2cache.overall_hits::total 1 # number of overall hits
502system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses
503system.cpu.l2cache.ReadReq_misses::cpu.data 69 # number of ReadReq misses
504system.cpu.l2cache.ReadReq_misses::total 370 # number of ReadReq misses
|
505system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses
506system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses
| 505system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses
506system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses
|
507system.cpu.l2cache.demand_misses::cpu.inst 302 # number of demand (read+write) misses
508system.cpu.l2cache.demand_misses::cpu.data 149 # number of demand (read+write) misses
509system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses
510system.cpu.l2cache.overall_misses::cpu.inst 302 # number of overall misses
511system.cpu.l2cache.overall_misses::cpu.data 149 # number of overall misses
512system.cpu.l2cache.overall_misses::total 451 # number of overall misses
513system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10368000 # number of ReadReq miss cycles
514system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2486500 # number of ReadReq miss cycles
515system.cpu.l2cache.ReadReq_miss_latency::total 12854500 # number of ReadReq miss cycles
516system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2603000 # number of ReadExReq miss cycles
517system.cpu.l2cache.ReadExReq_miss_latency::total 2603000 # number of ReadExReq miss cycles
518system.cpu.l2cache.demand_miss_latency::cpu.inst 10368000 # number of demand (read+write) miss cycles
519system.cpu.l2cache.demand_miss_latency::cpu.data 5089500 # number of demand (read+write) miss cycles
520system.cpu.l2cache.demand_miss_latency::total 15457500 # number of demand (read+write) miss cycles
521system.cpu.l2cache.overall_miss_latency::cpu.inst 10368000 # number of overall miss cycles
522system.cpu.l2cache.overall_miss_latency::cpu.data 5089500 # number of overall miss cycles
523system.cpu.l2cache.overall_miss_latency::total 15457500 # number of overall miss cycles
524system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses)
525system.cpu.l2cache.ReadReq_accesses::cpu.data 73 # number of ReadReq accesses(hits+misses)
526system.cpu.l2cache.ReadReq_accesses::total 377 # number of ReadReq accesses(hits+misses)
| 507system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses
508system.cpu.l2cache.demand_misses::cpu.data 145 # number of demand (read+write) misses
509system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses
510system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
511system.cpu.l2cache.overall_misses::cpu.data 145 # number of overall misses
512system.cpu.l2cache.overall_misses::total 446 # number of overall misses
513system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10831500 # number of ReadReq miss cycles
514system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2627000 # number of ReadReq miss cycles
515system.cpu.l2cache.ReadReq_miss_latency::total 13458500 # number of ReadReq miss cycles
516system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2772000 # number of ReadExReq miss cycles
517system.cpu.l2cache.ReadExReq_miss_latency::total 2772000 # number of ReadExReq miss cycles
518system.cpu.l2cache.demand_miss_latency::cpu.inst 10831500 # number of demand (read+write) miss cycles
519system.cpu.l2cache.demand_miss_latency::cpu.data 5399000 # number of demand (read+write) miss cycles
520system.cpu.l2cache.demand_miss_latency::total 16230500 # number of demand (read+write) miss cycles
521system.cpu.l2cache.overall_miss_latency::cpu.inst 10831500 # number of overall miss cycles
522system.cpu.l2cache.overall_miss_latency::cpu.data 5399000 # number of overall miss cycles
523system.cpu.l2cache.overall_miss_latency::total 16230500 # number of overall miss cycles
524system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
525system.cpu.l2cache.ReadReq_accesses::cpu.data 69 # number of ReadReq accesses(hits+misses)
526system.cpu.l2cache.ReadReq_accesses::total 371 # number of ReadReq accesses(hits+misses)
|
527system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses)
528system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses)
| 527system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses)
528system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses)
|
529system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses
530system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses
531system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses
532system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses
533system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses
534system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses
535system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993421 # miss rate for ReadReq accesses
| 529system.cpu.l2cache.demand_accesses::cpu.inst 302 # number of demand (read+write) accesses
530system.cpu.l2cache.demand_accesses::cpu.data 145 # number of demand (read+write) accesses
531system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses
532system.cpu.l2cache.overall_accesses::cpu.inst 302 # number of overall (read+write) accesses
533system.cpu.l2cache.overall_accesses::cpu.data 145 # number of overall (read+write) accesses
534system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses
535system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996689 # miss rate for ReadReq accesses
|
536system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
| 536system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
537system.cpu.l2cache.ReadReq_miss_rate::total 0.994695 # miss rate for ReadReq accesses
| 537system.cpu.l2cache.ReadReq_miss_rate::total 0.997305 # miss rate for ReadReq accesses
|
538system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
539system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
| 538system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
539system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
540system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993421 # miss rate for demand accesses
| 540system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 # miss rate for demand accesses
|
541system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
| 541system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
542system.cpu.l2cache.demand_miss_rate::total 0.995585 # miss rate for demand accesses
543system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993421 # miss rate for overall accesses
| 542system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses
543system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
|
544system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
| 544system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
545system.cpu.l2cache.overall_miss_rate::total 0.995585 # miss rate for overall accesses
546system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.125828 # average ReadReq miss latency
547system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836 # average ReadReq miss latency
548system.cpu.l2cache.ReadReq_avg_miss_latency::total 34278.666667 # average ReadReq miss latency
549system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34250 # average ReadExReq miss latency
550system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34250 # average ReadExReq miss latency
551system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency
552system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency
553system.cpu.l2cache.demand_avg_miss_latency::total 34273.835920 # average overall miss latency
554system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency
555system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency
556system.cpu.l2cache.overall_avg_miss_latency::total 34273.835920 # average overall miss latency
| 545system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses
546system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35985.049834 # average ReadReq miss latency
547system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38072.463768 # average ReadReq miss latency
548system.cpu.l2cache.ReadReq_avg_miss_latency::total 36374.324324 # average ReadReq miss latency
549system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36473.684211 # average ReadExReq miss latency
550system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36473.684211 # average ReadExReq miss latency
551system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35985.049834 # average overall miss latency
552system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37234.482759 # average overall miss latency
553system.cpu.l2cache.demand_avg_miss_latency::total 36391.255605 # average overall miss latency
554system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35985.049834 # average overall miss latency
555system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37234.482759 # average overall miss latency
556system.cpu.l2cache.overall_avg_miss_latency::total 36391.255605 # average overall miss latency
|
557system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
558system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
559system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
560system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
561system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
562system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
563system.cpu.l2cache.fast_writes 0 # number of fast writes performed
564system.cpu.l2cache.cache_copies 0 # number of cache copies performed
| 557system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
558system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
559system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
560system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
561system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
562system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
563system.cpu.l2cache.fast_writes 0 # number of fast writes performed
564system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
565system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
566system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses
567system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses
| 565system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
566system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 69 # number of ReadReq MSHR misses
567system.cpu.l2cache.ReadReq_mshr_misses::total 370 # number of ReadReq MSHR misses
|
568system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses
569system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses
| 568system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses
569system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses
|
570system.cpu.l2cache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
571system.cpu.l2cache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses
572system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses
573system.cpu.l2cache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
574system.cpu.l2cache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses
575system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses
576system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9394000 # number of ReadReq MSHR miss cycles
577system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2263500 # number of ReadReq MSHR miss cycles
578system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11657500 # number of ReadReq MSHR miss cycles
579system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2369500 # number of ReadExReq MSHR miss cycles
580system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2369500 # number of ReadExReq MSHR miss cycles
581system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9394000 # number of demand (read+write) MSHR miss cycles
582system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4633000 # number of demand (read+write) MSHR miss cycles
583system.cpu.l2cache.demand_mshr_miss_latency::total 14027000 # number of demand (read+write) MSHR miss cycles
584system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9394000 # number of overall MSHR miss cycles
585system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4633000 # number of overall MSHR miss cycles
586system.cpu.l2cache.overall_mshr_miss_latency::total 14027000 # number of overall MSHR miss cycles
587system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for ReadReq accesses
| 570system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
571system.cpu.l2cache.demand_mshr_misses::cpu.data 145 # number of demand (read+write) MSHR misses
572system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
573system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
574system.cpu.l2cache.overall_mshr_misses::cpu.data 145 # number of overall MSHR misses
575system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
576system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9877000 # number of ReadReq MSHR miss cycles
577system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2416500 # number of ReadReq MSHR miss cycles
578system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12293500 # number of ReadReq MSHR miss cycles
579system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2541500 # number of ReadExReq MSHR miss cycles
580system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2541500 # number of ReadExReq MSHR miss cycles
581system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9877000 # number of demand (read+write) MSHR miss cycles
582system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4958000 # number of demand (read+write) MSHR miss cycles
583system.cpu.l2cache.demand_mshr_miss_latency::total 14835000 # number of demand (read+write) MSHR miss cycles
584system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9877000 # number of overall MSHR miss cycles
585system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4958000 # number of overall MSHR miss cycles
586system.cpu.l2cache.overall_mshr_miss_latency::total 14835000 # number of overall MSHR miss cycles
587system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
|
588system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
| 588system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
589system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994695 # mshr miss rate for ReadReq accesses
| 589system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997305 # mshr miss rate for ReadReq accesses
|
590system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
591system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
| 590system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
591system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
592system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for demand accesses
| 592system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses
|
593system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
| 593system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
594system.cpu.l2cache.demand_mshr_miss_rate::total 0.995585 # mshr miss rate for demand accesses
595system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for overall accesses
| 594system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses
595system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
|
596system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
| 596system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
597system.cpu.l2cache.overall_mshr_miss_rate::total 0.995585 # mshr miss rate for overall accesses
598system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.960265 # average ReadReq mshr miss latency
599system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.849315 # average ReadReq mshr miss latency
600system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.666667 # average ReadReq mshr miss latency
601system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency
602system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31177.631579 # average ReadExReq mshr miss latency
603system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency
604system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency
605system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency
606system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency
607system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency
608system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency
| 597system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses
598system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32813.953488 # average ReadReq mshr miss latency
599system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35021.739130 # average ReadReq mshr miss latency
600system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33225.675676 # average ReadReq mshr miss latency
601system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33440.789474 # average ReadExReq mshr miss latency
602system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33440.789474 # average ReadExReq mshr miss latency
603system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32813.953488 # average overall mshr miss latency
604system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34193.103448 # average overall mshr miss latency
605system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33262.331839 # average overall mshr miss latency
606system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32813.953488 # average overall mshr miss latency
607system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34193.103448 # average overall mshr miss latency
608system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33262.331839 # average overall mshr miss latency
|
609system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
610
611---------- End Simulation Statistics ----------
| 609system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
610
611---------- End Simulation Statistics ----------
|