| stats.txt (9039:9a22621c741c) | stats.txt (9055:38f1926fb599) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 12198000 # Number of ticks simulated 5final_tick 12198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 12198000 # Number of ticks simulated 5final_tick 12198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 27776 # Simulator instruction rate (inst/s) 8host_op_rate 50299 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 62542635 # Simulator tick rate (ticks/s) 10host_mem_usage 245428 # Number of bytes of host memory used 11host_seconds 0.20 # Real time elapsed on the host | 7host_inst_rate 39950 # Simulator instruction rate (inst/s) 8host_op_rate 72345 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 89952499 # Simulator tick rate (ticks/s) 10host_mem_usage 224288 # Number of bytes of host memory used 11host_seconds 0.14 # Real time elapsed on the host |
| 12sim_insts 5416 # Number of instructions simulated 13sim_ops 9809 # Number of ops (including micro ops) simulated | 12sim_insts 5416 # Number of instructions simulated 13sim_ops 9809 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 28864 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 19328 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 451 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 2366289556 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 1584522053 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 2366289556 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::cpu.inst 19328 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9536 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28864 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 19328 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 19328 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 302 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 149 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 451 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1584522053 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 781767503 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2366289556 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1584522053 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1584522053 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1584522053 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 781767503 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2366289556 # Total bandwidth to/from this memory (bytes/s) |
| 23system.cpu.workload.num_syscalls 11 # Number of system calls 24system.cpu.numCycles 24397 # number of cpu cycles simulated 25system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 26system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 27system.cpu.BPredUnit.lookups 3206 # Number of BP lookups 28system.cpu.BPredUnit.condPredicted 3206 # Number of conditional branches predicted 29system.cpu.BPredUnit.condIncorrect 560 # Number of conditional branches incorrect 30system.cpu.BPredUnit.BTBLookups 2627 # Number of BTB lookups --- 285 unchanged lines hidden (view full) --- 316system.cpu.icache.overall_miss_latency::total 13866500 # number of overall miss cycles 317system.cpu.icache.ReadReq_accesses::cpu.inst 1951 # number of ReadReq accesses(hits+misses) 318system.cpu.icache.ReadReq_accesses::total 1951 # number of ReadReq accesses(hits+misses) 319system.cpu.icache.demand_accesses::cpu.inst 1951 # number of demand (read+write) accesses 320system.cpu.icache.demand_accesses::total 1951 # number of demand (read+write) accesses 321system.cpu.icache.overall_accesses::cpu.inst 1951 # number of overall (read+write) accesses 322system.cpu.icache.overall_accesses::total 1951 # number of overall (read+write) accesses 323system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199897 # miss rate for ReadReq accesses | 30system.cpu.workload.num_syscalls 11 # Number of system calls 31system.cpu.numCycles 24397 # number of cpu cycles simulated 32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 34system.cpu.BPredUnit.lookups 3206 # Number of BP lookups 35system.cpu.BPredUnit.condPredicted 3206 # Number of conditional branches predicted 36system.cpu.BPredUnit.condIncorrect 560 # Number of conditional branches incorrect 37system.cpu.BPredUnit.BTBLookups 2627 # Number of BTB lookups --- 285 unchanged lines hidden (view full) --- 323system.cpu.icache.overall_miss_latency::total 13866500 # number of overall miss cycles 324system.cpu.icache.ReadReq_accesses::cpu.inst 1951 # number of ReadReq accesses(hits+misses) 325system.cpu.icache.ReadReq_accesses::total 1951 # number of ReadReq accesses(hits+misses) 326system.cpu.icache.demand_accesses::cpu.inst 1951 # number of demand (read+write) accesses 327system.cpu.icache.demand_accesses::total 1951 # number of demand (read+write) accesses 328system.cpu.icache.overall_accesses::cpu.inst 1951 # number of overall (read+write) accesses 329system.cpu.icache.overall_accesses::total 1951 # number of overall (read+write) accesses 330system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199897 # miss rate for ReadReq accesses |
| 331system.cpu.icache.ReadReq_miss_rate::total 0.199897 # miss rate for ReadReq accesses |
|
| 324system.cpu.icache.demand_miss_rate::cpu.inst 0.199897 # miss rate for demand accesses | 332system.cpu.icache.demand_miss_rate::cpu.inst 0.199897 # miss rate for demand accesses |
| 333system.cpu.icache.demand_miss_rate::total 0.199897 # miss rate for demand accesses |
|
| 325system.cpu.icache.overall_miss_rate::cpu.inst 0.199897 # miss rate for overall accesses | 334system.cpu.icache.overall_miss_rate::cpu.inst 0.199897 # miss rate for overall accesses |
| 335system.cpu.icache.overall_miss_rate::total 0.199897 # miss rate for overall accesses |
|
| 326system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35555.128205 # average ReadReq miss latency | 336system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35555.128205 # average ReadReq miss latency |
| 337system.cpu.icache.ReadReq_avg_miss_latency::total 35555.128205 # average ReadReq miss latency |
|
| 327system.cpu.icache.demand_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency | 338system.cpu.icache.demand_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency |
| 339system.cpu.icache.demand_avg_miss_latency::total 35555.128205 # average overall miss latency |
|
| 328system.cpu.icache.overall_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency | 340system.cpu.icache.overall_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency |
| 341system.cpu.icache.overall_avg_miss_latency::total 35555.128205 # average overall miss latency |
|
| 329system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 330system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 331system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 332system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 333system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 334system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 335system.cpu.icache.fast_writes 0 # number of fast writes performed 336system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 348system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses 349system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10687000 # number of ReadReq MSHR miss cycles 350system.cpu.icache.ReadReq_mshr_miss_latency::total 10687000 # number of ReadReq MSHR miss cycles 351system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10687000 # number of demand (read+write) MSHR miss cycles 352system.cpu.icache.demand_mshr_miss_latency::total 10687000 # number of demand (read+write) MSHR miss cycles 353system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10687000 # number of overall MSHR miss cycles 354system.cpu.icache.overall_mshr_miss_latency::total 10687000 # number of overall MSHR miss cycles 355system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for ReadReq accesses | 342system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 343system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 344system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 345system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 346system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 347system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 348system.cpu.icache.fast_writes 0 # number of fast writes performed 349system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 361system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses 362system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10687000 # number of ReadReq MSHR miss cycles 363system.cpu.icache.ReadReq_mshr_miss_latency::total 10687000 # number of ReadReq MSHR miss cycles 364system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10687000 # number of demand (read+write) MSHR miss cycles 365system.cpu.icache.demand_mshr_miss_latency::total 10687000 # number of demand (read+write) MSHR miss cycles 366system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10687000 # number of overall MSHR miss cycles 367system.cpu.icache.overall_mshr_miss_latency::total 10687000 # number of overall MSHR miss cycles 368system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for ReadReq accesses |
| 369system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155818 # mshr miss rate for ReadReq accesses |
|
| 356system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for demand accesses | 370system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for demand accesses |
| 371system.cpu.icache.demand_mshr_miss_rate::total 0.155818 # mshr miss rate for demand accesses |
|
| 357system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for overall accesses | 372system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for overall accesses |
| 373system.cpu.icache.overall_mshr_miss_rate::total 0.155818 # mshr miss rate for overall accesses |
|
| 358system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35154.605263 # average ReadReq mshr miss latency | 374system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35154.605263 # average ReadReq mshr miss latency |
| 375system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35154.605263 # average ReadReq mshr miss latency |
|
| 359system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency | 376system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency |
| 377system.cpu.icache.demand_avg_mshr_miss_latency::total 35154.605263 # average overall mshr miss latency |
|
| 360system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency | 378system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency |
| 379system.cpu.icache.overall_avg_mshr_miss_latency::total 35154.605263 # average overall mshr miss latency |
|
| 361system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 362system.cpu.dcache.replacements 0 # number of replacements 363system.cpu.dcache.tagsinuse 84.751522 # Cycle average of tags in use 364system.cpu.dcache.total_refs 2365 # Total number of references to valid blocks. 365system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. 366system.cpu.dcache.avg_refs 15.979730 # Average number of references to valid blocks. 367system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 368system.cpu.dcache.occ_blocks::cpu.data 84.751522 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 396system.cpu.dcache.ReadReq_accesses::total 1622 # number of ReadReq accesses(hits+misses) 397system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) 398system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) 399system.cpu.dcache.demand_accesses::cpu.data 2556 # number of demand (read+write) accesses 400system.cpu.dcache.demand_accesses::total 2556 # number of demand (read+write) accesses 401system.cpu.dcache.overall_accesses::cpu.data 2556 # number of overall (read+write) accesses 402system.cpu.dcache.overall_accesses::total 2556 # number of overall (read+write) accesses 403system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070900 # miss rate for ReadReq accesses | 380system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 381system.cpu.dcache.replacements 0 # number of replacements 382system.cpu.dcache.tagsinuse 84.751522 # Cycle average of tags in use 383system.cpu.dcache.total_refs 2365 # Total number of references to valid blocks. 384system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. 385system.cpu.dcache.avg_refs 15.979730 # Average number of references to valid blocks. 386system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 387system.cpu.dcache.occ_blocks::cpu.data 84.751522 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 415system.cpu.dcache.ReadReq_accesses::total 1622 # number of ReadReq accesses(hits+misses) 416system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) 417system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) 418system.cpu.dcache.demand_accesses::cpu.data 2556 # number of demand (read+write) accesses 419system.cpu.dcache.demand_accesses::total 2556 # number of demand (read+write) accesses 420system.cpu.dcache.overall_accesses::cpu.data 2556 # number of overall (read+write) accesses 421system.cpu.dcache.overall_accesses::total 2556 # number of overall (read+write) accesses 422system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070900 # miss rate for ReadReq accesses |
| 423system.cpu.dcache.ReadReq_miss_rate::total 0.070900 # miss rate for ReadReq accesses |
|
| 404system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses | 424system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses |
| 425system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses |
|
| 405system.cpu.dcache.demand_miss_rate::cpu.data 0.074726 # miss rate for demand accesses | 426system.cpu.dcache.demand_miss_rate::cpu.data 0.074726 # miss rate for demand accesses |
| 427system.cpu.dcache.demand_miss_rate::total 0.074726 # miss rate for demand accesses |
|
| 406system.cpu.dcache.overall_miss_rate::cpu.data 0.074726 # miss rate for overall accesses | 428system.cpu.dcache.overall_miss_rate::cpu.data 0.074726 # miss rate for overall accesses |
| 429system.cpu.dcache.overall_miss_rate::total 0.074726 # miss rate for overall accesses |
|
| 407system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35047.826087 # average ReadReq miss latency | 430system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35047.826087 # average ReadReq miss latency |
| 431system.cpu.dcache.ReadReq_avg_miss_latency::total 35047.826087 # average ReadReq miss latency |
|
| 408system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency | 432system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency |
| 433system.cpu.dcache.WriteReq_avg_miss_latency::total 38388.157895 # average WriteReq miss latency |
|
| 409system.cpu.dcache.demand_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency | 434system.cpu.dcache.demand_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency |
| 435system.cpu.dcache.demand_avg_miss_latency::total 36376.963351 # average overall miss latency |
|
| 410system.cpu.dcache.overall_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency | 436system.cpu.dcache.overall_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency |
| 437system.cpu.dcache.overall_avg_miss_latency::total 36376.963351 # average overall miss latency |
|
| 411system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 412system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 413system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 414system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 415system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 416system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 417system.cpu.dcache.fast_writes 0 # number of fast writes performed 418system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 15 unchanged lines hidden (view full) --- 434system.cpu.dcache.ReadReq_mshr_miss_latency::total 2574000 # number of ReadReq MSHR miss cycles 435system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689500 # number of WriteReq MSHR miss cycles 436system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689500 # number of WriteReq MSHR miss cycles 437system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5263500 # number of demand (read+write) MSHR miss cycles 438system.cpu.dcache.demand_mshr_miss_latency::total 5263500 # number of demand (read+write) MSHR miss cycles 439system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5263500 # number of overall MSHR miss cycles 440system.cpu.dcache.overall_mshr_miss_latency::total 5263500 # number of overall MSHR miss cycles 441system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045006 # mshr miss rate for ReadReq accesses | 438system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 439system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 440system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 441system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 442system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 443system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 444system.cpu.dcache.fast_writes 0 # number of fast writes performed 445system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 15 unchanged lines hidden (view full) --- 461system.cpu.dcache.ReadReq_mshr_miss_latency::total 2574000 # number of ReadReq MSHR miss cycles 462system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689500 # number of WriteReq MSHR miss cycles 463system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689500 # number of WriteReq MSHR miss cycles 464system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5263500 # number of demand (read+write) MSHR miss cycles 465system.cpu.dcache.demand_mshr_miss_latency::total 5263500 # number of demand (read+write) MSHR miss cycles 466system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5263500 # number of overall MSHR miss cycles 467system.cpu.dcache.overall_mshr_miss_latency::total 5263500 # number of overall MSHR miss cycles 468system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045006 # mshr miss rate for ReadReq accesses |
| 469system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045006 # mshr miss rate for ReadReq accesses |
|
| 442system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses | 470system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses |
| 471system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses |
|
| 443system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for demand accesses | 472system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for demand accesses |
| 473system.cpu.dcache.demand_mshr_miss_rate::total 0.058294 # mshr miss rate for demand accesses |
|
| 444system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for overall accesses | 474system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for overall accesses |
| 475system.cpu.dcache.overall_mshr_miss_rate::total 0.058294 # mshr miss rate for overall accesses |
|
| 445system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35260.273973 # average ReadReq mshr miss latency | 476system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35260.273973 # average ReadReq mshr miss latency |
| 477system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35260.273973 # average ReadReq mshr miss latency |
|
| 446system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35388.157895 # average WriteReq mshr miss latency | 478system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35388.157895 # average WriteReq mshr miss latency |
| 479system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35388.157895 # average WriteReq mshr miss latency |
|
| 447system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency | 480system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency |
| 481system.cpu.dcache.demand_avg_mshr_miss_latency::total 35325.503356 # average overall mshr miss latency |
|
| 448system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency | 482system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency |
| 483system.cpu.dcache.overall_avg_mshr_miss_latency::total 35325.503356 # average overall mshr miss latency |
|
| 449system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 450system.cpu.l2cache.replacements 0 # number of replacements 451system.cpu.l2cache.tagsinuse 179.622577 # Cycle average of tags in use 452system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 453system.cpu.l2cache.sampled_refs 374 # Sample count of references to valid blocks. 454system.cpu.l2cache.avg_refs 0.005348 # Average number of references to valid blocks. 455system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 456system.cpu.l2cache.occ_blocks::cpu.inst 145.234150 # Average occupied blocks per requestor --- 37 unchanged lines hidden (view full) --- 494system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses 495system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses 496system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses 497system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses 498system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses 499system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses 500system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993421 # miss rate for ReadReq accesses 501system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses | 484system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 485system.cpu.l2cache.replacements 0 # number of replacements 486system.cpu.l2cache.tagsinuse 179.622577 # Cycle average of tags in use 487system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 488system.cpu.l2cache.sampled_refs 374 # Sample count of references to valid blocks. 489system.cpu.l2cache.avg_refs 0.005348 # Average number of references to valid blocks. 490system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 491system.cpu.l2cache.occ_blocks::cpu.inst 145.234150 # Average occupied blocks per requestor --- 37 unchanged lines hidden (view full) --- 529system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses 530system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses 531system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses 532system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses 533system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses 534system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses 535system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993421 # miss rate for ReadReq accesses 536system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses |
| 537system.cpu.l2cache.ReadReq_miss_rate::total 0.994695 # miss rate for ReadReq accesses |
|
| 502system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses | 538system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses |
| 539system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
|
| 503system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993421 # miss rate for demand accesses 504system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses | 540system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993421 # miss rate for demand accesses 541system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
| 542system.cpu.l2cache.demand_miss_rate::total 0.995585 # miss rate for demand accesses |
|
| 505system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993421 # miss rate for overall accesses 506system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses | 543system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993421 # miss rate for overall accesses 544system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
| 545system.cpu.l2cache.overall_miss_rate::total 0.995585 # miss rate for overall accesses |
|
| 507system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.125828 # average ReadReq miss latency 508system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836 # average ReadReq miss latency | 546system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.125828 # average ReadReq miss latency 547system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836 # average ReadReq miss latency |
| 548system.cpu.l2cache.ReadReq_avg_miss_latency::total 34278.666667 # average ReadReq miss latency |
|
| 509system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34250 # average ReadExReq miss latency | 549system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34250 # average ReadExReq miss latency |
| 550system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34250 # average ReadExReq miss latency |
|
| 510system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency 511system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency | 551system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency 552system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency |
| 553system.cpu.l2cache.demand_avg_miss_latency::total 34273.835920 # average overall miss latency |
|
| 512system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency 513system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency | 554system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency 555system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency |
| 556system.cpu.l2cache.overall_avg_miss_latency::total 34273.835920 # average overall miss latency |
|
| 514system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 515system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 516system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 517system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 518system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 519system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 520system.cpu.l2cache.fast_writes 0 # number of fast writes performed 521system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 16 unchanged lines hidden (view full) --- 538system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9394000 # number of demand (read+write) MSHR miss cycles 539system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4633000 # number of demand (read+write) MSHR miss cycles 540system.cpu.l2cache.demand_mshr_miss_latency::total 14027000 # number of demand (read+write) MSHR miss cycles 541system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9394000 # number of overall MSHR miss cycles 542system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4633000 # number of overall MSHR miss cycles 543system.cpu.l2cache.overall_mshr_miss_latency::total 14027000 # number of overall MSHR miss cycles 544system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for ReadReq accesses 545system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses | 557system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 558system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 559system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 560system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 561system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 562system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 563system.cpu.l2cache.fast_writes 0 # number of fast writes performed 564system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 16 unchanged lines hidden (view full) --- 581system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9394000 # number of demand (read+write) MSHR miss cycles 582system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4633000 # number of demand (read+write) MSHR miss cycles 583system.cpu.l2cache.demand_mshr_miss_latency::total 14027000 # number of demand (read+write) MSHR miss cycles 584system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9394000 # number of overall MSHR miss cycles 585system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4633000 # number of overall MSHR miss cycles 586system.cpu.l2cache.overall_mshr_miss_latency::total 14027000 # number of overall MSHR miss cycles 587system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for ReadReq accesses 588system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses |
| 589system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994695 # mshr miss rate for ReadReq accesses |
|
| 546system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses | 590system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses |
| 591system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
|
| 547system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for demand accesses 548system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses | 592system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for demand accesses 593system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
| 594system.cpu.l2cache.demand_mshr_miss_rate::total 0.995585 # mshr miss rate for demand accesses |
|
| 549system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for overall accesses 550system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses | 595system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for overall accesses 596system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
| 597system.cpu.l2cache.overall_mshr_miss_rate::total 0.995585 # mshr miss rate for overall accesses |
|
| 551system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.960265 # average ReadReq mshr miss latency 552system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.849315 # average ReadReq mshr miss latency | 598system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.960265 # average ReadReq mshr miss latency 599system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.849315 # average ReadReq mshr miss latency |
| 600system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.666667 # average ReadReq mshr miss latency |
|
| 553system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency | 601system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency |
| 602system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31177.631579 # average ReadExReq mshr miss latency |
|
| 554system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency 555system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency | 603system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency 604system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency |
| 605system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency |
|
| 556system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency 557system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency | 606system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency 607system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency |
| 608system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency |
|
| 558system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 559 560---------- End Simulation Statistics ---------- | 609system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 610 611---------- End Simulation Statistics ---------- |