| stats.txt (8844:a451e4eda591) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 12299500 # Number of ticks simulated 5final_tick 12299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 12299500 # Number of ticks simulated 5final_tick 12299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 59298 # Simulator instruction rate (inst/s) 8host_op_rate 107375 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 134612595 # Simulator tick rate (ticks/s) 10host_mem_usage 218308 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host | 7host_inst_rate 24245 # Simulator instruction rate (inst/s) 8host_op_rate 43905 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 55046151 # Simulator tick rate (ticks/s) 10host_mem_usage 223460 # Number of bytes of host memory used 11host_seconds 0.22 # Real time elapsed on the host |
| 12sim_insts 5416 # Number of instructions simulated 13sim_ops 9809 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 28864 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 19328 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 451 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 304 unchanged lines hidden (view full) --- 324system.cpu.icache.overall_miss_rate::cpu.inst 0.199187 # miss rate for overall accesses 325system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35471.938776 # average ReadReq miss latency 326system.cpu.icache.demand_avg_miss_latency::cpu.inst 35471.938776 # average overall miss latency 327system.cpu.icache.overall_avg_miss_latency::cpu.inst 35471.938776 # average overall miss latency 328system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 329system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 330system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 331system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 5416 # Number of instructions simulated 13sim_ops 9809 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 28864 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 19328 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 451 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 304 unchanged lines hidden (view full) --- 324system.cpu.icache.overall_miss_rate::cpu.inst 0.199187 # miss rate for overall accesses 325system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35471.938776 # average ReadReq miss latency 326system.cpu.icache.demand_avg_miss_latency::cpu.inst 35471.938776 # average overall miss latency 327system.cpu.icache.overall_avg_miss_latency::cpu.inst 35471.938776 # average overall miss latency 328system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 329system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 330system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 331system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 332system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 333system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 332system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 333system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 334system.cpu.icache.fast_writes 0 # number of fast writes performed 335system.cpu.icache.cache_copies 0 # number of cache copies performed 336system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits 337system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits 338system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits 339system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits 340system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits 341system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits --- 64 unchanged lines hidden (view full) --- 406system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34670.940171 # average ReadReq miss latency 407system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency 408system.cpu.dcache.demand_avg_miss_latency::cpu.data 36134.715026 # average overall miss latency 409system.cpu.dcache.overall_avg_miss_latency::cpu.data 36134.715026 # average overall miss latency 410system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 411system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 412system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 413system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 334system.cpu.icache.fast_writes 0 # number of fast writes performed 335system.cpu.icache.cache_copies 0 # number of cache copies performed 336system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits 337system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits 338system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits 339system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits 340system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits 341system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits --- 64 unchanged lines hidden (view full) --- 406system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34670.940171 # average ReadReq miss latency 407system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency 408system.cpu.dcache.demand_avg_miss_latency::cpu.data 36134.715026 # average overall miss latency 409system.cpu.dcache.overall_avg_miss_latency::cpu.data 36134.715026 # average overall miss latency 410system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 411system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 412system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 413system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 414system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 415system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 414system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 415system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 416system.cpu.dcache.fast_writes 0 # number of fast writes performed 417system.cpu.dcache.cache_copies 0 # number of cache copies performed 418system.cpu.dcache.ReadReq_mshr_hits::cpu.data 44 # number of ReadReq MSHR hits 419system.cpu.dcache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits 420system.cpu.dcache.demand_mshr_hits::cpu.data 44 # number of demand (read+write) MSHR hits 421system.cpu.dcache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits 422system.cpu.dcache.overall_mshr_hits::cpu.data 44 # number of overall MSHR hits 423system.cpu.dcache.overall_mshr_hits::total 44 # number of overall MSHR hits --- 85 unchanged lines hidden (view full) --- 509system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.847682 # average overall miss latency 510system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency 511system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.847682 # average overall miss latency 512system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency 513system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 514system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 515system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 516system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 416system.cpu.dcache.fast_writes 0 # number of fast writes performed 417system.cpu.dcache.cache_copies 0 # number of cache copies performed 418system.cpu.dcache.ReadReq_mshr_hits::cpu.data 44 # number of ReadReq MSHR hits 419system.cpu.dcache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits 420system.cpu.dcache.demand_mshr_hits::cpu.data 44 # number of demand (read+write) MSHR hits 421system.cpu.dcache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits 422system.cpu.dcache.overall_mshr_hits::cpu.data 44 # number of overall MSHR hits 423system.cpu.dcache.overall_mshr_hits::total 44 # number of overall MSHR hits --- 85 unchanged lines hidden (view full) --- 509system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.847682 # average overall miss latency 510system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency 511system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.847682 # average overall miss latency 512system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency 513system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 514system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 515system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 516system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 517system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 518system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 517system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 518system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 519system.cpu.l2cache.fast_writes 0 # number of fast writes performed 520system.cpu.l2cache.cache_copies 0 # number of cache copies performed 521system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses 522system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses 523system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses 524system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses 525system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses 526system.cpu.l2cache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- | 519system.cpu.l2cache.fast_writes 0 # number of fast writes performed 520system.cpu.l2cache.cache_copies 0 # number of cache copies performed 521system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses 522system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses 523system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses 524system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses 525system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses 526system.cpu.l2cache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- |