Cross Reference: /gem5/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000022 # Number of seconds simulated
4sim_ticks 22466500 # Number of ticks simulated
5final_tick 22466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 70304 # Simulator instruction rate (inst/s)
8host_op_rate 127350 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 293494415 # Simulator tick rate (ticks/s)
10host_mem_usage 271256 # Number of bytes of host memory used
11host_seconds 0.08 # Real time elapsed on the host

7host_inst_rate 24766 # Simulator instruction rate (inst/s)
8host_op_rate 44863 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 103395613 # Simulator tick rate (ticks/s)
10host_mem_usage 253532 # Number of bytes of host memory used
11host_seconds 0.22 # Real time elapsed on the host

12sim_insts 5380 # Number of instructions simulated
13sim_ops 9747 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
19system.physmem.bytes_read::total 26752 # Number of bytes read from this memory

--- 176 unchanged lines hidden (view full) ---

196system.physmem.bytesPerActivate::256-383 16 16.84% 80.00% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::384-511 6 6.32% 86.32% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::512-639 2 2.11% 88.42% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::640-767 3 3.16% 91.58% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::768-895 2 2.11% 93.68% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::896-1023 2 2.11% 95.79% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1024-1151 4 4.21% 100.00% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::total 95 # Bytes accessed per row activation

204system.physmem.totQLat 6803250 # Total ticks spent queuing
205system.physmem.totMemAccLat 14640750 # Total ticks spent from burst creation until serviced by the DRAM

204system.physmem.totQLat 6799250 # Total ticks spent queuing
205system.physmem.totMemAccLat 14636750 # Total ticks spent from burst creation until serviced by the DRAM

206system.physmem.totBusLat 2090000 # Total ticks spent in databus transfers

207system.physmem.avgQLat 16275.72 # Average queueing delay per DRAM burst

207system.physmem.avgQLat 16266.15 # Average queueing delay per DRAM burst

208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

209system.physmem.avgMemAccLat 35025.72 # Average memory access latency per DRAM burst

209system.physmem.avgMemAccLat 35016.15 # Average memory access latency per DRAM burst

210system.physmem.avgRdBW 1190.75 # Average DRAM read bandwidth in MiByte/s
211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
212system.physmem.avgRdBWSys 1190.75 # Average system read bandwidth in MiByte/s
213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
215system.physmem.busUtil 9.30 # Data bus utilization in percentage
216system.physmem.busUtilRead 9.30 # Data bus utilization in percentage for reads
217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes

--- 24 unchanged lines hidden (view full) ---

242system.physmem_0.memoryStateTime::PRE_PDN 359250 # Time in different power states
243system.physmem_0.memoryStateTime::ACT 4794250 # Time in different power states
244system.physmem_0.memoryStateTime::ACT_PDN 16769500 # Time in different power states
245system.physmem_1.actEnergy 485520 # Energy for activate commands per rank (pJ)
246system.physmem_1.preEnergy 235290 # Energy for precharge commands per rank (pJ)
247system.physmem_1.readEnergy 1570800 # Energy for read commands per rank (pJ)
248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
249system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)

250system.physmem_1.actBackEnergy 2963430 # Energy for active background per rank (pJ)

250system.physmem_1.actBackEnergy 2962290 # Energy for active background per rank (pJ)

251system.physmem_1.preBackEnergy 82560 # Energy for precharge background per rank (pJ)

252system.physmem_1.actPowerDownEnergy 7182000 # Energy for active power-down per rank (pJ)

252system.physmem_1.actPowerDownEnergy 7183140 # Energy for active power-down per rank (pJ)

253system.physmem_1.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ)
254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
255system.physmem_1.totalEnergy 13750320 # Total energy per rank (pJ)
256system.physmem_1.averagePower 612.009347 # Core power per rank (mW)
257system.physmem_1.totalIdleTime 14672000 # Total Idle time Per DRAM Rank
258system.physmem_1.memoryStateTime::IDLE 109000 # Time in different power states
259system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states

--- 88 unchanged lines hidden (view full) ---

349system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
350system.cpu.iq.iqInstsIssued 18112 # Number of instructions issued
351system.cpu.iq.iqSquashedInstsIssued 144 # Number of squashed instructions issued
352system.cpu.iq.iqSquashedInstsExamined 12051 # Number of squashed instructions iterated over during squash; mainly for profiling
353system.cpu.iq.iqSquashedOperandsExamined 16553 # Number of squashed operands that are examined and possibly removed from graph
354system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
355system.cpu.iq.issued_per_cycle::samples 24836 # Number of insts issued each cycle
356system.cpu.iq.issued_per_cycle::mean 0.729264 # Number of insts issued each cycle

357system.cpu.iq.issued_per_cycle::stdev 1.710819 # Number of insts issued each cycle

357system.cpu.iq.issued_per_cycle::stdev 1.710701 # Number of insts issued each cycle

358system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

359system.cpu.iq.issued_per_cycle::0 19691 79.28% 79.28% # Number of insts issued each cycle
360system.cpu.iq.issued_per_cycle::1 1200 4.83% 84.12% # Number of insts issued each cycle
361system.cpu.iq.issued_per_cycle::2 866 3.49% 87.60% # Number of insts issued each cycle

359system.cpu.iq.issued_per_cycle::0 19689 79.28% 79.28% # Number of insts issued each cycle
360system.cpu.iq.issued_per_cycle::1 1202 4.84% 84.12% # Number of insts issued each cycle
361system.cpu.iq.issued_per_cycle::2 867 3.49% 87.61% # Number of insts issued each cycle

362system.cpu.iq.issued_per_cycle::3 575 2.32% 89.92% # Number of insts issued each cycle

363system.cpu.iq.issued_per_cycle::4 815 3.28% 93.20% # Number of insts issued each cycle

363system.cpu.iq.issued_per_cycle::4 814 3.28% 93.20% # Number of insts issued each cycle

364system.cpu.iq.issued_per_cycle::5 575 2.32% 95.51% # Number of insts issued each cycle
365system.cpu.iq.issued_per_cycle::6 614 2.47% 97.99% # Number of insts issued each cycle
366system.cpu.iq.issued_per_cycle::7 364 1.47% 99.45% # Number of insts issued each cycle
367system.cpu.iq.issued_per_cycle::8 136 0.55% 100.00% # Number of insts issued each cycle
368system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
369system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
370system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
371system.cpu.iq.issued_per_cycle::total 24836 # Number of insts issued each cycle

--- 116 unchanged lines hidden (view full) ---

488system.cpu.iew.exec_swp 0 # number of swp insts executed
489system.cpu.iew.exec_nop 0 # number of nop insts executed
490system.cpu.iew.exec_refs 3306 # number of memory reference insts executed
491system.cpu.iew.exec_branches 1731 # Number of branches executed
492system.cpu.iew.exec_stores 1259 # Number of stores executed
493system.cpu.iew.exec_rate 0.379178 # Inst execution rate
494system.cpu.iew.wb_sent 16737 # cumulative count of insts sent to commit
495system.cpu.iew.wb_count 16422 # cumulative count of insts written-back

496system.cpu.iew.wb_producers 11019 # num instructions producing a value
497system.cpu.iew.wb_consumers 17148 # num instructions consuming a value

496system.cpu.iew.wb_producers 11018 # num instructions producing a value
497system.cpu.iew.wb_consumers 17146 # num instructions consuming a value

498system.cpu.iew.wb_rate 0.365469 # insts written-back per cycle

499system.cpu.iew.wb_fanout 0.642582 # average fanout of values written-back

499system.cpu.iew.wb_fanout 0.642599 # average fanout of values written-back

500system.cpu.commit.commitSquashedInsts 12050 # The number of squashed insts skipped by commit
501system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
502system.cpu.commit.branchMispredicts 648 # The number of times a branch was mispredicted
503system.cpu.commit.committed_per_cycle::samples 22793 # Number of insts commited each cycle
504system.cpu.commit.committed_per_cycle::mean 0.427631 # Number of insts commited each cycle

505system.cpu.commit.committed_per_cycle::stdev 1.307645 # Number of insts commited each cycle

505system.cpu.commit.committed_per_cycle::stdev 1.307612 # Number of insts commited each cycle

506system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

507system.cpu.commit.committed_per_cycle::0 19538 85.72% 85.72% # Number of insts commited each cycle
508system.cpu.commit.committed_per_cycle::1 1001 4.39% 90.11% # Number of insts commited each cycle
509system.cpu.commit.committed_per_cycle::2 566 2.48% 92.59% # Number of insts commited each cycle

507system.cpu.commit.committed_per_cycle::0 19537 85.71% 85.71% # Number of insts commited each cycle
508system.cpu.commit.committed_per_cycle::1 1003 4.40% 90.12% # Number of insts commited each cycle
509system.cpu.commit.committed_per_cycle::2 565 2.48% 92.59% # Number of insts commited each cycle

510system.cpu.commit.committed_per_cycle::3 727 3.19% 95.78% # Number of insts commited each cycle
511system.cpu.commit.committed_per_cycle::4 384 1.68% 97.47% # Number of insts commited each cycle
512system.cpu.commit.committed_per_cycle::5 133 0.58% 98.05% # Number of insts commited each cycle
513system.cpu.commit.committed_per_cycle::6 124 0.54% 98.60% # Number of insts commited each cycle
514system.cpu.commit.committed_per_cycle::7 72 0.32% 98.91% # Number of insts commited each cycle
515system.cpu.commit.committed_per_cycle::8 248 1.09% 100.00% # Number of insts commited each cycle
516system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
517system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle

--- 63 unchanged lines hidden (view full) ---

581system.cpu.int_regfile_writes 13219 # number of integer regfile writes
582system.cpu.fp_regfile_reads 4 # number of floating regfile reads
583system.cpu.cc_regfile_reads 8286 # number of cc regfile reads
584system.cpu.cc_regfile_writes 5066 # number of cc regfile writes
585system.cpu.misc_regfile_reads 7640 # number of misc regfile reads
586system.cpu.misc_regfile_writes 1 # number of misc regfile writes
587system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
588system.cpu.dcache.tags.replacements 0 # number of replacements

589system.cpu.dcache.tags.tagsinuse 81.537714 # Cycle average of tags in use

589system.cpu.dcache.tags.tagsinuse 81.537314 # Cycle average of tags in use

590system.cpu.dcache.tags.total_refs 2520 # Total number of references to valid blocks.
591system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
592system.cpu.dcache.tags.avg_refs 17.872340 # Average number of references to valid blocks.
593system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

594system.cpu.dcache.tags.occ_blocks::cpu.data 81.537714 # Average occupied blocks per requestor

594system.cpu.dcache.tags.occ_blocks::cpu.data 81.537314 # Average occupied blocks per requestor

595system.cpu.dcache.tags.occ_percent::cpu.data 0.019907 # Average percentage of cache occupancy
596system.cpu.dcache.tags.occ_percent::total 0.019907 # Average percentage of cache occupancy
597system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
598system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
599system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id
600system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
601system.cpu.dcache.tags.tag_accesses 5567 # Number of tag accesses
602system.cpu.dcache.tags.data_accesses 5567 # Number of data accesses

--- 9 unchanged lines hidden (view full) ---

612system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses
613system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses
614system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
615system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
616system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses
617system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses
618system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses
619system.cpu.dcache.overall_misses::total 193 # number of overall misses

620system.cpu.dcache.ReadReq_miss_latency::cpu.data 10226000 # number of ReadReq miss cycles
621system.cpu.dcache.ReadReq_miss_latency::total 10226000 # number of ReadReq miss cycles
622system.cpu.dcache.WriteReq_miss_latency::cpu.data 7070500 # number of WriteReq miss cycles
623system.cpu.dcache.WriteReq_miss_latency::total 7070500 # number of WriteReq miss cycles
624system.cpu.dcache.demand_miss_latency::cpu.data 17296500 # number of demand (read+write) miss cycles
625system.cpu.dcache.demand_miss_latency::total 17296500 # number of demand (read+write) miss cycles
626system.cpu.dcache.overall_miss_latency::cpu.data 17296500 # number of overall miss cycles
627system.cpu.dcache.overall_miss_latency::total 17296500 # number of overall miss cycles

620system.cpu.dcache.ReadReq_miss_latency::cpu.data 10224000 # number of ReadReq miss cycles
621system.cpu.dcache.ReadReq_miss_latency::total 10224000 # number of ReadReq miss cycles
622system.cpu.dcache.WriteReq_miss_latency::cpu.data 7069500 # number of WriteReq miss cycles
623system.cpu.dcache.WriteReq_miss_latency::total 7069500 # number of WriteReq miss cycles
624system.cpu.dcache.demand_miss_latency::cpu.data 17293500 # number of demand (read+write) miss cycles
625system.cpu.dcache.demand_miss_latency::total 17293500 # number of demand (read+write) miss cycles
626system.cpu.dcache.overall_miss_latency::cpu.data 17293500 # number of overall miss cycles
627system.cpu.dcache.overall_miss_latency::total 17293500 # number of overall miss cycles

628system.cpu.dcache.ReadReq_accesses::cpu.data 1778 # number of ReadReq accesses(hits+misses)
629system.cpu.dcache.ReadReq_accesses::total 1778 # number of ReadReq accesses(hits+misses)
630system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
631system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
632system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses
633system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses
634system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses
635system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses
636system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065804 # miss rate for ReadReq accesses
637system.cpu.dcache.ReadReq_miss_rate::total 0.065804 # miss rate for ReadReq accesses
638system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses
639system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses
640system.cpu.dcache.demand_miss_rate::cpu.data 0.071139 # miss rate for demand accesses
641system.cpu.dcache.demand_miss_rate::total 0.071139 # miss rate for demand accesses
642system.cpu.dcache.overall_miss_rate::cpu.data 0.071139 # miss rate for overall accesses
643system.cpu.dcache.overall_miss_rate::total 0.071139 # miss rate for overall accesses

644system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87401.709402 # average ReadReq miss latency
645system.cpu.dcache.ReadReq_avg_miss_latency::total 87401.709402 # average ReadReq miss latency
646system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93032.894737 # average WriteReq miss latency
647system.cpu.dcache.WriteReq_avg_miss_latency::total 93032.894737 # average WriteReq miss latency
648system.cpu.dcache.demand_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency
649system.cpu.dcache.demand_avg_miss_latency::total 89619.170984 # average overall miss latency
650system.cpu.dcache.overall_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency
651system.cpu.dcache.overall_avg_miss_latency::total 89619.170984 # average overall miss latency

644system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87384.615385 # average ReadReq miss latency
645system.cpu.dcache.ReadReq_avg_miss_latency::total 87384.615385 # average ReadReq miss latency
646system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93019.736842 # average WriteReq miss latency
647system.cpu.dcache.WriteReq_avg_miss_latency::total 93019.736842 # average WriteReq miss latency
648system.cpu.dcache.demand_avg_miss_latency::cpu.data 89603.626943 # average overall miss latency
649system.cpu.dcache.demand_avg_miss_latency::total 89603.626943 # average overall miss latency
650system.cpu.dcache.overall_avg_miss_latency::cpu.data 89603.626943 # average overall miss latency
651system.cpu.dcache.overall_avg_miss_latency::total 89603.626943 # average overall miss latency

652system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked
653system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
654system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
655system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
656system.cpu.dcache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked
657system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
658system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits
659system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits

--- 4 unchanged lines hidden (view full) ---

664system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
665system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses
666system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
667system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
668system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
669system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
670system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
671system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses

672system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6448000 # number of ReadReq MSHR miss cycles
673system.cpu.dcache.ReadReq_mshr_miss_latency::total 6448000 # number of ReadReq MSHR miss cycles
674system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6994500 # number of WriteReq MSHR miss cycles
675system.cpu.dcache.WriteReq_mshr_miss_latency::total 6994500 # number of WriteReq MSHR miss cycles
676system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13442500 # number of demand (read+write) MSHR miss cycles
677system.cpu.dcache.demand_mshr_miss_latency::total 13442500 # number of demand (read+write) MSHR miss cycles
678system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13442500 # number of overall MSHR miss cycles
679system.cpu.dcache.overall_mshr_miss_latency::total 13442500 # number of overall MSHR miss cycles

672system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6446000 # number of ReadReq MSHR miss cycles
673system.cpu.dcache.ReadReq_mshr_miss_latency::total 6446000 # number of ReadReq MSHR miss cycles
674system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6993500 # number of WriteReq MSHR miss cycles
675system.cpu.dcache.WriteReq_mshr_miss_latency::total 6993500 # number of WriteReq MSHR miss cycles
676system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13439500 # number of demand (read+write) MSHR miss cycles
677system.cpu.dcache.demand_mshr_miss_latency::total 13439500 # number of demand (read+write) MSHR miss cycles
678system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13439500 # number of overall MSHR miss cycles
679system.cpu.dcache.overall_mshr_miss_latency::total 13439500 # number of overall MSHR miss cycles

680system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036558 # mshr miss rate for ReadReq accesses
681system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036558 # mshr miss rate for ReadReq accesses
682system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses
683system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses
684system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for demand accesses
685system.cpu.dcache.demand_mshr_miss_rate::total 0.051972 # mshr miss rate for demand accesses
686system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for overall accesses
687system.cpu.dcache.overall_mshr_miss_rate::total 0.051972 # mshr miss rate for overall accesses

688system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99200 # average ReadReq mshr miss latency
689system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99200 # average ReadReq mshr miss latency
690system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92032.894737 # average WriteReq mshr miss latency
691system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92032.894737 # average WriteReq mshr miss latency
692system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency
693system.cpu.dcache.demand_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency
694system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency
695system.cpu.dcache.overall_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency

688system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99169.230769 # average ReadReq mshr miss latency
689system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99169.230769 # average ReadReq mshr miss latency
690system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92019.736842 # average WriteReq mshr miss latency
691system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92019.736842 # average WriteReq mshr miss latency
692system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95315.602837 # average overall mshr miss latency
693system.cpu.dcache.demand_avg_mshr_miss_latency::total 95315.602837 # average overall mshr miss latency
694system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95315.602837 # average overall mshr miss latency
695system.cpu.dcache.overall_avg_mshr_miss_latency::total 95315.602837 # average overall mshr miss latency

696system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
697system.cpu.icache.tags.replacements 0 # number of replacements

698system.cpu.icache.tags.tagsinuse 130.260906 # Cycle average of tags in use

698system.cpu.icache.tags.tagsinuse 130.259615 # Cycle average of tags in use

699system.cpu.icache.tags.total_refs 1641 # Total number of references to valid blocks.
700system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks.
701system.cpu.icache.tags.avg_refs 5.902878 # Average number of references to valid blocks.
702system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

703system.cpu.icache.tags.occ_blocks::cpu.inst 130.260906 # Average occupied blocks per requestor
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705system.cpu.icache.tags.occ_percent::total 0.063604 # Average percentage of cache occupancy

703system.cpu.icache.tags.occ_blocks::cpu.inst 130.259615 # Average occupied blocks per requestor
704system.cpu.icache.tags.occ_percent::cpu.inst 0.063603 # Average percentage of cache occupancy
705system.cpu.icache.tags.occ_percent::total 0.063603 # Average percentage of cache occupancy

706system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id
707system.cpu.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id
708system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
709system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id
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714system.cpu.icache.ReadReq_hits::total 1641 # number of ReadReq hits
715system.cpu.icache.demand_hits::cpu.inst 1641 # number of demand (read+write) hits
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718system.cpu.icache.overall_hits::total 1641 # number of overall hits
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720system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses
721system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses
722system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses
723system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses
724system.cpu.icache.overall_misses::total 385 # number of overall misses

725system.cpu.icache.ReadReq_miss_latency::cpu.inst 30146000 # number of ReadReq miss cycles
726system.cpu.icache.ReadReq_miss_latency::total 30146000 # number of ReadReq miss cycles
727system.cpu.icache.demand_miss_latency::cpu.inst 30146000 # number of demand (read+write) miss cycles
728system.cpu.icache.demand_miss_latency::total 30146000 # number of demand (read+write) miss cycles
729system.cpu.icache.overall_miss_latency::cpu.inst 30146000 # number of overall miss cycles
730system.cpu.icache.overall_miss_latency::total 30146000 # number of overall miss cycles

725system.cpu.icache.ReadReq_miss_latency::cpu.inst 30145000 # number of ReadReq miss cycles
726system.cpu.icache.ReadReq_miss_latency::total 30145000 # number of ReadReq miss cycles
727system.cpu.icache.demand_miss_latency::cpu.inst 30145000 # number of demand (read+write) miss cycles
728system.cpu.icache.demand_miss_latency::total 30145000 # number of demand (read+write) miss cycles
729system.cpu.icache.overall_miss_latency::cpu.inst 30145000 # number of overall miss cycles
730system.cpu.icache.overall_miss_latency::total 30145000 # number of overall miss cycles

731system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses)
732system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses)
733system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses
734system.cpu.icache.demand_accesses::total 2026 # number of demand (read+write) accesses
735system.cpu.icache.overall_accesses::cpu.inst 2026 # number of overall (read+write) accesses
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738system.cpu.icache.ReadReq_miss_rate::total 0.190030 # miss rate for ReadReq accesses
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740system.cpu.icache.demand_miss_rate::total 0.190030 # miss rate for demand accesses
741system.cpu.icache.overall_miss_rate::cpu.inst 0.190030 # miss rate for overall accesses
742system.cpu.icache.overall_miss_rate::total 0.190030 # miss rate for overall accesses

743system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78301.298701 # average ReadReq miss latency
744system.cpu.icache.ReadReq_avg_miss_latency::total 78301.298701 # average ReadReq miss latency
745system.cpu.icache.demand_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency
746system.cpu.icache.demand_avg_miss_latency::total 78301.298701 # average overall miss latency
747system.cpu.icache.overall_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency
748system.cpu.icache.overall_avg_miss_latency::total 78301.298701 # average overall miss latency

743system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78298.701299 # average ReadReq miss latency
744system.cpu.icache.ReadReq_avg_miss_latency::total 78298.701299 # average ReadReq miss latency
745system.cpu.icache.demand_avg_miss_latency::cpu.inst 78298.701299 # average overall miss latency
746system.cpu.icache.demand_avg_miss_latency::total 78298.701299 # average overall miss latency
747system.cpu.icache.overall_avg_miss_latency::cpu.inst 78298.701299 # average overall miss latency
748system.cpu.icache.overall_avg_miss_latency::total 78298.701299 # average overall miss latency

749system.cpu.icache.blocked_cycles::no_mshrs 171 # number of cycles access was blocked
750system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
751system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
752system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
753system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked
754system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
755system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # number of ReadReq MSHR hits
756system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits
757system.cpu.icache.demand_mshr_hits::cpu.inst 107 # number of demand (read+write) MSHR hits
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760system.cpu.icache.overall_mshr_hits::total 107 # number of overall MSHR hits
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762system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses
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766system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses

767system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23206500 # number of ReadReq MSHR miss cycles
768system.cpu.icache.ReadReq_mshr_miss_latency::total 23206500 # number of ReadReq MSHR miss cycles
769system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23206500 # number of demand (read+write) MSHR miss cycles
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771system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23206500 # number of overall MSHR miss cycles
772system.cpu.icache.overall_mshr_miss_latency::total 23206500 # number of overall MSHR miss cycles

767system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23205500 # number of ReadReq MSHR miss cycles
768system.cpu.icache.ReadReq_mshr_miss_latency::total 23205500 # number of ReadReq MSHR miss cycles
769system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23205500 # number of demand (read+write) MSHR miss cycles
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771system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23205500 # number of overall MSHR miss cycles
772system.cpu.icache.overall_mshr_miss_latency::total 23205500 # number of overall MSHR miss cycles

773system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for ReadReq accesses
774system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137216 # mshr miss rate for ReadReq accesses
775system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for demand accesses
776system.cpu.icache.demand_mshr_miss_rate::total 0.137216 # mshr miss rate for demand accesses
777system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for overall accesses
778system.cpu.icache.overall_mshr_miss_rate::total 0.137216 # mshr miss rate for overall accesses

779system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83476.618705 # average ReadReq mshr miss latency
780system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83476.618705 # average ReadReq mshr miss latency
781system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency
782system.cpu.icache.demand_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency
783system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency
784system.cpu.icache.overall_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency

779system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83473.021583 # average ReadReq mshr miss latency
780system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83473.021583 # average ReadReq mshr miss latency
781system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83473.021583 # average overall mshr miss latency
782system.cpu.icache.demand_avg_mshr_miss_latency::total 83473.021583 # average overall mshr miss latency
783system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83473.021583 # average overall mshr miss latency
784system.cpu.icache.overall_avg_mshr_miss_latency::total 83473.021583 # average overall mshr miss latency

785system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
786system.cpu.l2cache.tags.replacements 0 # number of replacements

787system.cpu.l2cache.tags.tagsinuse 211.897546 # Cycle average of tags in use

787system.cpu.l2cache.tags.tagsinuse 211.895854 # Cycle average of tags in use

788system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
789system.cpu.l2cache.tags.sampled_refs 418 # Sample count of references to valid blocks.
790system.cpu.l2cache.tags.avg_refs 0.002392 # Average number of references to valid blocks.
791system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

792system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.293933 # Average occupied blocks per requestor
793system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603612 # Average occupied blocks per requestor

792system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.292642 # Average occupied blocks per requestor
793system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603212 # Average occupied blocks per requestor

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796system.cpu.l2cache.tags.occ_percent::total 0.006467 # Average percentage of cache occupancy
797system.cpu.l2cache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id
798system.cpu.l2cache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id
799system.cpu.l2cache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
800system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012756 # Percentage of cache occupancy per task id
801system.cpu.l2cache.tags.tag_accesses 3770 # Number of tag accesses

--- 12 unchanged lines hidden (view full) ---

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895system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11817500 # number of demand (read+write) MSHR miss cycles
896system.cpu.l2cache.demand_mshr_miss_latency::total 31824000 # number of demand (read+write) MSHR miss cycles
897system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20006500 # number of overall MSHR miss cycles
898system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11817500 # number of overall MSHR miss cycles
899system.cpu.l2cache.overall_mshr_miss_latency::total 31824000 # number of overall MSHR miss cycles

900system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
901system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
902system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses
903system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996403 # mshr miss rate for ReadCleanReq accesses
904system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
905system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
906system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses
907system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
908system.cpu.l2cache.demand_mshr_miss_rate::total 0.997613 # mshr miss rate for demand accesses
909system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses
910system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
911system.cpu.l2cache.overall_mshr_miss_rate::total 0.997613 # mshr miss rate for overall accesses

912system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80532.894737 # average ReadExReq mshr miss latency
913system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80532.894737 # average ReadExReq mshr miss latency
914system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72229.241877 # average ReadCleanReq mshr miss latency
915system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72229.241877 # average ReadCleanReq mshr miss latency
916system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87692.307692 # average ReadSharedReq mshr miss latency
917system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87692.307692 # average ReadSharedReq mshr miss latency
918system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency
919system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency
920system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency
921system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency
922system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency
923system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency

912system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80519.736842 # average ReadExReq mshr miss latency
913system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80519.736842 # average ReadExReq mshr miss latency
914system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72225.631769 # average ReadCleanReq mshr miss latency
915system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72225.631769 # average ReadCleanReq mshr miss latency
916system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87661.538462 # average ReadSharedReq mshr miss latency
917system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87661.538462 # average ReadSharedReq mshr miss latency
918system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72225.631769 # average overall mshr miss latency
919system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83812.056738 # average overall mshr miss latency
920system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76133.971292 # average overall mshr miss latency
921system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72225.631769 # average overall mshr miss latency
922system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83812.056738 # average overall mshr miss latency
923system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76133.971292 # average overall mshr miss latency