| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000021 # Number of seconds simulated 4sim_ticks 21382500 # Number of ticks simulated 5final_tick 21382500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 22466500 # Number of ticks simulated 5final_tick 22466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 21602 # Simulator instruction rate (inst/s) 8host_op_rate 39134 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 85845466 # Simulator tick rate (ticks/s) 10host_mem_usage 271116 # Number of bytes of host memory used 11host_seconds 0.25 # Real time elapsed on the host | 7host_inst_rate 32079 # Simulator instruction rate (inst/s) 8host_op_rate 58113 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 133941475 # Simulator tick rate (ticks/s) 10host_mem_usage 269032 # Number of bytes of host memory used 11host_seconds 0.17 # Real time elapsed on the host |
| 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory 19system.physmem.bytes_read::total 26688 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 417 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 832082310 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 416041155 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1248123465 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 832082310 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 832082310 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 832082310 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 416041155 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1248123465 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 417 # Number of read requests accepted | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 19system.physmem.bytes_read::total 26752 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 418 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 789085972 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 401664701 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1190750673 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 789085972 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 789085972 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 789085972 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 401664701 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1190750673 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 418 # Number of read requests accepted |
| 34system.physmem.writeReqs 0 # Number of write requests accepted | 34system.physmem.writeReqs 0 # Number of write requests accepted |
| 35system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue | 35system.physmem.readBursts 418 # Number of DRAM read bursts, including those serviced by the write queue |
| 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 37system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM | 37system.physmem.bytesReadDRAM 26752 # Total number of bytes read from DRAM |
| 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 40system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side | 40system.physmem.bytesReadSys 26752 # Total read bytes from the system interface side |
| 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 45system.physmem.perBankRdBursts::0 31 # Per bank write bursts | 45system.physmem.perBankRdBursts::0 32 # Per bank write bursts |
| 46system.physmem.perBankRdBursts::1 1 # Per bank write bursts 47system.physmem.perBankRdBursts::2 5 # Per bank write bursts 48system.physmem.perBankRdBursts::3 8 # Per bank write bursts | 46system.physmem.perBankRdBursts::1 1 # Per bank write bursts 47system.physmem.perBankRdBursts::2 5 # Per bank write bursts 48system.physmem.perBankRdBursts::3 8 # Per bank write bursts |
| 49system.physmem.perBankRdBursts::4 51 # Per bank write bursts | 49system.physmem.perBankRdBursts::4 50 # Per bank write bursts |
| 50system.physmem.perBankRdBursts::5 44 # Per bank write bursts 51system.physmem.perBankRdBursts::6 21 # Per bank write bursts 52system.physmem.perBankRdBursts::7 37 # Per bank write bursts | 50system.physmem.perBankRdBursts::5 44 # Per bank write bursts 51system.physmem.perBankRdBursts::6 21 # Per bank write bursts 52system.physmem.perBankRdBursts::7 37 # Per bank write bursts |
| 53system.physmem.perBankRdBursts::8 23 # Per bank write bursts | 53system.physmem.perBankRdBursts::8 24 # Per bank write bursts |
| 54system.physmem.perBankRdBursts::9 71 # Per bank write bursts 55system.physmem.perBankRdBursts::10 64 # Per bank write bursts 56system.physmem.perBankRdBursts::11 16 # Per bank write bursts 57system.physmem.perBankRdBursts::12 2 # Per bank write bursts | 54system.physmem.perBankRdBursts::9 71 # Per bank write bursts 55system.physmem.perBankRdBursts::10 64 # Per bank write bursts 56system.physmem.perBankRdBursts::11 16 # Per bank write bursts 57system.physmem.perBankRdBursts::12 2 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::13 19 # Per bank write bursts 59system.physmem.perBankRdBursts::14 7 # Per bank write bursts | 58system.physmem.perBankRdBursts::13 20 # Per bank write bursts 59system.physmem.perBankRdBursts::14 6 # Per bank write bursts |
| 60system.physmem.perBankRdBursts::15 17 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 60system.physmem.perBankRdBursts::15 17 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 21259500 # Total gap between requests | 79system.physmem.totGap 22337000 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 86system.physmem.readPktSize::6 417 # Read request sizes (log2) | 86system.physmem.readPktSize::6 418 # Read request sizes (log2) |
| 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) | 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 94system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 125 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see |
| 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 190system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 248.742268 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 161.877699 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 262.561948 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 36 37.11% 37.11% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 27 27.84% 64.95% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 16 16.49% 81.44% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 4 4.12% 85.57% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 2 2.06% 87.63% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 4 4.12% 91.75% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 2 2.06% 93.81% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 1 1.03% 94.85% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation 204system.physmem.totQLat 5040250 # Total ticks spent queuing 205system.physmem.totMemAccLat 12859000 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 12086.93 # Average queueing delay per DRAM burst | 190system.physmem.bytesPerActivate::samples 95 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 246.568421 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 159.892164 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 259.040400 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 37 38.95% 38.95% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 23 24.21% 63.16% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 16 16.84% 80.00% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 6 6.32% 86.32% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 2 2.11% 88.42% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 3 3.16% 91.58% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 2 2.11% 93.68% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 2 2.11% 95.79% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 4 4.21% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 95 # Bytes accessed per row activation 204system.physmem.totQLat 6803250 # Total ticks spent queuing 205system.physmem.totMemAccLat 14640750 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 2090000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 16275.72 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 30836.93 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1248.12 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgMemAccLat 35025.72 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1190.75 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 1248.12 # Average system read bandwidth in MiByte/s | 212system.physmem.avgRdBWSys 1190.75 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 215system.physmem.busUtil 9.75 # Data bus utilization in percentage 216system.physmem.busUtilRead 9.75 # Data bus utilization in percentage for reads | 215system.physmem.busUtil 9.30 # Data bus utilization in percentage 216system.physmem.busUtilRead 9.30 # Data bus utilization in percentage for reads |
| 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 218system.physmem.avgRdQLen 1.67 # Average read queue length when enqueuing | 218system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing |
| 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 220system.physmem.readRowHits 309 # Number of row buffer hits during reads | 220system.physmem.readRowHits 310 # Number of row buffer hits during reads |
| 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 222system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads | 222system.physmem.readRowHitRate 74.16 # Row buffer hit rate for reads |
| 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 50982.01 # Average gap between requests 225system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 173880 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 94875 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 912600 # Energy for read commands per rank (pJ) | 224system.physmem.avgGap 53437.80 # Average gap between requests 225system.physmem.pageHitRate 74.16 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 285600 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 1413720 # Energy for read commands per rank (pJ) |
| 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 230system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) 233system.physmem_0.totalEnergy 13023390 # Total energy per rank (pJ) 234system.physmem_0.averagePower 822.573188 # Core power per rank (mW) 235system.physmem_0.memoryStateTime::IDLE 13750 # Time in different power states | 230system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 2399130 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 30240 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 7645980 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 138240 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 13267425 # Total energy per rank (pJ) 237system.physmem_0.averagePower 590.516301 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 17035500 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states |
| 236system.physmem_0.memoryStateTime::REF 520000 # Time in different power states | 240system.physmem_0.memoryStateTime::REF 520000 # Time in different power states |
| 237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 238system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states 239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 240system.physmem_1.actEnergy 415800 # Energy for activate commands per rank (pJ) 241system.physmem_1.preEnergy 226875 # Energy for precharge commands per rank (pJ) 242system.physmem_1.readEnergy 1497600 # Energy for read commands per rank (pJ) | 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 359250 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 4794250 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 16769500 # Time in different power states 245system.physmem_1.actEnergy 485520 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 235290 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 1570800 # Energy for read commands per rank (pJ) |
| 243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 244system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 245system.physmem_1.actBackEnergy 10696050 # Energy for active background per rank (pJ) 246system.physmem_1.preBackEnergy 117000 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 13970445 # Total energy per rank (pJ) 248system.physmem_1.averagePower 882.390336 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 103000 # Time in different power states | 249system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 2963430 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 82560 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 7182000 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 13750320 # Total energy per rank (pJ) 256system.physmem_1.averagePower 612.009347 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 14672000 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 109000 # Time in different power states |
| 250system.physmem_1.memoryStateTime::REF 520000 # Time in different power states | 259system.physmem_1.memoryStateTime::REF 520000 # Time in different power states |
| 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 252system.physmem_1.memoryStateTime::ACT 15223250 # Time in different power states 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 254system.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states 255system.cpu.branchPred.lookups 3511 # Number of BP lookups 256system.cpu.branchPred.condPredicted 3511 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 567 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 2933 # Number of BTB lookups | 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 3500 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 6091750 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 15742250 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 3488 # Number of BP lookups 266system.cpu.branchPred.condPredicted 3488 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 571 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 2960 # Number of BTB lookups |
| 259system.cpu.branchPred.BTBHits 0 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage | 269system.cpu.branchPred.BTBHits 0 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage |
| 262system.cpu.branchPred.usedRAS 414 # Number of times the RAS was used to get a target. | 272system.cpu.branchPred.usedRAS 360 # Number of times the RAS was used to get a target. |
| 263system.cpu.branchPred.RASInCorrect 94 # Number of incorrect RAS predictions. | 273system.cpu.branchPred.RASInCorrect 94 # Number of incorrect RAS predictions. |
| 264system.cpu.branchPred.indirectLookups 2933 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 496 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 2437 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 406 # Number of mispredicted indirect branches. | 274system.cpu.branchPred.indirectLookups 2960 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 483 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 2477 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 410 # Number of mispredicted indirect branches. |
| 268system.cpu_clk_domain.clock 500 # Clock period in ticks | 278system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 269system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states | 279system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states |
| 270system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 280system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 271system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states 272system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states | 281system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states 282system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states |
| 273system.cpu.workload.num_syscalls 11 # Number of system calls | 283system.cpu.workload.num_syscalls 11 # Number of system calls |
| 274system.cpu.pwrStateResidencyTicks::ON 21382500 # Cumulative time (in ticks) in various power states 275system.cpu.numCycles 42766 # number of cpu cycles simulated | 284system.cpu.pwrStateResidencyTicks::ON 22466500 # Cumulative time (in ticks) in various power states 285system.cpu.numCycles 44934 # number of cpu cycles simulated |
| 276system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 277system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 286system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 287system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 278system.cpu.fetch.icacheStallCycles 11494 # Number of cycles fetch is stalled on an Icache miss 279system.cpu.fetch.Insts 15919 # Number of instructions fetch has processed 280system.cpu.fetch.Branches 3511 # Number of branches that fetch encountered 281system.cpu.fetch.predictedBranches 910 # Number of branches that fetch has predicted taken 282system.cpu.fetch.Cycles 9718 # Number of cycles fetch has run and was not squashing or blocked 283system.cpu.fetch.SquashCycles 1335 # Number of cycles fetch has spent squashing 284system.cpu.fetch.MiscStallCycles 93 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 288system.cpu.fetch.icacheStallCycles 12177 # Number of cycles fetch is stalled on an Icache miss 289system.cpu.fetch.Insts 15717 # Number of instructions fetch has processed 290system.cpu.fetch.Branches 3488 # Number of branches that fetch encountered 291system.cpu.fetch.predictedBranches 843 # Number of branches that fetch has predicted taken 292system.cpu.fetch.Cycles 10477 # Number of cycles fetch has run and was not squashing or blocked 293system.cpu.fetch.SquashCycles 1321 # Number of cycles fetch has spent squashing 294system.cpu.fetch.MiscStallCycles 78 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 285system.cpu.fetch.PendingTrapStallCycles 1414 # Number of stall cycles due to pending traps 286system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions | 295system.cpu.fetch.PendingTrapStallCycles 1414 # Number of stall cycles due to pending traps 296system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions |
| 287system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR 288system.cpu.fetch.CacheLines 2042 # Number of cache lines fetched 289system.cpu.fetch.IcacheSquashes 273 # Number of outstanding Icache misses that were squashed 290system.cpu.fetch.rateDist::samples 23431 # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::mean 1.223593 # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::stdev 2.745730 # Number of instructions fetched each cycle (Total) | 297system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR 298system.cpu.fetch.CacheLines 2026 # Number of cache lines fetched 299system.cpu.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed 300system.cpu.fetch.rateDist::samples 24836 # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::mean 1.141770 # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::stdev 2.668775 # Number of instructions fetched each cycle (Total) |
| 293system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 303system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 294system.cpu.fetch.rateDist::0 19161 81.78% 81.78% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::1 166 0.71% 82.48% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::2 156 0.67% 83.15% # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::3 235 1.00% 84.15% # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::4 218 0.93% 85.08% # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::5 215 0.92% 86.00% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::6 266 1.14% 87.14% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::7 168 0.72% 87.85% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::8 2846 12.15% 100.00% # Number of instructions fetched each cycle (Total) | 304system.cpu.fetch.rateDist::0 20599 82.94% 82.94% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::1 175 0.70% 83.64% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::2 165 0.66% 84.31% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::3 225 0.91% 85.22% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::4 209 0.84% 86.06% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::5 222 0.89% 86.95% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::6 269 1.08% 88.03% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::7 159 0.64% 88.67% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::8 2813 11.33% 100.00% # Number of instructions fetched each cycle (Total) |
| 303system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 313system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 306system.cpu.fetch.rateDist::total 23431 # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.branchRate 0.082098 # Number of branch fetches per cycle 308system.cpu.fetch.rate 0.372235 # Number of inst fetches per cycle 309system.cpu.decode.IdleCycles 11586 # Number of cycles decode is idle 310system.cpu.decode.BlockedCycles 7313 # Number of cycles decode is blocked 311system.cpu.decode.RunCycles 3407 # Number of cycles decode is running 312system.cpu.decode.UnblockCycles 458 # Number of cycles decode is unblocking 313system.cpu.decode.SquashCycles 667 # Number of cycles decode is squashing 314system.cpu.decode.DecodedInsts 26631 # Number of instructions handled by decode 315system.cpu.rename.SquashCycles 667 # Number of cycles rename is squashing 316system.cpu.rename.IdleCycles 11849 # Number of cycles rename is idle 317system.cpu.rename.BlockCycles 2059 # Number of cycles rename is blocking 318system.cpu.rename.serializeStallCycles 1032 # count of cycles rename stalled for serializing inst 319system.cpu.rename.RunCycles 3561 # Number of cycles rename is running 320system.cpu.rename.UnblockCycles 4263 # Number of cycles rename is unblocking 321system.cpu.rename.RenamedInsts 25112 # Number of instructions processed by rename 322system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full 323system.cpu.rename.IQFullEvents 80 # Number of times rename has blocked due to IQ full 324system.cpu.rename.SQFullEvents 4127 # Number of times rename has blocked due to SQ full 325system.cpu.rename.RenamedOperands 28145 # Number of destination operands rename has renamed 326system.cpu.rename.RenameLookups 61260 # Number of register rename lookups that rename has made 327system.cpu.rename.int_rename_lookups 35084 # Number of integer rename lookups | 316system.cpu.fetch.rateDist::total 24836 # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.branchRate 0.077625 # Number of branch fetches per cycle 318system.cpu.fetch.rate 0.349780 # Number of inst fetches per cycle 319system.cpu.decode.IdleCycles 12221 # Number of cycles decode is idle 320system.cpu.decode.BlockedCycles 8128 # Number of cycles decode is blocked 321system.cpu.decode.RunCycles 3370 # Number of cycles decode is running 322system.cpu.decode.UnblockCycles 457 # Number of cycles decode is unblocking 323system.cpu.decode.SquashCycles 660 # Number of cycles decode is squashing 324system.cpu.decode.DecodedInsts 26405 # Number of instructions handled by decode 325system.cpu.rename.SquashCycles 660 # Number of cycles rename is squashing 326system.cpu.rename.IdleCycles 12481 # Number of cycles rename is idle 327system.cpu.rename.BlockCycles 1971 # Number of cycles rename is blocking 328system.cpu.rename.serializeStallCycles 1213 # count of cycles rename stalled for serializing inst 329system.cpu.rename.RunCycles 3524 # Number of cycles rename is running 330system.cpu.rename.UnblockCycles 4987 # Number of cycles rename is unblocking 331system.cpu.rename.RenamedInsts 24875 # Number of instructions processed by rename 332system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full 333system.cpu.rename.IQFullEvents 82 # Number of times rename has blocked due to IQ full 334system.cpu.rename.SQFullEvents 4849 # Number of times rename has blocked due to SQ full 335system.cpu.rename.RenamedOperands 27762 # Number of destination operands rename has renamed 336system.cpu.rename.RenameLookups 60616 # Number of register rename lookups that rename has made 337system.cpu.rename.int_rename_lookups 34638 # Number of integer rename lookups |
| 328system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 329system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed | 338system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 339system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed |
| 330system.cpu.rename.UndoneMaps 17082 # Number of HB maps that are undone due to squashing 331system.cpu.rename.serializingInsts 24 # count of serializing insts renamed 332system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed 333system.cpu.rename.skidInsts 1417 # count of insts added to the skid buffer 334system.cpu.memDep0.insertedLoads 2745 # Number of loads inserted to the mem dependence unit. 335system.cpu.memDep0.insertedStores 1552 # Number of stores inserted to the mem dependence unit. 336system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. 337system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. 338system.cpu.iq.iqInstsAdded 21890 # Number of instructions added to the IQ (excludes non-spec) 339system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ 340system.cpu.iq.iqInstsIssued 18162 # Number of instructions issued 341system.cpu.iq.iqSquashedInstsIssued 138 # Number of squashed instructions issued 342system.cpu.iq.iqSquashedInstsExamined 12165 # Number of squashed instructions iterated over during squash; mainly for profiling 343system.cpu.iq.iqSquashedOperandsExamined 16733 # Number of squashed operands that are examined and possibly removed from graph 344system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed 345system.cpu.iq.issued_per_cycle::samples 23431 # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::mean 0.775127 # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::stdev 1.748484 # Number of insts issued each cycle | 340system.cpu.rename.UndoneMaps 16699 # Number of HB maps that are undone due to squashing 341system.cpu.rename.serializingInsts 25 # count of serializing insts renamed 342system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed 343system.cpu.rename.skidInsts 1436 # count of insts added to the skid buffer 344system.cpu.memDep0.insertedLoads 2622 # Number of loads inserted to the mem dependence unit. 345system.cpu.memDep0.insertedStores 1598 # Number of stores inserted to the mem dependence unit. 346system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. 347system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores. 348system.cpu.iq.iqInstsAdded 21775 # Number of instructions added to the IQ (excludes non-spec) 349system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ 350system.cpu.iq.iqInstsIssued 18112 # Number of instructions issued 351system.cpu.iq.iqSquashedInstsIssued 144 # Number of squashed instructions issued 352system.cpu.iq.iqSquashedInstsExamined 12051 # Number of squashed instructions iterated over during squash; mainly for profiling 353system.cpu.iq.iqSquashedOperandsExamined 16553 # Number of squashed operands that are examined and possibly removed from graph 354system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed 355system.cpu.iq.issued_per_cycle::samples 24836 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::mean 0.729264 # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::stdev 1.710819 # Number of insts issued each cycle |
| 348system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 358system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 349system.cpu.iq.issued_per_cycle::0 18255 77.91% 77.91% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::1 1208 5.16% 83.07% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::2 874 3.73% 86.80% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::3 566 2.42% 89.21% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::4 836 3.57% 92.78% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::5 600 2.56% 95.34% # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::6 613 2.62% 97.96% # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::7 346 1.48% 99.43% # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::8 133 0.57% 100.00% # Number of insts issued each cycle | 359system.cpu.iq.issued_per_cycle::0 19691 79.28% 79.28% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::1 1200 4.83% 84.12% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::2 866 3.49% 87.60% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::3 575 2.32% 89.92% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::4 815 3.28% 93.20% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::5 575 2.32% 95.51% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::6 614 2.47% 97.99% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::7 364 1.47% 99.45% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::8 136 0.55% 100.00% # Number of insts issued each cycle |
| 358system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 368system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 361system.cpu.iq.issued_per_cycle::total 23431 # Number of insts issued each cycle | 371system.cpu.iq.issued_per_cycle::total 24836 # Number of insts issued each cycle |
| 362system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 372system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 363system.cpu.iq.fu_full::IntAlu 213 76.07% 76.07% # attempts to use FU when none available 364system.cpu.iq.fu_full::IntMult 0 0.00% 76.07% # attempts to use FU when none available 365system.cpu.iq.fu_full::IntDiv 0 0.00% 76.07% # attempts to use FU when none available 366system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.07% # attempts to use FU when none available 367system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.07% # attempts to use FU when none available 368system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.07% # attempts to use FU when none available 369system.cpu.iq.fu_full::FloatMult 0 0.00% 76.07% # attempts to use FU when none available 370system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.07% # attempts to use FU when none available 371system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.07% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.07% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.07% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.07% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.07% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.07% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.07% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdMult 0 0.00% 76.07% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.07% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdShift 0 0.00% 76.07% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.07% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.07% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.07% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.07% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.07% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.07% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.07% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.07% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.07% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.07% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.07% # attempts to use FU when none available 392system.cpu.iq.fu_full::MemRead 51 18.21% 94.29% # attempts to use FU when none available 393system.cpu.iq.fu_full::MemWrite 16 5.71% 100.00% # attempts to use FU when none available | 373system.cpu.iq.fu_full::IntAlu 223 79.93% 79.93% # attempts to use FU when none available 374system.cpu.iq.fu_full::IntMult 0 0.00% 79.93% # attempts to use FU when none available 375system.cpu.iq.fu_full::IntDiv 0 0.00% 79.93% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.93% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.93% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.93% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatMult 0 0.00% 79.93% # attempts to use FU when none available 380system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.93% # attempts to use FU when none available 381system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.93% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.93% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.93% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.93% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.93% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.93% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.93% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdMult 0 0.00% 79.93% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.93% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdShift 0 0.00% 79.93% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.93% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.93% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.93% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.93% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.93% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.93% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.93% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.93% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.93% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.93% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.93% # attempts to use FU when none available 402system.cpu.iq.fu_full::MemRead 41 14.70% 94.62% # attempts to use FU when none available 403system.cpu.iq.fu_full::MemWrite 15 5.38% 100.00% # attempts to use FU when none available |
| 394system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 395system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 396system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued | 404system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 405system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 406system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued |
| 397system.cpu.iq.FU_type_0::IntAlu 14483 79.74% 79.75% # Type of FU issued 398system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.79% # Type of FU issued 399system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.83% # Type of FU issued 400system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.83% # Type of FU issued 401system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.83% # Type of FU issued 402system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.83% # Type of FU issued 403system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.83% # Type of FU issued 404system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.83% # Type of FU issued 405system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.83% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.83% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.83% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.83% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.83% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.83% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.83% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.83% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.83% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.83% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.83% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.83% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.83% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.83% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.83% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.83% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.83% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.83% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.83% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.83% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.83% # Type of FU issued 426system.cpu.iq.FU_type_0::MemRead 2327 12.81% 92.64% # Type of FU issued 427system.cpu.iq.FU_type_0::MemWrite 1337 7.36% 100.00% # Type of FU issued | 407system.cpu.iq.FU_type_0::IntAlu 14478 79.94% 79.95% # Type of FU issued 408system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.98% # Type of FU issued 409system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.02% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.02% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.02% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.02% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.02% # Type of FU issued 414system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.02% # Type of FU issued 415system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.02% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.02% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.02% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.02% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.02% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.02% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.02% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.02% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.02% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.02% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.02% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.02% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.02% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.02% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.02% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.02% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.02% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.02% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.02% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.02% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.02% # Type of FU issued 436system.cpu.iq.FU_type_0::MemRead 2258 12.47% 92.49% # Type of FU issued 437system.cpu.iq.FU_type_0::MemWrite 1361 7.51% 100.00% # Type of FU issued |
| 428system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 429system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 438system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 430system.cpu.iq.FU_type_0::total 18162 # Type of FU issued 431system.cpu.iq.rate 0.424683 # Inst issue rate 432system.cpu.iq.fu_busy_cnt 280 # FU busy when requested 433system.cpu.iq.fu_busy_rate 0.015417 # FU busy rate (busy events/executed inst) 434system.cpu.iq.int_inst_queue_reads 60165 # Number of integer instruction queue reads 435system.cpu.iq.int_inst_queue_writes 34082 # Number of integer instruction queue writes 436system.cpu.iq.int_inst_queue_wakeup_accesses 16453 # Number of integer instruction queue wakeup accesses | 440system.cpu.iq.FU_type_0::total 18112 # Type of FU issued 441system.cpu.iq.rate 0.403080 # Inst issue rate 442system.cpu.iq.fu_busy_cnt 279 # FU busy when requested 443system.cpu.iq.fu_busy_rate 0.015404 # FU busy rate (busy events/executed inst) 444system.cpu.iq.int_inst_queue_reads 61475 # Number of integer instruction queue reads 445system.cpu.iq.int_inst_queue_writes 33854 # Number of integer instruction queue writes 446system.cpu.iq.int_inst_queue_wakeup_accesses 16418 # Number of integer instruction queue wakeup accesses |
| 437system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 438system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes 439system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses | 447system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 448system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes 449system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses |
| 440system.cpu.iq.int_alu_accesses 18436 # Number of integer alu accesses | 450system.cpu.iq.int_alu_accesses 18385 # Number of integer alu accesses |
| 441system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses | 451system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses |
| 442system.cpu.iew.lsq.thread0.forwLoads 200 # Number of loads that had data forwarded from stores | 452system.cpu.iew.lsq.thread0.forwLoads 215 # Number of loads that had data forwarded from stores |
| 443system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 453system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 444system.cpu.iew.lsq.thread0.squashedLoads 1692 # Number of loads squashed 445system.cpu.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed | 454system.cpu.iew.lsq.thread0.squashedLoads 1569 # Number of loads squashed 455system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed |
| 446system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations | 456system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations |
| 447system.cpu.iew.lsq.thread0.squashedStores 617 # Number of stores squashed | 457system.cpu.iew.lsq.thread0.squashedStores 663 # Number of stores squashed |
| 448system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 449system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 450system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled | 458system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 459system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 460system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled |
| 451system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked | 461system.cpu.iew.lsq.thread0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked |
| 452system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 462system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 453system.cpu.iew.iewSquashCycles 667 # Number of cycles IEW is squashing 454system.cpu.iew.iewBlockCycles 1486 # Number of cycles IEW is blocking 455system.cpu.iew.iewUnblockCycles 141 # Number of cycles IEW is unblocking 456system.cpu.iew.iewDispatchedInsts 21912 # Number of instructions dispatched to IQ 457system.cpu.iew.iewDispSquashedInsts 9 # Number of squashed instructions skipped by dispatch 458system.cpu.iew.iewDispLoadInsts 2745 # Number of dispatched load instructions 459system.cpu.iew.iewDispStoreInsts 1552 # Number of dispatched store instructions 460system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions | 463system.cpu.iew.iewSquashCycles 660 # Number of cycles IEW is squashing 464system.cpu.iew.iewBlockCycles 1482 # Number of cycles IEW is blocking 465system.cpu.iew.iewUnblockCycles 153 # Number of cycles IEW is unblocking 466system.cpu.iew.iewDispatchedInsts 21798 # Number of instructions dispatched to IQ 467system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch 468system.cpu.iew.iewDispLoadInsts 2622 # Number of dispatched load instructions 469system.cpu.iew.iewDispStoreInsts 1598 # Number of dispatched store instructions 470system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions |
| 461system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall | 471system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall |
| 462system.cpu.iew.iewLSQFullEvents 140 # Number of times the LSQ has become full, causing a stall | 472system.cpu.iew.iewLSQFullEvents 152 # Number of times the LSQ has become full, causing a stall |
| 463system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations | 473system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations |
| 464system.cpu.iew.predictedTakenIncorrect 120 # Number of branches that were predicted taken incorrectly 465system.cpu.iew.predictedNotTakenIncorrect 685 # Number of branches that were predicted not taken incorrectly 466system.cpu.iew.branchMispredicts 805 # Number of branch mispredicts detected at execute 467system.cpu.iew.iewExecutedInsts 17078 # Number of executed instructions 468system.cpu.iew.iewExecLoadInsts 2088 # Number of load instructions executed 469system.cpu.iew.iewExecSquashedInsts 1084 # Number of squashed instructions skipped in execute | 474system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly 475system.cpu.iew.predictedNotTakenIncorrect 680 # Number of branches that were predicted not taken incorrectly 476system.cpu.iew.branchMispredicts 798 # Number of branch mispredicts detected at execute 477system.cpu.iew.iewExecutedInsts 17038 # Number of executed instructions 478system.cpu.iew.iewExecLoadInsts 2047 # Number of load instructions executed 479system.cpu.iew.iewExecSquashedInsts 1074 # Number of squashed instructions skipped in execute |
| 470system.cpu.iew.exec_swp 0 # number of swp insts executed 471system.cpu.iew.exec_nop 0 # number of nop insts executed | 480system.cpu.iew.exec_swp 0 # number of swp insts executed 481system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 472system.cpu.iew.exec_refs 3333 # number of memory reference insts executed 473system.cpu.iew.exec_branches 1727 # Number of branches executed 474system.cpu.iew.exec_stores 1245 # Number of stores executed 475system.cpu.iew.exec_rate 0.399336 # Inst execution rate 476system.cpu.iew.wb_sent 16776 # cumulative count of insts sent to commit 477system.cpu.iew.wb_count 16457 # cumulative count of insts written-back 478system.cpu.iew.wb_producers 11050 # num instructions producing a value 479system.cpu.iew.wb_consumers 17247 # num instructions consuming a value 480system.cpu.iew.wb_rate 0.384815 # insts written-back per cycle 481system.cpu.iew.wb_fanout 0.640691 # average fanout of values written-back 482system.cpu.commit.commitSquashedInsts 12164 # The number of squashed insts skipped by commit | 482system.cpu.iew.exec_refs 3306 # number of memory reference insts executed 483system.cpu.iew.exec_branches 1731 # Number of branches executed 484system.cpu.iew.exec_stores 1259 # Number of stores executed 485system.cpu.iew.exec_rate 0.379178 # Inst execution rate 486system.cpu.iew.wb_sent 16737 # cumulative count of insts sent to commit 487system.cpu.iew.wb_count 16422 # cumulative count of insts written-back 488system.cpu.iew.wb_producers 11019 # num instructions producing a value 489system.cpu.iew.wb_consumers 17148 # num instructions consuming a value 490system.cpu.iew.wb_rate 0.365469 # insts written-back per cycle 491system.cpu.iew.wb_fanout 0.642582 # average fanout of values written-back 492system.cpu.commit.commitSquashedInsts 12050 # The number of squashed insts skipped by commit |
| 483system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards | 493system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards |
| 484system.cpu.commit.branchMispredicts 655 # The number of times a branch was mispredicted 485system.cpu.commit.committed_per_cycle::samples 21365 # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::mean 0.456213 # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::stdev 1.347578 # Number of insts commited each cycle | 494system.cpu.commit.branchMispredicts 648 # The number of times a branch was mispredicted 495system.cpu.commit.committed_per_cycle::samples 22793 # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::mean 0.427631 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::stdev 1.307645 # Number of insts commited each cycle |
| 488system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 498system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 489system.cpu.commit.committed_per_cycle::0 18118 84.80% 84.80% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::1 989 4.63% 89.43% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::2 572 2.68% 92.11% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::3 729 3.41% 95.52% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::4 380 1.78% 97.30% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::5 132 0.62% 97.92% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::6 120 0.56% 98.48% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::7 73 0.34% 98.82% # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::8 252 1.18% 100.00% # Number of insts commited each cycle | 499system.cpu.commit.committed_per_cycle::0 19538 85.72% 85.72% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::1 1001 4.39% 90.11% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::2 566 2.48% 92.59% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::3 727 3.19% 95.78% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::4 384 1.68% 97.47% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::5 133 0.58% 98.05% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::6 124 0.54% 98.60% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::7 72 0.32% 98.91% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::8 248 1.09% 100.00% # Number of insts commited each cycle |
| 498system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 508system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 501system.cpu.commit.committed_per_cycle::total 21365 # Number of insts commited each cycle | 511system.cpu.commit.committed_per_cycle::total 22793 # Number of insts commited each cycle |
| 502system.cpu.commit.committedInsts 5380 # Number of instructions committed 503system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed 504system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 505system.cpu.commit.refs 1988 # Number of memory references committed 506system.cpu.commit.loads 1053 # Number of loads committed 507system.cpu.commit.membars 0 # Number of memory barriers committed 508system.cpu.commit.branches 1208 # Number of branches committed 509system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 539system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction 542system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction 543system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction 544system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 545system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 546system.cpu.commit.op_class_0::total 9747 # Class of committed instruction | 512system.cpu.commit.committedInsts 5380 # Number of instructions committed 513system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed 514system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 515system.cpu.commit.refs 1988 # Number of memory references committed 516system.cpu.commit.loads 1053 # Number of loads committed 517system.cpu.commit.membars 0 # Number of memory barriers committed 518system.cpu.commit.branches 1208 # Number of branches committed 519system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 549system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction 552system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction 553system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction 554system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::total 9747 # Class of committed instruction |
| 547system.cpu.commit.bw_lim_events 252 # number cycles where commit BW limit reached 548system.cpu.rob.rob_reads 43024 # The number of ROB reads 549system.cpu.rob.rob_writes 45919 # The number of ROB writes 550system.cpu.timesIdled 159 # Number of times that the entire CPU went into an idle state and unscheduled itself 551system.cpu.idleCycles 19335 # Total number of cycles that the CPU has spent unscheduled due to idling | 557system.cpu.commit.bw_lim_events 248 # number cycles where commit BW limit reached 558system.cpu.rob.rob_reads 44342 # The number of ROB reads 559system.cpu.rob.rob_writes 45672 # The number of ROB writes 560system.cpu.timesIdled 156 # Number of times that the entire CPU went into an idle state and unscheduled itself 561system.cpu.idleCycles 20098 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 552system.cpu.committedInsts 5380 # Number of Instructions Simulated 553system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated | 562system.cpu.committedInsts 5380 # Number of Instructions Simulated 563system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated |
| 554system.cpu.cpi 7.949071 # CPI: Cycles Per Instruction 555system.cpu.cpi_total 7.949071 # CPI: Total CPI of All Threads 556system.cpu.ipc 0.125801 # IPC: Instructions Per Cycle 557system.cpu.ipc_total 0.125801 # IPC: Total IPC of All Threads 558system.cpu.int_regfile_reads 21733 # number of integer regfile reads 559system.cpu.int_regfile_writes 13291 # number of integer regfile writes | 564system.cpu.cpi 8.352045 # CPI: Cycles Per Instruction 565system.cpu.cpi_total 8.352045 # CPI: Total CPI of All Threads 566system.cpu.ipc 0.119731 # IPC: Instructions Per Cycle 567system.cpu.ipc_total 0.119731 # IPC: Total IPC of All Threads 568system.cpu.int_regfile_reads 21663 # number of integer regfile reads 569system.cpu.int_regfile_writes 13219 # number of integer regfile writes |
| 560system.cpu.fp_regfile_reads 4 # number of floating regfile reads | 570system.cpu.fp_regfile_reads 4 # number of floating regfile reads |
| 561system.cpu.cc_regfile_reads 8307 # number of cc regfile reads 562system.cpu.cc_regfile_writes 5092 # number of cc regfile writes 563system.cpu.misc_regfile_reads 7667 # number of misc regfile reads | 571system.cpu.cc_regfile_reads 8286 # number of cc regfile reads 572system.cpu.cc_regfile_writes 5066 # number of cc regfile writes 573system.cpu.misc_regfile_reads 7640 # number of misc regfile reads |
| 564system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 574system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 565system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states | 575system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states |
| 566system.cpu.dcache.tags.replacements 0 # number of replacements | 576system.cpu.dcache.tags.replacements 0 # number of replacements |
| 567system.cpu.dcache.tags.tagsinuse 81.328051 # Cycle average of tags in use 568system.cpu.dcache.tags.total_refs 2579 # Total number of references to valid blocks. 569system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks. 570system.cpu.dcache.tags.avg_refs 18.553957 # Average number of references to valid blocks. | 577system.cpu.dcache.tags.tagsinuse 81.537714 # Cycle average of tags in use 578system.cpu.dcache.tags.total_refs 2520 # Total number of references to valid blocks. 579system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 580system.cpu.dcache.tags.avg_refs 17.872340 # Average number of references to valid blocks. |
| 571system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 581system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 572system.cpu.dcache.tags.occ_blocks::cpu.data 81.328051 # Average occupied blocks per requestor 573system.cpu.dcache.tags.occ_percent::cpu.data 0.019855 # Average percentage of cache occupancy 574system.cpu.dcache.tags.occ_percent::total 0.019855 # Average percentage of cache occupancy 575system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id | 582system.cpu.dcache.tags.occ_blocks::cpu.data 81.537714 # Average occupied blocks per requestor 583system.cpu.dcache.tags.occ_percent::cpu.data 0.019907 # Average percentage of cache occupancy 584system.cpu.dcache.tags.occ_percent::total 0.019907 # Average percentage of cache occupancy 585system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id |
| 576system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id | 586system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id |
| 577system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 578system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id 579system.cpu.dcache.tags.tag_accesses 5679 # Number of tag accesses 580system.cpu.dcache.tags.data_accesses 5679 # Number of data accesses 581system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states 582system.cpu.dcache.ReadReq_hits::cpu.data 1719 # number of ReadReq hits 583system.cpu.dcache.ReadReq_hits::total 1719 # number of ReadReq hits 584system.cpu.dcache.WriteReq_hits::cpu.data 860 # number of WriteReq hits 585system.cpu.dcache.WriteReq_hits::total 860 # number of WriteReq hits 586system.cpu.dcache.demand_hits::cpu.data 2579 # number of demand (read+write) hits 587system.cpu.dcache.demand_hits::total 2579 # number of demand (read+write) hits 588system.cpu.dcache.overall_hits::cpu.data 2579 # number of overall hits 589system.cpu.dcache.overall_hits::total 2579 # number of overall hits 590system.cpu.dcache.ReadReq_misses::cpu.data 116 # number of ReadReq misses 591system.cpu.dcache.ReadReq_misses::total 116 # number of ReadReq misses 592system.cpu.dcache.WriteReq_misses::cpu.data 75 # number of WriteReq misses 593system.cpu.dcache.WriteReq_misses::total 75 # number of WriteReq misses 594system.cpu.dcache.demand_misses::cpu.data 191 # number of demand (read+write) misses 595system.cpu.dcache.demand_misses::total 191 # number of demand (read+write) misses 596system.cpu.dcache.overall_misses::cpu.data 191 # number of overall misses 597system.cpu.dcache.overall_misses::total 191 # number of overall misses 598system.cpu.dcache.ReadReq_miss_latency::cpu.data 9465500 # number of ReadReq miss cycles 599system.cpu.dcache.ReadReq_miss_latency::total 9465500 # number of ReadReq miss cycles 600system.cpu.dcache.WriteReq_miss_latency::cpu.data 6317000 # number of WriteReq miss cycles 601system.cpu.dcache.WriteReq_miss_latency::total 6317000 # number of WriteReq miss cycles 602system.cpu.dcache.demand_miss_latency::cpu.data 15782500 # number of demand (read+write) miss cycles 603system.cpu.dcache.demand_miss_latency::total 15782500 # number of demand (read+write) miss cycles 604system.cpu.dcache.overall_miss_latency::cpu.data 15782500 # number of overall miss cycles 605system.cpu.dcache.overall_miss_latency::total 15782500 # number of overall miss cycles 606system.cpu.dcache.ReadReq_accesses::cpu.data 1835 # number of ReadReq accesses(hits+misses) 607system.cpu.dcache.ReadReq_accesses::total 1835 # number of ReadReq accesses(hits+misses) | 587system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id 588system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id 589system.cpu.dcache.tags.tag_accesses 5567 # Number of tag accesses 590system.cpu.dcache.tags.data_accesses 5567 # Number of data accesses 591system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states 592system.cpu.dcache.ReadReq_hits::cpu.data 1661 # number of ReadReq hits 593system.cpu.dcache.ReadReq_hits::total 1661 # number of ReadReq hits 594system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits 595system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits 596system.cpu.dcache.demand_hits::cpu.data 2520 # number of demand (read+write) hits 597system.cpu.dcache.demand_hits::total 2520 # number of demand (read+write) hits 598system.cpu.dcache.overall_hits::cpu.data 2520 # number of overall hits 599system.cpu.dcache.overall_hits::total 2520 # number of overall hits 600system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses 601system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses 602system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses 603system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses 604system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses 605system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses 606system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses 607system.cpu.dcache.overall_misses::total 193 # number of overall misses 608system.cpu.dcache.ReadReq_miss_latency::cpu.data 10226000 # number of ReadReq miss cycles 609system.cpu.dcache.ReadReq_miss_latency::total 10226000 # number of ReadReq miss cycles 610system.cpu.dcache.WriteReq_miss_latency::cpu.data 7070500 # number of WriteReq miss cycles 611system.cpu.dcache.WriteReq_miss_latency::total 7070500 # number of WriteReq miss cycles 612system.cpu.dcache.demand_miss_latency::cpu.data 17296500 # number of demand (read+write) miss cycles 613system.cpu.dcache.demand_miss_latency::total 17296500 # number of demand (read+write) miss cycles 614system.cpu.dcache.overall_miss_latency::cpu.data 17296500 # number of overall miss cycles 615system.cpu.dcache.overall_miss_latency::total 17296500 # number of overall miss cycles 616system.cpu.dcache.ReadReq_accesses::cpu.data 1778 # number of ReadReq accesses(hits+misses) 617system.cpu.dcache.ReadReq_accesses::total 1778 # number of ReadReq accesses(hits+misses) |
| 608system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 609system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) | 618system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 619system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) |
| 610system.cpu.dcache.demand_accesses::cpu.data 2770 # number of demand (read+write) accesses 611system.cpu.dcache.demand_accesses::total 2770 # number of demand (read+write) accesses 612system.cpu.dcache.overall_accesses::cpu.data 2770 # number of overall (read+write) accesses 613system.cpu.dcache.overall_accesses::total 2770 # number of overall (read+write) accesses 614system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063215 # miss rate for ReadReq accesses 615system.cpu.dcache.ReadReq_miss_rate::total 0.063215 # miss rate for ReadReq accesses 616system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080214 # miss rate for WriteReq accesses 617system.cpu.dcache.WriteReq_miss_rate::total 0.080214 # miss rate for WriteReq accesses 618system.cpu.dcache.demand_miss_rate::cpu.data 0.068953 # miss rate for demand accesses 619system.cpu.dcache.demand_miss_rate::total 0.068953 # miss rate for demand accesses 620system.cpu.dcache.overall_miss_rate::cpu.data 0.068953 # miss rate for overall accesses 621system.cpu.dcache.overall_miss_rate::total 0.068953 # miss rate for overall accesses 622system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81599.137931 # average ReadReq miss latency 623system.cpu.dcache.ReadReq_avg_miss_latency::total 81599.137931 # average ReadReq miss latency 624system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84226.666667 # average WriteReq miss latency 625system.cpu.dcache.WriteReq_avg_miss_latency::total 84226.666667 # average WriteReq miss latency 626system.cpu.dcache.demand_avg_miss_latency::cpu.data 82630.890052 # average overall miss latency 627system.cpu.dcache.demand_avg_miss_latency::total 82630.890052 # average overall miss latency 628system.cpu.dcache.overall_avg_miss_latency::cpu.data 82630.890052 # average overall miss latency 629system.cpu.dcache.overall_avg_miss_latency::total 82630.890052 # average overall miss latency 630system.cpu.dcache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked | 620system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses 621system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses 622system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses 623system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses 624system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065804 # miss rate for ReadReq accesses 625system.cpu.dcache.ReadReq_miss_rate::total 0.065804 # miss rate for ReadReq accesses 626system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses 627system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses 628system.cpu.dcache.demand_miss_rate::cpu.data 0.071139 # miss rate for demand accesses 629system.cpu.dcache.demand_miss_rate::total 0.071139 # miss rate for demand accesses 630system.cpu.dcache.overall_miss_rate::cpu.data 0.071139 # miss rate for overall accesses 631system.cpu.dcache.overall_miss_rate::total 0.071139 # miss rate for overall accesses 632system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87401.709402 # average ReadReq miss latency 633system.cpu.dcache.ReadReq_avg_miss_latency::total 87401.709402 # average ReadReq miss latency 634system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93032.894737 # average WriteReq miss latency 635system.cpu.dcache.WriteReq_avg_miss_latency::total 93032.894737 # average WriteReq miss latency 636system.cpu.dcache.demand_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency 637system.cpu.dcache.demand_avg_miss_latency::total 89619.170984 # average overall miss latency 638system.cpu.dcache.overall_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency 639system.cpu.dcache.overall_avg_miss_latency::total 89619.170984 # average overall miss latency 640system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked |
| 631system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 632system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 633system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 641system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 642system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 643system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 634system.cpu.dcache.avg_blocked_cycles::no_mshrs 41.333333 # average number of cycles each access was blocked | 644system.cpu.dcache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked |
| 635system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 636system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits 637system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits 638system.cpu.dcache.demand_mshr_hits::cpu.data 52 # number of demand (read+write) MSHR hits 639system.cpu.dcache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits 640system.cpu.dcache.overall_mshr_hits::cpu.data 52 # number of overall MSHR hits 641system.cpu.dcache.overall_mshr_hits::total 52 # number of overall MSHR hits | 645system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 646system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits 647system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits 648system.cpu.dcache.demand_mshr_hits::cpu.data 52 # number of demand (read+write) MSHR hits 649system.cpu.dcache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits 650system.cpu.dcache.overall_mshr_hits::cpu.data 52 # number of overall MSHR hits 651system.cpu.dcache.overall_mshr_hits::total 52 # number of overall MSHR hits |
| 642system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 643system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses 644system.cpu.dcache.WriteReq_mshr_misses::cpu.data 75 # number of WriteReq MSHR misses 645system.cpu.dcache.WriteReq_mshr_misses::total 75 # number of WriteReq MSHR misses 646system.cpu.dcache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses 647system.cpu.dcache.demand_mshr_misses::total 139 # number of demand (read+write) MSHR misses 648system.cpu.dcache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses 649system.cpu.dcache.overall_mshr_misses::total 139 # number of overall MSHR misses 650system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5739000 # number of ReadReq MSHR miss cycles 651system.cpu.dcache.ReadReq_mshr_miss_latency::total 5739000 # number of ReadReq MSHR miss cycles 652system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6242000 # number of WriteReq MSHR miss cycles 653system.cpu.dcache.WriteReq_mshr_miss_latency::total 6242000 # number of WriteReq MSHR miss cycles 654system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981000 # number of demand (read+write) MSHR miss cycles 655system.cpu.dcache.demand_mshr_miss_latency::total 11981000 # number of demand (read+write) MSHR miss cycles 656system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981000 # number of overall MSHR miss cycles 657system.cpu.dcache.overall_mshr_miss_latency::total 11981000 # number of overall MSHR miss cycles 658system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for ReadReq accesses 659system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034877 # mshr miss rate for ReadReq accesses 660system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.080214 # mshr miss rate for WriteReq accesses 661system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.080214 # mshr miss rate for WriteReq accesses 662system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050181 # mshr miss rate for demand accesses 663system.cpu.dcache.demand_mshr_miss_rate::total 0.050181 # mshr miss rate for demand accesses 664system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050181 # mshr miss rate for overall accesses 665system.cpu.dcache.overall_mshr_miss_rate::total 0.050181 # mshr miss rate for overall accesses 666system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89671.875000 # average ReadReq mshr miss latency 667system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89671.875000 # average ReadReq mshr miss latency 668system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83226.666667 # average WriteReq mshr miss latency 669system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83226.666667 # average WriteReq mshr miss latency 670system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86194.244604 # average overall mshr miss latency 671system.cpu.dcache.demand_avg_mshr_miss_latency::total 86194.244604 # average overall mshr miss latency 672system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86194.244604 # average overall mshr miss latency 673system.cpu.dcache.overall_avg_mshr_miss_latency::total 86194.244604 # average overall mshr miss latency 674system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states | 652system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 653system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses 654system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses 655system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses 656system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 657system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 658system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 659system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 660system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6448000 # number of ReadReq MSHR miss cycles 661system.cpu.dcache.ReadReq_mshr_miss_latency::total 6448000 # number of ReadReq MSHR miss cycles 662system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6994500 # number of WriteReq MSHR miss cycles 663system.cpu.dcache.WriteReq_mshr_miss_latency::total 6994500 # number of WriteReq MSHR miss cycles 664system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13442500 # number of demand (read+write) MSHR miss cycles 665system.cpu.dcache.demand_mshr_miss_latency::total 13442500 # number of demand (read+write) MSHR miss cycles 666system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13442500 # number of overall MSHR miss cycles 667system.cpu.dcache.overall_mshr_miss_latency::total 13442500 # number of overall MSHR miss cycles 668system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036558 # mshr miss rate for ReadReq accesses 669system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036558 # mshr miss rate for ReadReq accesses 670system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses 671system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses 672system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for demand accesses 673system.cpu.dcache.demand_mshr_miss_rate::total 0.051972 # mshr miss rate for demand accesses 674system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for overall accesses 675system.cpu.dcache.overall_mshr_miss_rate::total 0.051972 # mshr miss rate for overall accesses 676system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99200 # average ReadReq mshr miss latency 677system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99200 # average ReadReq mshr miss latency 678system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92032.894737 # average WriteReq mshr miss latency 679system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92032.894737 # average WriteReq mshr miss latency 680system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency 681system.cpu.dcache.demand_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency 682system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency 683system.cpu.dcache.overall_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency 684system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states |
| 675system.cpu.icache.tags.replacements 0 # number of replacements | 685system.cpu.icache.tags.replacements 0 # number of replacements |
| 676system.cpu.icache.tags.tagsinuse 130.610950 # Cycle average of tags in use 677system.cpu.icache.tags.total_refs 1656 # Total number of references to valid blocks. 678system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. 679system.cpu.icache.tags.avg_refs 5.935484 # Average number of references to valid blocks. | 686system.cpu.icache.tags.tagsinuse 130.260906 # Cycle average of tags in use 687system.cpu.icache.tags.total_refs 1641 # Total number of references to valid blocks. 688system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. 689system.cpu.icache.tags.avg_refs 5.902878 # Average number of references to valid blocks. |
| 680system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 690system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 681system.cpu.icache.tags.occ_blocks::cpu.inst 130.610950 # Average occupied blocks per requestor 682system.cpu.icache.tags.occ_percent::cpu.inst 0.063775 # Average percentage of cache occupancy 683system.cpu.icache.tags.occ_percent::total 0.063775 # Average percentage of cache occupancy 684system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id 685system.cpu.icache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id 686system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 687system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id 688system.cpu.icache.tags.tag_accesses 4363 # Number of tag accesses 689system.cpu.icache.tags.data_accesses 4363 # Number of data accesses 690system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states 691system.cpu.icache.ReadReq_hits::cpu.inst 1656 # number of ReadReq hits 692system.cpu.icache.ReadReq_hits::total 1656 # number of ReadReq hits 693system.cpu.icache.demand_hits::cpu.inst 1656 # number of demand (read+write) hits 694system.cpu.icache.demand_hits::total 1656 # number of demand (read+write) hits 695system.cpu.icache.overall_hits::cpu.inst 1656 # number of overall hits 696system.cpu.icache.overall_hits::total 1656 # number of overall hits 697system.cpu.icache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses 698system.cpu.icache.ReadReq_misses::total 386 # number of ReadReq misses 699system.cpu.icache.demand_misses::cpu.inst 386 # number of demand (read+write) misses 700system.cpu.icache.demand_misses::total 386 # number of demand (read+write) misses 701system.cpu.icache.overall_misses::cpu.inst 386 # number of overall misses 702system.cpu.icache.overall_misses::total 386 # number of overall misses 703system.cpu.icache.ReadReq_miss_latency::cpu.inst 29282500 # number of ReadReq miss cycles 704system.cpu.icache.ReadReq_miss_latency::total 29282500 # number of ReadReq miss cycles 705system.cpu.icache.demand_miss_latency::cpu.inst 29282500 # number of demand (read+write) miss cycles 706system.cpu.icache.demand_miss_latency::total 29282500 # number of demand (read+write) miss cycles 707system.cpu.icache.overall_miss_latency::cpu.inst 29282500 # number of overall miss cycles 708system.cpu.icache.overall_miss_latency::total 29282500 # number of overall miss cycles 709system.cpu.icache.ReadReq_accesses::cpu.inst 2042 # number of ReadReq accesses(hits+misses) 710system.cpu.icache.ReadReq_accesses::total 2042 # number of ReadReq accesses(hits+misses) 711system.cpu.icache.demand_accesses::cpu.inst 2042 # number of demand (read+write) accesses 712system.cpu.icache.demand_accesses::total 2042 # number of demand (read+write) accesses 713system.cpu.icache.overall_accesses::cpu.inst 2042 # number of overall (read+write) accesses 714system.cpu.icache.overall_accesses::total 2042 # number of overall (read+write) accesses 715system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.189030 # miss rate for ReadReq accesses 716system.cpu.icache.ReadReq_miss_rate::total 0.189030 # miss rate for ReadReq accesses 717system.cpu.icache.demand_miss_rate::cpu.inst 0.189030 # miss rate for demand accesses 718system.cpu.icache.demand_miss_rate::total 0.189030 # miss rate for demand accesses 719system.cpu.icache.overall_miss_rate::cpu.inst 0.189030 # miss rate for overall accesses 720system.cpu.icache.overall_miss_rate::total 0.189030 # miss rate for overall accesses 721system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75861.398964 # average ReadReq miss latency 722system.cpu.icache.ReadReq_avg_miss_latency::total 75861.398964 # average ReadReq miss latency 723system.cpu.icache.demand_avg_miss_latency::cpu.inst 75861.398964 # average overall miss latency 724system.cpu.icache.demand_avg_miss_latency::total 75861.398964 # average overall miss latency 725system.cpu.icache.overall_avg_miss_latency::cpu.inst 75861.398964 # average overall miss latency 726system.cpu.icache.overall_avg_miss_latency::total 75861.398964 # average overall miss latency 727system.cpu.icache.blocked_cycles::no_mshrs 121 # number of cycles access was blocked | 691system.cpu.icache.tags.occ_blocks::cpu.inst 130.260906 # Average occupied blocks per requestor 692system.cpu.icache.tags.occ_percent::cpu.inst 0.063604 # Average percentage of cache occupancy 693system.cpu.icache.tags.occ_percent::total 0.063604 # Average percentage of cache occupancy 694system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id 695system.cpu.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id 696system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id 697system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id 698system.cpu.icache.tags.tag_accesses 4330 # Number of tag accesses 699system.cpu.icache.tags.data_accesses 4330 # Number of data accesses 700system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states 701system.cpu.icache.ReadReq_hits::cpu.inst 1641 # number of ReadReq hits 702system.cpu.icache.ReadReq_hits::total 1641 # number of ReadReq hits 703system.cpu.icache.demand_hits::cpu.inst 1641 # number of demand (read+write) hits 704system.cpu.icache.demand_hits::total 1641 # number of demand (read+write) hits 705system.cpu.icache.overall_hits::cpu.inst 1641 # number of overall hits 706system.cpu.icache.overall_hits::total 1641 # number of overall hits 707system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses 708system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses 709system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses 710system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses 711system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses 712system.cpu.icache.overall_misses::total 385 # number of overall misses 713system.cpu.icache.ReadReq_miss_latency::cpu.inst 30146000 # number of ReadReq miss cycles 714system.cpu.icache.ReadReq_miss_latency::total 30146000 # number of ReadReq miss cycles 715system.cpu.icache.demand_miss_latency::cpu.inst 30146000 # number of demand (read+write) miss cycles 716system.cpu.icache.demand_miss_latency::total 30146000 # number of demand (read+write) miss cycles 717system.cpu.icache.overall_miss_latency::cpu.inst 30146000 # number of overall miss cycles 718system.cpu.icache.overall_miss_latency::total 30146000 # number of overall miss cycles 719system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses) 720system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses) 721system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses 722system.cpu.icache.demand_accesses::total 2026 # number of demand (read+write) accesses 723system.cpu.icache.overall_accesses::cpu.inst 2026 # number of overall (read+write) accesses 724system.cpu.icache.overall_accesses::total 2026 # number of overall (read+write) accesses 725system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190030 # miss rate for ReadReq accesses 726system.cpu.icache.ReadReq_miss_rate::total 0.190030 # miss rate for ReadReq accesses 727system.cpu.icache.demand_miss_rate::cpu.inst 0.190030 # miss rate for demand accesses 728system.cpu.icache.demand_miss_rate::total 0.190030 # miss rate for demand accesses 729system.cpu.icache.overall_miss_rate::cpu.inst 0.190030 # miss rate for overall accesses 730system.cpu.icache.overall_miss_rate::total 0.190030 # miss rate for overall accesses 731system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78301.298701 # average ReadReq miss latency 732system.cpu.icache.ReadReq_avg_miss_latency::total 78301.298701 # average ReadReq miss latency 733system.cpu.icache.demand_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency 734system.cpu.icache.demand_avg_miss_latency::total 78301.298701 # average overall miss latency 735system.cpu.icache.overall_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency 736system.cpu.icache.overall_avg_miss_latency::total 78301.298701 # average overall miss latency 737system.cpu.icache.blocked_cycles::no_mshrs 171 # number of cycles access was blocked |
| 728system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 729system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 730system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 738system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 739system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 740system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 731system.cpu.icache.avg_blocked_cycles::no_mshrs 40.333333 # average number of cycles each access was blocked | 741system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked |
| 732system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 733system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # number of ReadReq MSHR hits 734system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits 735system.cpu.icache.demand_mshr_hits::cpu.inst 107 # number of demand (read+write) MSHR hits 736system.cpu.icache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits 737system.cpu.icache.overall_mshr_hits::cpu.inst 107 # number of overall MSHR hits 738system.cpu.icache.overall_mshr_hits::total 107 # number of overall MSHR hits | 742system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 743system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # number of ReadReq MSHR hits 744system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits 745system.cpu.icache.demand_mshr_hits::cpu.inst 107 # number of demand (read+write) MSHR hits 746system.cpu.icache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits 747system.cpu.icache.overall_mshr_hits::cpu.inst 107 # number of overall MSHR hits 748system.cpu.icache.overall_mshr_hits::total 107 # number of overall MSHR hits |
| 739system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 740system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 741system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 742system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 743system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 744system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses 745system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22839500 # number of ReadReq MSHR miss cycles 746system.cpu.icache.ReadReq_mshr_miss_latency::total 22839500 # number of ReadReq MSHR miss cycles 747system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22839500 # number of demand (read+write) MSHR miss cycles 748system.cpu.icache.demand_mshr_miss_latency::total 22839500 # number of demand (read+write) MSHR miss cycles 749system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22839500 # number of overall MSHR miss cycles 750system.cpu.icache.overall_mshr_miss_latency::total 22839500 # number of overall MSHR miss cycles 751system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136631 # mshr miss rate for ReadReq accesses 752system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136631 # mshr miss rate for ReadReq accesses 753system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136631 # mshr miss rate for demand accesses 754system.cpu.icache.demand_mshr_miss_rate::total 0.136631 # mshr miss rate for demand accesses 755system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136631 # mshr miss rate for overall accesses 756system.cpu.icache.overall_mshr_miss_rate::total 0.136631 # mshr miss rate for overall accesses 757system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81862.007168 # average ReadReq mshr miss latency 758system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81862.007168 # average ReadReq mshr miss latency 759system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81862.007168 # average overall mshr miss latency 760system.cpu.icache.demand_avg_mshr_miss_latency::total 81862.007168 # average overall mshr miss latency 761system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81862.007168 # average overall mshr miss latency 762system.cpu.icache.overall_avg_mshr_miss_latency::total 81862.007168 # average overall mshr miss latency 763system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states | 749system.cpu.icache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 750system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses 751system.cpu.icache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 752system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses 753system.cpu.icache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 754system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses 755system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23206500 # number of ReadReq MSHR miss cycles 756system.cpu.icache.ReadReq_mshr_miss_latency::total 23206500 # number of ReadReq MSHR miss cycles 757system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23206500 # number of demand (read+write) MSHR miss cycles 758system.cpu.icache.demand_mshr_miss_latency::total 23206500 # number of demand (read+write) MSHR miss cycles 759system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23206500 # number of overall MSHR miss cycles 760system.cpu.icache.overall_mshr_miss_latency::total 23206500 # number of overall MSHR miss cycles 761system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for ReadReq accesses 762system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137216 # mshr miss rate for ReadReq accesses 763system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for demand accesses 764system.cpu.icache.demand_mshr_miss_rate::total 0.137216 # mshr miss rate for demand accesses 765system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for overall accesses 766system.cpu.icache.overall_mshr_miss_rate::total 0.137216 # mshr miss rate for overall accesses 767system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83476.618705 # average ReadReq mshr miss latency 768system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83476.618705 # average ReadReq mshr miss latency 769system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency 770system.cpu.icache.demand_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency 771system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency 772system.cpu.icache.overall_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency 773system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states |
| 764system.cpu.l2cache.tags.replacements 0 # number of replacements | 774system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 765system.cpu.l2cache.tags.tagsinuse 212.046379 # Cycle average of tags in use | 775system.cpu.l2cache.tags.tagsinuse 211.897546 # Cycle average of tags in use |
| 766system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. | 776system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. |
| 767system.cpu.l2cache.tags.sampled_refs 417 # Sample count of references to valid blocks. 768system.cpu.l2cache.tags.avg_refs 0.002398 # Average number of references to valid blocks. | 777system.cpu.l2cache.tags.sampled_refs 418 # Sample count of references to valid blocks. 778system.cpu.l2cache.tags.avg_refs 0.002392 # Average number of references to valid blocks. |
| 769system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 779system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 770system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.650071 # Average occupied blocks per requestor 771system.cpu.l2cache.tags.occ_blocks::cpu.data 81.396308 # Average occupied blocks per requestor 772system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003987 # Average percentage of cache occupancy 773system.cpu.l2cache.tags.occ_percent::cpu.data 0.002484 # Average percentage of cache occupancy 774system.cpu.l2cache.tags.occ_percent::total 0.006471 # Average percentage of cache occupancy 775system.cpu.l2cache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id 776system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id 777system.cpu.l2cache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id 778system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012726 # Percentage of cache occupancy per task id 779system.cpu.l2cache.tags.tag_accesses 3761 # Number of tag accesses 780system.cpu.l2cache.tags.data_accesses 3761 # Number of data accesses 781system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states | 780system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.293933 # Average occupied blocks per requestor 781system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603612 # Average occupied blocks per requestor 782system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003976 # Average percentage of cache occupancy 783system.cpu.l2cache.tags.occ_percent::cpu.data 0.002490 # Average percentage of cache occupancy 784system.cpu.l2cache.tags.occ_percent::total 0.006467 # Average percentage of cache occupancy 785system.cpu.l2cache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id 786system.cpu.l2cache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id 787system.cpu.l2cache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id 788system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012756 # Percentage of cache occupancy per task id 789system.cpu.l2cache.tags.tag_accesses 3770 # Number of tag accesses 790system.cpu.l2cache.tags.data_accesses 3770 # Number of data accesses 791system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states |
| 782system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 783system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 784system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 785system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 786system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 787system.cpu.l2cache.overall_hits::total 1 # number of overall hits | 792system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 793system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 794system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 795system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 796system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 797system.cpu.l2cache.overall_hits::total 1 # number of overall hits |
| 788system.cpu.l2cache.ReadExReq_misses::cpu.data 75 # number of ReadExReq misses 789system.cpu.l2cache.ReadExReq_misses::total 75 # number of ReadExReq misses 790system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses 791system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses 792system.cpu.l2cache.ReadSharedReq_misses::cpu.data 64 # number of ReadSharedReq misses 793system.cpu.l2cache.ReadSharedReq_misses::total 64 # number of ReadSharedReq misses 794system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 795system.cpu.l2cache.demand_misses::cpu.data 139 # number of demand (read+write) misses 796system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses 797system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses 798system.cpu.l2cache.overall_misses::cpu.data 139 # number of overall misses 799system.cpu.l2cache.overall_misses::total 417 # number of overall misses 800system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6129000 # number of ReadExReq miss cycles 801system.cpu.l2cache.ReadExReq_miss_latency::total 6129000 # number of ReadExReq miss cycles 802system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22409000 # number of ReadCleanReq miss cycles 803system.cpu.l2cache.ReadCleanReq_miss_latency::total 22409000 # number of ReadCleanReq miss cycles 804system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5642000 # number of ReadSharedReq miss cycles 805system.cpu.l2cache.ReadSharedReq_miss_latency::total 5642000 # number of ReadSharedReq miss cycles 806system.cpu.l2cache.demand_miss_latency::cpu.inst 22409000 # number of demand (read+write) miss cycles 807system.cpu.l2cache.demand_miss_latency::cpu.data 11771000 # number of demand (read+write) miss cycles 808system.cpu.l2cache.demand_miss_latency::total 34180000 # number of demand (read+write) miss cycles 809system.cpu.l2cache.overall_miss_latency::cpu.inst 22409000 # number of overall miss cycles 810system.cpu.l2cache.overall_miss_latency::cpu.data 11771000 # number of overall miss cycles 811system.cpu.l2cache.overall_miss_latency::total 34180000 # number of overall miss cycles 812system.cpu.l2cache.ReadExReq_accesses::cpu.data 75 # number of ReadExReq accesses(hits+misses) 813system.cpu.l2cache.ReadExReq_accesses::total 75 # number of ReadExReq accesses(hits+misses) 814system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses) 815system.cpu.l2cache.ReadCleanReq_accesses::total 279 # number of ReadCleanReq accesses(hits+misses) 816system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64 # number of ReadSharedReq accesses(hits+misses) 817system.cpu.l2cache.ReadSharedReq_accesses::total 64 # number of ReadSharedReq accesses(hits+misses) 818system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses 819system.cpu.l2cache.demand_accesses::cpu.data 139 # number of demand (read+write) accesses 820system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses 821system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses 822system.cpu.l2cache.overall_accesses::cpu.data 139 # number of overall (read+write) accesses 823system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses | 798system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses 799system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses 800system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 277 # number of ReadCleanReq misses 801system.cpu.l2cache.ReadCleanReq_misses::total 277 # number of ReadCleanReq misses 802system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses 803system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses 804system.cpu.l2cache.demand_misses::cpu.inst 277 # number of demand (read+write) misses 805system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses 806system.cpu.l2cache.demand_misses::total 418 # number of demand (read+write) misses 807system.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses 808system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses 809system.cpu.l2cache.overall_misses::total 418 # number of overall misses 810system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6880500 # number of ReadExReq miss cycles 811system.cpu.l2cache.ReadExReq_miss_latency::total 6880500 # number of ReadExReq miss cycles 812system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22777500 # number of ReadCleanReq miss cycles 813system.cpu.l2cache.ReadCleanReq_miss_latency::total 22777500 # number of ReadCleanReq miss cycles 814system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6350000 # number of ReadSharedReq miss cycles 815system.cpu.l2cache.ReadSharedReq_miss_latency::total 6350000 # number of ReadSharedReq miss cycles 816system.cpu.l2cache.demand_miss_latency::cpu.inst 22777500 # number of demand (read+write) miss cycles 817system.cpu.l2cache.demand_miss_latency::cpu.data 13230500 # number of demand (read+write) miss cycles 818system.cpu.l2cache.demand_miss_latency::total 36008000 # number of demand (read+write) miss cycles 819system.cpu.l2cache.overall_miss_latency::cpu.inst 22777500 # number of overall miss cycles 820system.cpu.l2cache.overall_miss_latency::cpu.data 13230500 # number of overall miss cycles 821system.cpu.l2cache.overall_miss_latency::total 36008000 # number of overall miss cycles 822system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) 823system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) 824system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 278 # number of ReadCleanReq accesses(hits+misses) 825system.cpu.l2cache.ReadCleanReq_accesses::total 278 # number of ReadCleanReq accesses(hits+misses) 826system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) 827system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) 828system.cpu.l2cache.demand_accesses::cpu.inst 278 # number of demand (read+write) accesses 829system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 830system.cpu.l2cache.demand_accesses::total 419 # number of demand (read+write) accesses 831system.cpu.l2cache.overall_accesses::cpu.inst 278 # number of overall (read+write) accesses 832system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 833system.cpu.l2cache.overall_accesses::total 419 # number of overall (read+write) accesses |
| 824system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 825system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 834system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 835system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 826system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadCleanReq accesses 827system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996416 # miss rate for ReadCleanReq accesses | 836system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996403 # miss rate for ReadCleanReq accesses 837system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996403 # miss rate for ReadCleanReq accesses |
| 828system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 829system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses | 838system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 839system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses |
| 830system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses | 840system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996403 # miss rate for demand accesses |
| 831system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses | 841system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
| 832system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses 833system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses | 842system.cpu.l2cache.demand_miss_rate::total 0.997613 # miss rate for demand accesses 843system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996403 # miss rate for overall accesses |
| 834system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses | 844system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
| 835system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses 836system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81720 # average ReadExReq miss latency 837system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81720 # average ReadExReq miss latency 838system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80607.913669 # average ReadCleanReq miss latency 839system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80607.913669 # average ReadCleanReq miss latency 840system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88156.250000 # average ReadSharedReq miss latency 841system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88156.250000 # average ReadSharedReq miss latency 842system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80607.913669 # average overall miss latency 843system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84683.453237 # average overall miss latency 844system.cpu.l2cache.demand_avg_miss_latency::total 81966.426859 # average overall miss latency 845system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80607.913669 # average overall miss latency 846system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84683.453237 # average overall miss latency 847system.cpu.l2cache.overall_avg_miss_latency::total 81966.426859 # average overall miss latency | 845system.cpu.l2cache.overall_miss_rate::total 0.997613 # miss rate for overall accesses 846system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90532.894737 # average ReadExReq miss latency 847system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90532.894737 # average ReadExReq miss latency 848system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82229.241877 # average ReadCleanReq miss latency 849system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82229.241877 # average ReadCleanReq miss latency 850system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97692.307692 # average ReadSharedReq miss latency 851system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 97692.307692 # average ReadSharedReq miss latency 852system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency 853system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency 854system.cpu.l2cache.demand_avg_miss_latency::total 86143.540670 # average overall miss latency 855system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency 856system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency 857system.cpu.l2cache.overall_avg_miss_latency::total 86143.540670 # average overall miss latency |
| 848system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 849system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 850system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 851system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 852system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 853system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 858system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 859system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 860system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 861system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 862system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 863system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 854system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 75 # number of ReadExReq MSHR misses 855system.cpu.l2cache.ReadExReq_mshr_misses::total 75 # number of ReadExReq MSHR misses 856system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses 857system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses 858system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses 859system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses 860system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 861system.cpu.l2cache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses 862system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses 863system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 864system.cpu.l2cache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses 865system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses 866system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5379000 # number of ReadExReq MSHR miss cycles 867system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5379000 # number of ReadExReq MSHR miss cycles 868system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19629000 # number of ReadCleanReq MSHR miss cycles 869system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19629000 # number of ReadCleanReq MSHR miss cycles 870system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5002000 # number of ReadSharedReq MSHR miss cycles 871system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5002000 # number of ReadSharedReq MSHR miss cycles 872system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19629000 # number of demand (read+write) MSHR miss cycles 873system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10381000 # number of demand (read+write) MSHR miss cycles 874system.cpu.l2cache.demand_mshr_miss_latency::total 30010000 # number of demand (read+write) MSHR miss cycles 875system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19629000 # number of overall MSHR miss cycles 876system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10381000 # number of overall MSHR miss cycles 877system.cpu.l2cache.overall_mshr_miss_latency::total 30010000 # number of overall MSHR miss cycles | 864system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses 865system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses 866system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses 867system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses 868system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses 869system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses 870system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses 871system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 872system.cpu.l2cache.demand_mshr_misses::total 418 # number of demand (read+write) MSHR misses 873system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses 874system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 875system.cpu.l2cache.overall_mshr_misses::total 418 # number of overall MSHR misses 876system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6120500 # number of ReadExReq MSHR miss cycles 877system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6120500 # number of ReadExReq MSHR miss cycles 878system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20007500 # number of ReadCleanReq MSHR miss cycles 879system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20007500 # number of ReadCleanReq MSHR miss cycles 880system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5700000 # number of ReadSharedReq MSHR miss cycles 881system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5700000 # number of ReadSharedReq MSHR miss cycles 882system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20007500 # number of demand (read+write) MSHR miss cycles 883system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11820500 # number of demand (read+write) MSHR miss cycles 884system.cpu.l2cache.demand_mshr_miss_latency::total 31828000 # number of demand (read+write) MSHR miss cycles 885system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20007500 # number of overall MSHR miss cycles 886system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11820500 # number of overall MSHR miss cycles 887system.cpu.l2cache.overall_mshr_miss_latency::total 31828000 # number of overall MSHR miss cycles |
| 878system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 879system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 888system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 889system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 880system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses 881system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996416 # mshr miss rate for ReadCleanReq accesses | 890system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses 891system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996403 # mshr miss rate for ReadCleanReq accesses |
| 882system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 883system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses | 892system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 893system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses |
| 884system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses | 894system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses |
| 885system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses | 895system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
| 886system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses 887system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses | 896system.cpu.l2cache.demand_mshr_miss_rate::total 0.997613 # mshr miss rate for demand accesses 897system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses |
| 888system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses | 898system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
| 889system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses 890system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71720 # average ReadExReq mshr miss latency 891system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71720 # average ReadExReq mshr miss latency 892system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70607.913669 # average ReadCleanReq mshr miss latency 893system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70607.913669 # average ReadCleanReq mshr miss latency 894system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78156.250000 # average ReadSharedReq mshr miss latency 895system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78156.250000 # average ReadSharedReq mshr miss latency 896system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70607.913669 # average overall mshr miss latency 897system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74683.453237 # average overall mshr miss latency 898system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71966.426859 # average overall mshr miss latency 899system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70607.913669 # average overall mshr miss latency 900system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74683.453237 # average overall mshr miss latency 901system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71966.426859 # average overall mshr miss latency 902system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. | 899system.cpu.l2cache.overall_mshr_miss_rate::total 0.997613 # mshr miss rate for overall accesses 900system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80532.894737 # average ReadExReq mshr miss latency 901system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80532.894737 # average ReadExReq mshr miss latency 902system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72229.241877 # average ReadCleanReq mshr miss latency 903system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72229.241877 # average ReadCleanReq mshr miss latency 904system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87692.307692 # average ReadSharedReq mshr miss latency 905system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87692.307692 # average ReadSharedReq mshr miss latency 906system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency 907system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency 908system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency 909system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency 910system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency 911system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency 912system.cpu.toL2Bus.snoop_filter.tot_requests 419 # Total number of requests made to the snoop filter. |
| 903system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 904system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 905system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 906system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 907system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 913system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 914system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 915system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 916system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 917system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 908system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states | 918system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states |
| 909system.cpu.toL2Bus.trans_dist::ReadResp 343 # Transaction distribution | 919system.cpu.toL2Bus.trans_dist::ReadResp 343 # Transaction distribution |
| 910system.cpu.toL2Bus.trans_dist::ReadExReq 75 # Transaction distribution 911system.cpu.toL2Bus.trans_dist::ReadExResp 75 # Transaction distribution 912system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution 913system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution 914system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) 915system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes) 916system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) 917system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) 918system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8896 # Cumulative packet size per connected master and slave (bytes) 919system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) | 920system.cpu.toL2Bus.trans_dist::ReadExReq 76 # Transaction distribution 921system.cpu.toL2Bus.trans_dist::ReadExResp 76 # Transaction distribution 922system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution 923system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution 924system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes) 925system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) 926system.cpu.toL2Bus.pkt_count::total 838 # Packet count per connected master and slave (bytes) 927system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes) 928system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) 929system.cpu.toL2Bus.pkt_size::total 26816 # Cumulative packet size per connected master and slave (bytes) |
| 920system.cpu.toL2Bus.snoops 0 # Total snoops (count) 921system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) | 930system.cpu.toL2Bus.snoops 0 # Total snoops (count) 931system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 922system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram 923system.cpu.toL2Bus.snoop_fanout::mean 0.002392 # Request fanout histogram 924system.cpu.toL2Bus.snoop_fanout::stdev 0.048912 # Request fanout histogram | 932system.cpu.toL2Bus.snoop_fanout::samples 419 # Request fanout histogram 933system.cpu.toL2Bus.snoop_fanout::mean 0.002387 # Request fanout histogram 934system.cpu.toL2Bus.snoop_fanout::stdev 0.048853 # Request fanout histogram |
| 925system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 935system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 926system.cpu.toL2Bus.snoop_fanout::0 417 99.76% 99.76% # Request fanout histogram | 936system.cpu.toL2Bus.snoop_fanout::0 418 99.76% 99.76% # Request fanout histogram |
| 927system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram 928system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 929system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 930system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 931system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 937system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram 938system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 939system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 940system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 941system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 932system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram 933system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) 934system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 935system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) 936system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 937system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks) 938system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 939system.membus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. | 942system.cpu.toL2Bus.snoop_fanout::total 419 # Request fanout histogram 943system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks) 944system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) 945system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks) 946system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) 947system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) 948system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 949system.membus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. |
| 940system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 941system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 942system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 943system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 944system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 950system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 951system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 952system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 953system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 954system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 945system.membus.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states | 955system.membus.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states |
| 946system.membus.trans_dist::ReadResp 342 # Transaction distribution | 956system.membus.trans_dist::ReadResp 342 # Transaction distribution |
| 947system.membus.trans_dist::ReadExReq 75 # Transaction distribution 948system.membus.trans_dist::ReadExResp 75 # Transaction distribution | 957system.membus.trans_dist::ReadExReq 76 # Transaction distribution 958system.membus.trans_dist::ReadExResp 76 # Transaction distribution |
| 949system.membus.trans_dist::ReadSharedReq 342 # Transaction distribution | 959system.membus.trans_dist::ReadSharedReq 342 # Transaction distribution |
| 950system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 834 # Packet count per connected master and slave (bytes) 951system.membus.pkt_count_system.cpu.l2cache.mem_side::total 834 # Packet count per connected master and slave (bytes) 952system.membus.pkt_count::total 834 # Packet count per connected master and slave (bytes) 953system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26688 # Cumulative packet size per connected master and slave (bytes) 954system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26688 # Cumulative packet size per connected master and slave (bytes) 955system.membus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) | 960system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836 # Packet count per connected master and slave (bytes) 961system.membus.pkt_count_system.cpu.l2cache.mem_side::total 836 # Packet count per connected master and slave (bytes) 962system.membus.pkt_count::total 836 # Packet count per connected master and slave (bytes) 963system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26752 # Cumulative packet size per connected master and slave (bytes) 964system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26752 # Cumulative packet size per connected master and slave (bytes) 965system.membus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) |
| 956system.membus.snoops 0 # Total snoops (count) 957system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 966system.membus.snoops 0 # Total snoops (count) 967system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 958system.membus.snoop_fanout::samples 417 # Request fanout histogram | 968system.membus.snoop_fanout::samples 418 # Request fanout histogram |
| 959system.membus.snoop_fanout::mean 0 # Request fanout histogram 960system.membus.snoop_fanout::stdev 0 # Request fanout histogram 961system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 969system.membus.snoop_fanout::mean 0 # Request fanout histogram 970system.membus.snoop_fanout::stdev 0 # Request fanout histogram 971system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 962system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram | 972system.membus.snoop_fanout::0 418 100.00% 100.00% # Request fanout histogram |
| 963system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 964system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 965system.membus.snoop_fanout::min_value 0 # Request fanout histogram 966system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 973system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 974system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 975system.membus.snoop_fanout::min_value 0 # Request fanout histogram 976system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 967system.membus.snoop_fanout::total 417 # Request fanout histogram 968system.membus.reqLayer0.occupancy 503500 # Layer occupancy (ticks) 969system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) 970system.membus.respLayer1.occupancy 2228500 # Layer occupancy (ticks) 971system.membus.respLayer1.utilization 10.4 # Layer utilization (%) | 977system.membus.snoop_fanout::total 418 # Request fanout histogram 978system.membus.reqLayer0.occupancy 506000 # Layer occupancy (ticks) 979system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) 980system.membus.respLayer1.occupancy 2231250 # Layer occupancy (ticks) 981system.membus.respLayer1.utilization 9.9 # Layer utilization (%) |
| 972 973---------- End Simulation Statistics ---------- | 982 983---------- End Simulation Statistics ---------- |