| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated 4sim_ticks 21273500 # Number of ticks simulated 5final_tick 21273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated 4sim_ticks 21273500 # Number of ticks simulated 5final_tick 21273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 54566 # Simulator instruction rate (inst/s) 8host_op_rate 98846 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 215714601 # Simulator tick rate (ticks/s) 10host_mem_usage 266040 # Number of bytes of host memory used 11host_seconds 0.10 # Real time elapsed on the host | 7host_inst_rate 60676 # Simulator instruction rate (inst/s) 8host_op_rate 109916 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 239878032 # Simulator tick rate (ticks/s) 10host_mem_usage 312536 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host |
| 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 245system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 13993950 # Total energy per rank (pJ) 247system.physmem_1.averagePower 883.874941 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 262750 # Time in different power states 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 15224250 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory 19system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 416 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 246system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 13993950 # Total energy per rank (pJ) 248system.physmem_1.averagePower 883.874941 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 262750 # Time in different power states 250system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 252system.physmem_1.memoryStateTime::ACT 15224250 # Time in different power states 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 254system.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states |
|
| 253system.cpu.branchPred.lookups 3510 # Number of BP lookups 254system.cpu.branchPred.condPredicted 3510 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 564 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 2934 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 0 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 413 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 93 # Number of incorrect RAS predictions. 262system.cpu.branchPred.indirectLookups 2934 # Number of indirect predictor lookups. 263system.cpu.branchPred.indirectHits 493 # Number of indirect target hits. 264system.cpu.branchPred.indirectMisses 2441 # Number of indirect misses. 265system.cpu.branchPredindirectMispredicted 404 # Number of mispredicted indirect branches. 266system.cpu_clk_domain.clock 500 # Clock period in ticks | 255system.cpu.branchPred.lookups 3510 # Number of BP lookups 256system.cpu.branchPred.condPredicted 3510 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 564 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 2934 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 0 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 262system.cpu.branchPred.usedRAS 413 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 93 # Number of incorrect RAS predictions. 264system.cpu.branchPred.indirectLookups 2934 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 493 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 2441 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 404 # Number of mispredicted indirect branches. 268system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 269system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states |
|
| 267system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 270system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 271system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states 272system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states |
|
| 268system.cpu.workload.num_syscalls 11 # Number of system calls | 273system.cpu.workload.num_syscalls 11 # Number of system calls |
| 274system.cpu.pwrStateResidencyTicks::ON 21273500 # Cumulative time (in ticks) in various power states |
|
| 269system.cpu.numCycles 42548 # number of cpu cycles simulated 270system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 271system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 272system.cpu.fetch.icacheStallCycles 11447 # Number of cycles fetch is stalled on an Icache miss 273system.cpu.fetch.Insts 15916 # Number of instructions fetch has processed 274system.cpu.fetch.Branches 3510 # Number of branches that fetch encountered 275system.cpu.fetch.predictedBranches 906 # Number of branches that fetch has predicted taken 276system.cpu.fetch.Cycles 9652 # Number of cycles fetch has run and was not squashing or blocked --- 274 unchanged lines hidden (view full) --- 551system.cpu.ipc_total 0.126445 # IPC: Total IPC of All Threads 552system.cpu.int_regfile_reads 21687 # number of integer regfile reads 553system.cpu.int_regfile_writes 13280 # number of integer regfile writes 554system.cpu.fp_regfile_reads 4 # number of floating regfile reads 555system.cpu.cc_regfile_reads 8296 # number of cc regfile reads 556system.cpu.cc_regfile_writes 5092 # number of cc regfile writes 557system.cpu.misc_regfile_reads 7660 # number of misc regfile reads 558system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 275system.cpu.numCycles 42548 # number of cpu cycles simulated 276system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 277system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 278system.cpu.fetch.icacheStallCycles 11447 # Number of cycles fetch is stalled on an Icache miss 279system.cpu.fetch.Insts 15916 # Number of instructions fetch has processed 280system.cpu.fetch.Branches 3510 # Number of branches that fetch encountered 281system.cpu.fetch.predictedBranches 906 # Number of branches that fetch has predicted taken 282system.cpu.fetch.Cycles 9652 # Number of cycles fetch has run and was not squashing or blocked --- 274 unchanged lines hidden (view full) --- 557system.cpu.ipc_total 0.126445 # IPC: Total IPC of All Threads 558system.cpu.int_regfile_reads 21687 # number of integer regfile reads 559system.cpu.int_regfile_writes 13280 # number of integer regfile writes 560system.cpu.fp_regfile_reads 4 # number of floating regfile reads 561system.cpu.cc_regfile_reads 8296 # number of cc regfile reads 562system.cpu.cc_regfile_writes 5092 # number of cc regfile writes 563system.cpu.misc_regfile_reads 7660 # number of misc regfile reads 564system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 565system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states |
|
| 559system.cpu.dcache.tags.replacements 0 # number of replacements 560system.cpu.dcache.tags.tagsinuse 81.534494 # Cycle average of tags in use 561system.cpu.dcache.tags.total_refs 2583 # Total number of references to valid blocks. 562system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks. 563system.cpu.dcache.tags.avg_refs 18.582734 # Average number of references to valid blocks. 564system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 565system.cpu.dcache.tags.occ_blocks::cpu.data 81.534494 # Average occupied blocks per requestor 566system.cpu.dcache.tags.occ_percent::cpu.data 0.019906 # Average percentage of cache occupancy 567system.cpu.dcache.tags.occ_percent::total 0.019906 # Average percentage of cache occupancy 568system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id 569system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 570system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 571system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id 572system.cpu.dcache.tags.tag_accesses 5685 # Number of tag accesses 573system.cpu.dcache.tags.data_accesses 5685 # Number of data accesses | 566system.cpu.dcache.tags.replacements 0 # number of replacements 567system.cpu.dcache.tags.tagsinuse 81.534494 # Cycle average of tags in use 568system.cpu.dcache.tags.total_refs 2583 # Total number of references to valid blocks. 569system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks. 570system.cpu.dcache.tags.avg_refs 18.582734 # Average number of references to valid blocks. 571system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 572system.cpu.dcache.tags.occ_blocks::cpu.data 81.534494 # Average occupied blocks per requestor 573system.cpu.dcache.tags.occ_percent::cpu.data 0.019906 # Average percentage of cache occupancy 574system.cpu.dcache.tags.occ_percent::total 0.019906 # Average percentage of cache occupancy 575system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id 576system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 577system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 578system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id 579system.cpu.dcache.tags.tag_accesses 5685 # Number of tag accesses 580system.cpu.dcache.tags.data_accesses 5685 # Number of data accesses |
| 581system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states |
|
| 574system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits 575system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits 576system.cpu.dcache.WriteReq_hits::cpu.data 860 # number of WriteReq hits 577system.cpu.dcache.WriteReq_hits::total 860 # number of WriteReq hits 578system.cpu.dcache.demand_hits::cpu.data 2583 # number of demand (read+write) hits 579system.cpu.dcache.demand_hits::total 2583 # number of demand (read+write) hits 580system.cpu.dcache.overall_hits::cpu.data 2583 # number of overall hits 581system.cpu.dcache.overall_hits::total 2583 # number of overall hits --- 76 unchanged lines hidden (view full) --- 658system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85304.687500 # average ReadReq mshr miss latency 659system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85304.687500 # average ReadReq mshr miss latency 660system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82006.666667 # average WriteReq mshr miss latency 661system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82006.666667 # average WriteReq mshr miss latency 662system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency 663system.cpu.dcache.demand_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency 664system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency 665system.cpu.dcache.overall_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency | 582system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits 583system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits 584system.cpu.dcache.WriteReq_hits::cpu.data 860 # number of WriteReq hits 585system.cpu.dcache.WriteReq_hits::total 860 # number of WriteReq hits 586system.cpu.dcache.demand_hits::cpu.data 2583 # number of demand (read+write) hits 587system.cpu.dcache.demand_hits::total 2583 # number of demand (read+write) hits 588system.cpu.dcache.overall_hits::cpu.data 2583 # number of overall hits 589system.cpu.dcache.overall_hits::total 2583 # number of overall hits --- 76 unchanged lines hidden (view full) --- 666system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85304.687500 # average ReadReq mshr miss latency 667system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85304.687500 # average ReadReq mshr miss latency 668system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82006.666667 # average WriteReq mshr miss latency 669system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82006.666667 # average WriteReq mshr miss latency 670system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency 671system.cpu.dcache.demand_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency 672system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency 673system.cpu.dcache.overall_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency |
| 674system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states |
|
| 666system.cpu.icache.tags.replacements 0 # number of replacements 667system.cpu.icache.tags.tagsinuse 130.801873 # Cycle average of tags in use 668system.cpu.icache.tags.total_refs 1651 # Total number of references to valid blocks. 669system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. 670system.cpu.icache.tags.avg_refs 5.938849 # Average number of references to valid blocks. 671system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 672system.cpu.icache.tags.occ_blocks::cpu.inst 130.801873 # Average occupied blocks per requestor 673system.cpu.icache.tags.occ_percent::cpu.inst 0.063868 # Average percentage of cache occupancy 674system.cpu.icache.tags.occ_percent::total 0.063868 # Average percentage of cache occupancy 675system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id 676system.cpu.icache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id 677system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 678system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id 679system.cpu.icache.tags.tag_accesses 4350 # Number of tag accesses 680system.cpu.icache.tags.data_accesses 4350 # Number of data accesses | 675system.cpu.icache.tags.replacements 0 # number of replacements 676system.cpu.icache.tags.tagsinuse 130.801873 # Cycle average of tags in use 677system.cpu.icache.tags.total_refs 1651 # Total number of references to valid blocks. 678system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. 679system.cpu.icache.tags.avg_refs 5.938849 # Average number of references to valid blocks. 680system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 681system.cpu.icache.tags.occ_blocks::cpu.inst 130.801873 # Average occupied blocks per requestor 682system.cpu.icache.tags.occ_percent::cpu.inst 0.063868 # Average percentage of cache occupancy 683system.cpu.icache.tags.occ_percent::total 0.063868 # Average percentage of cache occupancy 684system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id 685system.cpu.icache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id 686system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 687system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id 688system.cpu.icache.tags.tag_accesses 4350 # Number of tag accesses 689system.cpu.icache.tags.data_accesses 4350 # Number of data accesses |
| 690system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states |
|
| 681system.cpu.icache.ReadReq_hits::cpu.inst 1651 # number of ReadReq hits 682system.cpu.icache.ReadReq_hits::total 1651 # number of ReadReq hits 683system.cpu.icache.demand_hits::cpu.inst 1651 # number of demand (read+write) hits 684system.cpu.icache.demand_hits::total 1651 # number of demand (read+write) hits 685system.cpu.icache.overall_hits::cpu.inst 1651 # number of overall hits 686system.cpu.icache.overall_hits::total 1651 # number of overall hits 687system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses 688system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 745system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for overall accesses 746system.cpu.icache.overall_mshr_miss_rate::total 0.136542 # mshr miss rate for overall accesses 747system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78663.669065 # average ReadReq mshr miss latency 748system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78663.669065 # average ReadReq mshr miss latency 749system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency 750system.cpu.icache.demand_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency 751system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency 752system.cpu.icache.overall_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency | 691system.cpu.icache.ReadReq_hits::cpu.inst 1651 # number of ReadReq hits 692system.cpu.icache.ReadReq_hits::total 1651 # number of ReadReq hits 693system.cpu.icache.demand_hits::cpu.inst 1651 # number of demand (read+write) hits 694system.cpu.icache.demand_hits::total 1651 # number of demand (read+write) hits 695system.cpu.icache.overall_hits::cpu.inst 1651 # number of overall hits 696system.cpu.icache.overall_hits::total 1651 # number of overall hits 697system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses 698system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 755system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for overall accesses 756system.cpu.icache.overall_mshr_miss_rate::total 0.136542 # mshr miss rate for overall accesses 757system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78663.669065 # average ReadReq mshr miss latency 758system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78663.669065 # average ReadReq mshr miss latency 759system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency 760system.cpu.icache.demand_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency 761system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency 762system.cpu.icache.overall_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency |
| 763system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states |
|
| 753system.cpu.l2cache.tags.replacements 0 # number of replacements 754system.cpu.l2cache.tags.tagsinuse 163.058861 # Cycle average of tags in use 755system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 756system.cpu.l2cache.tags.sampled_refs 341 # Sample count of references to valid blocks. 757system.cpu.l2cache.tags.avg_refs 0.002933 # Average number of references to valid blocks. 758system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 759system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.841735 # Average occupied blocks per requestor 760system.cpu.l2cache.tags.occ_blocks::cpu.data 32.217126 # Average occupied blocks per requestor 761system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003993 # Average percentage of cache occupancy 762system.cpu.l2cache.tags.occ_percent::cpu.data 0.000983 # Average percentage of cache occupancy 763system.cpu.l2cache.tags.occ_percent::total 0.004976 # Average percentage of cache occupancy 764system.cpu.l2cache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id 765system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id 766system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 767system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010406 # Percentage of cache occupancy per task id 768system.cpu.l2cache.tags.tag_accesses 3752 # Number of tag accesses 769system.cpu.l2cache.tags.data_accesses 3752 # Number of data accesses | 764system.cpu.l2cache.tags.replacements 0 # number of replacements 765system.cpu.l2cache.tags.tagsinuse 163.058861 # Cycle average of tags in use 766system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 767system.cpu.l2cache.tags.sampled_refs 341 # Sample count of references to valid blocks. 768system.cpu.l2cache.tags.avg_refs 0.002933 # Average number of references to valid blocks. 769system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 770system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.841735 # Average occupied blocks per requestor 771system.cpu.l2cache.tags.occ_blocks::cpu.data 32.217126 # Average occupied blocks per requestor 772system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003993 # Average percentage of cache occupancy 773system.cpu.l2cache.tags.occ_percent::cpu.data 0.000983 # Average percentage of cache occupancy 774system.cpu.l2cache.tags.occ_percent::total 0.004976 # Average percentage of cache occupancy 775system.cpu.l2cache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id 776system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id 777system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 778system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010406 # Percentage of cache occupancy per task id 779system.cpu.l2cache.tags.tag_accesses 3752 # Number of tag accesses 780system.cpu.l2cache.tags.data_accesses 3752 # Number of data accesses |
| 781system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states |
|
| 770system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 771system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 772system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 773system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 774system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 775system.cpu.l2cache.overall_hits::total 1 # number of overall hits 776system.cpu.l2cache.ReadExReq_misses::cpu.data 75 # number of ReadExReq misses 777system.cpu.l2cache.ReadExReq_misses::total 75 # number of ReadExReq misses --- 110 unchanged lines hidden (view full) --- 888system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency 889system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency 890system.cpu.toL2Bus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. 891system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 892system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 893system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 894system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 895system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 782system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 783system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 784system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 785system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 786system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 787system.cpu.l2cache.overall_hits::total 1 # number of overall hits 788system.cpu.l2cache.ReadExReq_misses::cpu.data 75 # number of ReadExReq misses 789system.cpu.l2cache.ReadExReq_misses::total 75 # number of ReadExReq misses --- 110 unchanged lines hidden (view full) --- 900system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency 901system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency 902system.cpu.toL2Bus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. 903system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 904system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 905system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 906system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 907system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 908system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states |
|
| 896system.cpu.toL2Bus.trans_dist::ReadResp 342 # Transaction distribution 897system.cpu.toL2Bus.trans_dist::ReadExReq 75 # Transaction distribution 898system.cpu.toL2Bus.trans_dist::ReadExResp 75 # Transaction distribution 899system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution 900system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution 901system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes) 902system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes) 903system.cpu.toL2Bus.pkt_count::total 834 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 917system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 918system.cpu.toL2Bus.snoop_fanout::total 417 # Request fanout histogram 919system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) 920system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 921system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks) 922system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 923system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks) 924system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) | 909system.cpu.toL2Bus.trans_dist::ReadResp 342 # Transaction distribution 910system.cpu.toL2Bus.trans_dist::ReadExReq 75 # Transaction distribution 911system.cpu.toL2Bus.trans_dist::ReadExResp 75 # Transaction distribution 912system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution 913system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution 914system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes) 915system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes) 916system.cpu.toL2Bus.pkt_count::total 834 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 930system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 931system.cpu.toL2Bus.snoop_fanout::total 417 # Request fanout histogram 932system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) 933system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 934system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks) 935system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 936system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks) 937system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) |
| 938system.membus.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states |
|
| 925system.membus.trans_dist::ReadResp 341 # Transaction distribution 926system.membus.trans_dist::ReadExReq 75 # Transaction distribution 927system.membus.trans_dist::ReadExResp 75 # Transaction distribution 928system.membus.trans_dist::ReadSharedReq 341 # Transaction distribution 929system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) 930system.membus.pkt_count_system.cpu.l2cache.mem_side::total 832 # Packet count per connected master and slave (bytes) 931system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) 932system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) --- 19 unchanged lines hidden --- | 939system.membus.trans_dist::ReadResp 341 # Transaction distribution 940system.membus.trans_dist::ReadExReq 75 # Transaction distribution 941system.membus.trans_dist::ReadExResp 75 # Transaction distribution 942system.membus.trans_dist::ReadSharedReq 341 # Transaction distribution 943system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) 944system.membus.pkt_count_system.cpu.l2cache.mem_side::total 832 # Packet count per connected master and slave (bytes) 945system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) 946system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) --- 19 unchanged lines hidden --- |