| stats.txt (11440:76b5639162af) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated 4sim_ticks 21273500 # Number of ticks simulated 5final_tick 21273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated 4sim_ticks 21273500 # Number of ticks simulated 5final_tick 21273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 39176 # Simulator instruction rate (inst/s) 8host_op_rate 70969 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 151562567 # Simulator tick rate (ticks/s) 10host_mem_usage 245924 # Number of bytes of host memory used 11host_seconds 0.14 # Real time elapsed on the host | 7host_inst_rate 70008 # Simulator instruction rate (inst/s) 8host_op_rate 126817 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 276755373 # Simulator tick rate (ticks/s) 10host_mem_usage 271684 # Number of bytes of host memory used 11host_seconds 0.08 # Real time elapsed on the host |
| 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory --- 600 unchanged lines hidden (view full) --- 620system.cpu.dcache.overall_avg_miss_latency::cpu.data 80336.842105 # average overall miss latency 621system.cpu.dcache.overall_avg_miss_latency::total 80336.842105 # average overall miss latency 622system.cpu.dcache.blocked_cycles::no_mshrs 122 # number of cycles access was blocked 623system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 624system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 625system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 626system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.666667 # average number of cycles each access was blocked 627system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory --- 600 unchanged lines hidden (view full) --- 620system.cpu.dcache.overall_avg_miss_latency::cpu.data 80336.842105 # average overall miss latency 621system.cpu.dcache.overall_avg_miss_latency::total 80336.842105 # average overall miss latency 622system.cpu.dcache.blocked_cycles::no_mshrs 122 # number of cycles access was blocked 623system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 624system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 625system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 626system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.666667 # average number of cycles each access was blocked 627system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 628system.cpu.dcache.fast_writes 0 # number of fast writes performed 629system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 630system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits 631system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits 632system.cpu.dcache.demand_mshr_hits::cpu.data 51 # number of demand (read+write) MSHR hits 633system.cpu.dcache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits 634system.cpu.dcache.overall_mshr_hits::cpu.data 51 # number of overall MSHR hits 635system.cpu.dcache.overall_mshr_hits::total 51 # number of overall MSHR hits 636system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 637system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses --- 22 unchanged lines hidden (view full) --- 660system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85304.687500 # average ReadReq mshr miss latency 661system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85304.687500 # average ReadReq mshr miss latency 662system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82006.666667 # average WriteReq mshr miss latency 663system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82006.666667 # average WriteReq mshr miss latency 664system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency 665system.cpu.dcache.demand_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency 666system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency 667system.cpu.dcache.overall_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency | 628system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits 629system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits 630system.cpu.dcache.demand_mshr_hits::cpu.data 51 # number of demand (read+write) MSHR hits 631system.cpu.dcache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits 632system.cpu.dcache.overall_mshr_hits::cpu.data 51 # number of overall MSHR hits 633system.cpu.dcache.overall_mshr_hits::total 51 # number of overall MSHR hits 634system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 635system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses --- 22 unchanged lines hidden (view full) --- 658system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85304.687500 # average ReadReq mshr miss latency 659system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85304.687500 # average ReadReq mshr miss latency 660system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82006.666667 # average WriteReq mshr miss latency 661system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82006.666667 # average WriteReq mshr miss latency 662system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency 663system.cpu.dcache.demand_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency 664system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency 665system.cpu.dcache.overall_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency |
| 668system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 669system.cpu.icache.tags.replacements 0 # number of replacements 670system.cpu.icache.tags.tagsinuse 130.801873 # Cycle average of tags in use 671system.cpu.icache.tags.total_refs 1651 # Total number of references to valid blocks. 672system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. 673system.cpu.icache.tags.avg_refs 5.938849 # Average number of references to valid blocks. 674system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 675system.cpu.icache.tags.occ_blocks::cpu.inst 130.801873 # Average occupied blocks per requestor 676system.cpu.icache.tags.occ_percent::cpu.inst 0.063868 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 718system.cpu.icache.overall_avg_miss_latency::cpu.inst 74068.831169 # average overall miss latency 719system.cpu.icache.overall_avg_miss_latency::total 74068.831169 # average overall miss latency 720system.cpu.icache.blocked_cycles::no_mshrs 142 # number of cycles access was blocked 721system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 722system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 723system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 724system.cpu.icache.avg_blocked_cycles::no_mshrs 47.333333 # average number of cycles each access was blocked 725system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 666system.cpu.icache.tags.replacements 0 # number of replacements 667system.cpu.icache.tags.tagsinuse 130.801873 # Cycle average of tags in use 668system.cpu.icache.tags.total_refs 1651 # Total number of references to valid blocks. 669system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. 670system.cpu.icache.tags.avg_refs 5.938849 # Average number of references to valid blocks. 671system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 672system.cpu.icache.tags.occ_blocks::cpu.inst 130.801873 # Average occupied blocks per requestor 673system.cpu.icache.tags.occ_percent::cpu.inst 0.063868 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 715system.cpu.icache.overall_avg_miss_latency::cpu.inst 74068.831169 # average overall miss latency 716system.cpu.icache.overall_avg_miss_latency::total 74068.831169 # average overall miss latency 717system.cpu.icache.blocked_cycles::no_mshrs 142 # number of cycles access was blocked 718system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 719system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 720system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 721system.cpu.icache.avg_blocked_cycles::no_mshrs 47.333333 # average number of cycles each access was blocked 722system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 726system.cpu.icache.fast_writes 0 # number of fast writes performed 727system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 728system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # number of ReadReq MSHR hits 729system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits 730system.cpu.icache.demand_mshr_hits::cpu.inst 107 # number of demand (read+write) MSHR hits 731system.cpu.icache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits 732system.cpu.icache.overall_mshr_hits::cpu.inst 107 # number of overall MSHR hits 733system.cpu.icache.overall_mshr_hits::total 107 # number of overall MSHR hits 734system.cpu.icache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 735system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses --- 14 unchanged lines hidden (view full) --- 750system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for overall accesses 751system.cpu.icache.overall_mshr_miss_rate::total 0.136542 # mshr miss rate for overall accesses 752system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78663.669065 # average ReadReq mshr miss latency 753system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78663.669065 # average ReadReq mshr miss latency 754system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency 755system.cpu.icache.demand_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency 756system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency 757system.cpu.icache.overall_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency | 723system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # number of ReadReq MSHR hits 724system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits 725system.cpu.icache.demand_mshr_hits::cpu.inst 107 # number of demand (read+write) MSHR hits 726system.cpu.icache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits 727system.cpu.icache.overall_mshr_hits::cpu.inst 107 # number of overall MSHR hits 728system.cpu.icache.overall_mshr_hits::total 107 # number of overall MSHR hits 729system.cpu.icache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 730system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses --- 14 unchanged lines hidden (view full) --- 745system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for overall accesses 746system.cpu.icache.overall_mshr_miss_rate::total 0.136542 # mshr miss rate for overall accesses 747system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78663.669065 # average ReadReq mshr miss latency 748system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78663.669065 # average ReadReq mshr miss latency 749system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency 750system.cpu.icache.demand_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency 751system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency 752system.cpu.icache.overall_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency |
| 758system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 759system.cpu.l2cache.tags.replacements 0 # number of replacements 760system.cpu.l2cache.tags.tagsinuse 163.058861 # Cycle average of tags in use 761system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 762system.cpu.l2cache.tags.sampled_refs 341 # Sample count of references to valid blocks. 763system.cpu.l2cache.tags.avg_refs 0.002933 # Average number of references to valid blocks. 764system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 765system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.841735 # Average occupied blocks per requestor 766system.cpu.l2cache.tags.occ_blocks::cpu.data 32.217126 # Average occupied blocks per requestor --- 73 unchanged lines hidden (view full) --- 840system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82014.388489 # average overall miss latency 841system.cpu.l2cache.overall_avg_miss_latency::total 78941.105769 # average overall miss latency 842system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 843system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 844system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 845system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 846system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 847system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 753system.cpu.l2cache.tags.replacements 0 # number of replacements 754system.cpu.l2cache.tags.tagsinuse 163.058861 # Cycle average of tags in use 755system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 756system.cpu.l2cache.tags.sampled_refs 341 # Sample count of references to valid blocks. 757system.cpu.l2cache.tags.avg_refs 0.002933 # Average number of references to valid blocks. 758system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 759system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.841735 # Average occupied blocks per requestor 760system.cpu.l2cache.tags.occ_blocks::cpu.data 32.217126 # Average occupied blocks per requestor --- 73 unchanged lines hidden (view full) --- 834system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82014.388489 # average overall miss latency 835system.cpu.l2cache.overall_avg_miss_latency::total 78941.105769 # average overall miss latency 836system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 837system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 838system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 839system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 840system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 841system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 848system.cpu.l2cache.fast_writes 0 # number of fast writes performed 849system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 850system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 75 # number of ReadExReq MSHR misses 851system.cpu.l2cache.ReadExReq_mshr_misses::total 75 # number of ReadExReq MSHR misses 852system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses 853system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses 854system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses 855system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses 856system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses 857system.cpu.l2cache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 890system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73789.062500 # average ReadSharedReq mshr miss latency 891system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73789.062500 # average ReadSharedReq mshr miss latency 892system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency 893system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency 894system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency 895system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency 896system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency 897system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency | 842system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 75 # number of ReadExReq MSHR misses 843system.cpu.l2cache.ReadExReq_mshr_misses::total 75 # number of ReadExReq MSHR misses 844system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses 845system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses 846system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses 847system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses 848system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses 849system.cpu.l2cache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 882system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73789.062500 # average ReadSharedReq mshr miss latency 883system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73789.062500 # average ReadSharedReq mshr miss latency 884system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency 885system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency 886system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency 887system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency 888system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency 889system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency |
| 898system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 899system.cpu.toL2Bus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. 900system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 901system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 902system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 903system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 904system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 905system.cpu.toL2Bus.trans_dist::ReadResp 342 # Transaction distribution 906system.cpu.toL2Bus.trans_dist::ReadExReq 75 # Transaction distribution --- 54 unchanged lines hidden --- | 890system.cpu.toL2Bus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. 891system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 892system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 893system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 894system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 895system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 896system.cpu.toL2Bus.trans_dist::ReadResp 342 # Transaction distribution 897system.cpu.toL2Bus.trans_dist::ReadExReq 75 # Transaction distribution --- 54 unchanged lines hidden --- |