| stats.txt (11384:e3cbd2823210) | stats.txt (11440:76b5639162af) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated |
| 4sim_ticks 20818000 # Number of ticks simulated 5final_tick 20818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 21273500 # Number of ticks simulated 5final_tick 21273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 39176 # Simulator instruction rate (inst/s) 8host_op_rate 70969 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 151562567 # Simulator tick rate (ticks/s) 10host_mem_usage 245924 # Number of bytes of host memory used 11host_seconds 0.14 # Real time elapsed on the host 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 39176 # Simulator instruction rate (inst/s) 8host_op_rate 70969 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 151562567 # Simulator tick rate (ticks/s) 10host_mem_usage 245924 # Number of bytes of host memory used 11host_seconds 0.14 # Real time elapsed on the host 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::total 26560 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory | 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory |
| 22system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory | 22system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory |
| 23system.physmem.num_reads::total 415 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 848496493 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 427322509 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1275819003 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 848496493 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 848496493 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 848496493 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 427322509 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1275819003 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 415 # Number of read requests accepted | 23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 833337251 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 418172844 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1251510095 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 833337251 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 833337251 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 833337251 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 418172844 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1251510095 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 416 # Number of read requests accepted |
| 33system.physmem.writeReqs 0 # Number of write requests accepted | 33system.physmem.writeReqs 0 # Number of write requests accepted |
| 34system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue | 34system.physmem.readBursts 416 # Number of DRAM read bursts, including those serviced by the write queue |
| 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 36system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM | 36system.physmem.bytesReadDRAM 26624 # Total number of bytes read from DRAM |
| 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 39system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side | 39system.physmem.bytesReadSys 26624 # Total read bytes from the system interface side |
| 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 44system.physmem.perBankRdBursts::0 32 # Per bank write bursts | 44system.physmem.perBankRdBursts::0 31 # Per bank write bursts |
| 45system.physmem.perBankRdBursts::1 1 # Per bank write bursts | 45system.physmem.perBankRdBursts::1 1 # Per bank write bursts |
| 46system.physmem.perBankRdBursts::2 6 # Per bank write bursts | 46system.physmem.perBankRdBursts::2 5 # Per bank write bursts |
| 47system.physmem.perBankRdBursts::3 8 # Per bank write bursts | 47system.physmem.perBankRdBursts::3 8 # Per bank write bursts |
| 48system.physmem.perBankRdBursts::4 50 # Per bank write bursts 49system.physmem.perBankRdBursts::5 46 # Per bank write bursts | 48system.physmem.perBankRdBursts::4 51 # Per bank write bursts 49system.physmem.perBankRdBursts::5 44 # Per bank write bursts |
| 50system.physmem.perBankRdBursts::6 21 # Per bank write bursts | 50system.physmem.perBankRdBursts::6 21 # Per bank write bursts |
| 51system.physmem.perBankRdBursts::7 33 # Per bank write bursts 52system.physmem.perBankRdBursts::8 25 # Per bank write bursts 53system.physmem.perBankRdBursts::9 72 # Per bank write bursts 54system.physmem.perBankRdBursts::10 63 # Per bank write bursts | 51system.physmem.perBankRdBursts::7 37 # Per bank write bursts 52system.physmem.perBankRdBursts::8 23 # Per bank write bursts 53system.physmem.perBankRdBursts::9 71 # Per bank write bursts 54system.physmem.perBankRdBursts::10 64 # Per bank write bursts |
| 55system.physmem.perBankRdBursts::11 16 # Per bank write bursts 56system.physmem.perBankRdBursts::12 2 # Per bank write bursts | 55system.physmem.perBankRdBursts::11 16 # Per bank write bursts 56system.physmem.perBankRdBursts::12 2 # Per bank write bursts |
| 57system.physmem.perBankRdBursts::13 17 # Per bank write bursts | 57system.physmem.perBankRdBursts::13 19 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::14 6 # Per bank write bursts 59system.physmem.perBankRdBursts::15 17 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts --- 4 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 58system.physmem.perBankRdBursts::14 6 # Per bank write bursts 59system.physmem.perBankRdBursts::15 17 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts --- 4 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 20722000 # Total gap between requests | 78system.physmem.totGap 21151500 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 85system.physmem.readPktSize::6 415 # Read request sizes (log2) | 85system.physmem.readPktSize::6 416 # Read request sizes (log2) |
| 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see | 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see |
| 95system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see | 95system.physmem.rdQLenPdf::2 39 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see |
| 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 96 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 252 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 164.484740 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 262.126687 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 35 36.46% 36.46% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 26 27.08% 63.54% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 15 15.62% 79.17% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 6 6.25% 85.42% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 3.12% 88.54% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 3 3.12% 91.67% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 2 2.08% 93.75% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 1 1.04% 94.79% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 5 5.21% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 96 # Bytes accessed per row activation 203system.physmem.totQLat 4745000 # Total ticks spent queuing 204system.physmem.totMemAccLat 12526250 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 11433.73 # Average queueing delay per DRAM burst | 189system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 250.721649 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 162.086023 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 265.276929 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 37 38.14% 38.14% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 25 25.77% 63.92% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 18 18.56% 82.47% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 3 3.09% 85.57% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 2 2.06% 87.63% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 2.06% 89.69% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 4 4.12% 93.81% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 1 1.03% 94.85% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation 203system.physmem.totQLat 4187000 # Total ticks spent queuing 204system.physmem.totMemAccLat 11987000 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 2080000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 10064.90 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 30183.73 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1275.82 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 28814.90 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1251.51 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 1275.82 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 1251.51 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 214system.physmem.busUtil 9.97 # Data bus utilization in percentage 215system.physmem.busUtilRead 9.97 # Data bus utilization in percentage for reads | 214system.physmem.busUtil 9.78 # Data bus utilization in percentage 215system.physmem.busUtilRead 9.78 # Data bus utilization in percentage for reads |
| 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 217system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing | 217system.physmem.avgRdQLen 1.63 # Average read queue length when enqueuing |
| 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 309 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 309 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.physmem.readRowHitRate 74.46 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 74.28 # Row buffer hit rate for reads |
| 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 49932.53 # Average gap between requests 224system.physmem.pageHitRate 74.46 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 959400 # Energy for read commands per rank (pJ) | 223system.physmem.avgGap 50844.95 # Average gap between requests 224system.physmem.pageHitRate 74.28 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 920400 # Energy for read commands per rank (pJ) |
| 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) | 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) |
| 232system.physmem_0.totalEnergy 13105245 # Total energy per rank (pJ) 233system.physmem_0.averagePower 827.743250 # Core power per rank (mW) | 232system.physmem_0.totalEnergy 13042875 # Total energy per rank (pJ) 233system.physmem_0.averagePower 823.803884 # Core power per rank (mW) |
| 234system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states 235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 234system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states 235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 239system.physmem_1.actEnergy 423360 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 231000 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 1536600 # Energy for read commands per rank (pJ) | 239system.physmem_1.actEnergy 415800 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 226875 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) |
| 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 10696905 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ) | 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 10696905 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ) |
| 246system.physmem_1.totalEnergy 14021235 # Total energy per rank (pJ) 247system.physmem_1.averagePower 885.598295 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 271750 # Time in different power states | 246system.physmem_1.totalEnergy 13993950 # Total energy per rank (pJ) 247system.physmem_1.averagePower 883.874941 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 262750 # Time in different power states |
| 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 15224250 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 15224250 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.cpu.branchPred.lookups 3234 # Number of BP lookups 254system.cpu.branchPred.condPredicted 3234 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 514 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 2557 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 881 # Number of BTB hits | 253system.cpu.branchPred.lookups 3510 # Number of BP lookups 254system.cpu.branchPred.condPredicted 3510 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 564 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 2934 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 0 # Number of BTB hits |
| 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 259system.cpu.branchPred.BTBHitPct 34.454439 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 280 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 86 # Number of incorrect RAS predictions. | 259system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 413 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 93 # Number of incorrect RAS predictions. 262system.cpu.branchPred.indirectLookups 2934 # Number of indirect predictor lookups. 263system.cpu.branchPred.indirectHits 493 # Number of indirect target hits. 264system.cpu.branchPred.indirectMisses 2441 # Number of indirect misses. 265system.cpu.branchPredindirectMispredicted 404 # Number of mispredicted indirect branches. |
| 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 264system.cpu.workload.num_syscalls 11 # Number of system calls | 266system.cpu_clk_domain.clock 500 # Clock period in ticks 267system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 268system.cpu.workload.num_syscalls 11 # Number of system calls |
| 265system.cpu.numCycles 41637 # number of cpu cycles simulated | 269system.cpu.numCycles 42548 # number of cpu cycles simulated |
| 266system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 267system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 270system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 271system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 268system.cpu.fetch.icacheStallCycles 11661 # Number of cycles fetch is stalled on an Icache miss 269system.cpu.fetch.Insts 14637 # Number of instructions fetch has processed 270system.cpu.fetch.Branches 3234 # Number of branches that fetch encountered 271system.cpu.fetch.predictedBranches 1161 # Number of branches that fetch has predicted taken 272system.cpu.fetch.Cycles 9674 # Number of cycles fetch has run and was not squashing or blocked 273system.cpu.fetch.SquashCycles 1159 # Number of cycles fetch has spent squashing 274system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 275system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps 276system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions 277system.cpu.fetch.CacheLines 2075 # Number of cache lines fetched 278system.cpu.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed 279system.cpu.fetch.rateDist::samples 22725 # Number of instructions fetched each cycle (Total) 280system.cpu.fetch.rateDist::mean 1.149527 # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::stdev 2.648759 # Number of instructions fetched each cycle (Total) | 272system.cpu.fetch.icacheStallCycles 11447 # Number of cycles fetch is stalled on an Icache miss 273system.cpu.fetch.Insts 15916 # Number of instructions fetch has processed 274system.cpu.fetch.Branches 3510 # Number of branches that fetch encountered 275system.cpu.fetch.predictedBranches 906 # Number of branches that fetch has predicted taken 276system.cpu.fetch.Cycles 9652 # Number of cycles fetch has run and was not squashing or blocked 277system.cpu.fetch.SquashCycles 1329 # Number of cycles fetch has spent squashing 278system.cpu.fetch.MiscStallCycles 93 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 279system.cpu.fetch.PendingTrapStallCycles 1405 # Number of stall cycles due to pending traps 280system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions 281system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR 282system.cpu.fetch.CacheLines 2036 # Number of cache lines fetched 283system.cpu.fetch.IcacheSquashes 273 # Number of outstanding Icache misses that were squashed 284system.cpu.fetch.rateDist::samples 23302 # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::mean 1.230495 # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::stdev 2.752458 # Number of instructions fetched each cycle (Total) |
| 282system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 287system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 283system.cpu.fetch.rateDist::0 18699 82.28% 82.28% # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::1 221 0.97% 83.26% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::2 146 0.64% 83.90% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::3 231 1.02% 84.92% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::4 214 0.94% 85.86% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::5 258 1.14% 86.99% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::6 336 1.48% 88.47% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::7 205 0.90% 89.37% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::8 2415 10.63% 100.00% # Number of instructions fetched each cycle (Total) | 288system.cpu.fetch.rateDist::0 19034 81.68% 81.68% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::1 165 0.71% 82.39% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::2 157 0.67% 83.07% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::3 234 1.00% 84.07% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::4 217 0.93% 85.00% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::5 212 0.91% 85.91% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::6 264 1.13% 87.04% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::7 172 0.74% 87.78% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::8 2847 12.22% 100.00% # Number of instructions fetched each cycle (Total) |
| 292system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 297system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 295system.cpu.fetch.rateDist::total 22725 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.branchRate 0.077671 # Number of branch fetches per cycle 297system.cpu.fetch.rate 0.351538 # Number of inst fetches per cycle 298system.cpu.decode.IdleCycles 11462 # Number of cycles decode is idle 299system.cpu.decode.BlockedCycles 7072 # Number of cycles decode is blocked 300system.cpu.decode.RunCycles 3206 # Number of cycles decode is running 301system.cpu.decode.UnblockCycles 406 # Number of cycles decode is unblocking 302system.cpu.decode.SquashCycles 579 # Number of cycles decode is squashing 303system.cpu.decode.DecodedInsts 24310 # Number of instructions handled by decode 304system.cpu.rename.SquashCycles 579 # Number of cycles rename is squashing 305system.cpu.rename.IdleCycles 11710 # Number of cycles rename is idle 306system.cpu.rename.BlockCycles 1815 # Number of cycles rename is blocking 307system.cpu.rename.serializeStallCycles 1004 # count of cycles rename stalled for serializing inst 308system.cpu.rename.RunCycles 3327 # Number of cycles rename is running 309system.cpu.rename.UnblockCycles 4290 # Number of cycles rename is unblocking 310system.cpu.rename.RenamedInsts 23005 # Number of instructions processed by rename 311system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full 312system.cpu.rename.IQFullEvents 71 # Number of times rename has blocked due to IQ full 313system.cpu.rename.SQFullEvents 4163 # Number of times rename has blocked due to SQ full 314system.cpu.rename.RenamedOperands 26169 # Number of destination operands rename has renamed 315system.cpu.rename.RenameLookups 57126 # Number of register rename lookups that rename has made 316system.cpu.rename.int_rename_lookups 32219 # Number of integer rename lookups | 300system.cpu.fetch.rateDist::total 23302 # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.branchRate 0.082495 # Number of branch fetches per cycle 302system.cpu.fetch.rate 0.374072 # Number of inst fetches per cycle 303system.cpu.decode.IdleCycles 11533 # Number of cycles decode is idle 304system.cpu.decode.BlockedCycles 7244 # Number of cycles decode is blocked 305system.cpu.decode.RunCycles 3404 # Number of cycles decode is running 306system.cpu.decode.UnblockCycles 457 # Number of cycles decode is unblocking 307system.cpu.decode.SquashCycles 664 # Number of cycles decode is squashing 308system.cpu.decode.DecodedInsts 26617 # Number of instructions handled by decode 309system.cpu.rename.SquashCycles 664 # Number of cycles rename is squashing 310system.cpu.rename.IdleCycles 11798 # Number of cycles rename is idle 311system.cpu.rename.BlockCycles 1942 # Number of cycles rename is blocking 312system.cpu.rename.serializeStallCycles 1135 # count of cycles rename stalled for serializing inst 313system.cpu.rename.RunCycles 3557 # Number of cycles rename is running 314system.cpu.rename.UnblockCycles 4206 # Number of cycles rename is unblocking 315system.cpu.rename.RenamedInsts 25098 # Number of instructions processed by rename 316system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full 317system.cpu.rename.IQFullEvents 80 # Number of times rename has blocked due to IQ full 318system.cpu.rename.SQFullEvents 4073 # Number of times rename has blocked due to SQ full 319system.cpu.rename.RenamedOperands 28145 # Number of destination operands rename has renamed 320system.cpu.rename.RenameLookups 61205 # Number of register rename lookups that rename has made 321system.cpu.rename.int_rename_lookups 35038 # Number of integer rename lookups |
| 317system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 318system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed | 322system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 323system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed |
| 319system.cpu.rename.UndoneMaps 15106 # Number of HB maps that are undone due to squashing 320system.cpu.rename.serializingInsts 28 # count of serializing insts renamed 321system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed 322system.cpu.rename.skidInsts 1472 # count of insts added to the skid buffer 323system.cpu.memDep0.insertedLoads 2371 # Number of loads inserted to the mem dependence unit. 324system.cpu.memDep0.insertedStores 1574 # Number of stores inserted to the mem dependence unit. 325system.cpu.memDep0.conflictingLoads 20 # Number of conflicting loads. 326system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. 327system.cpu.iq.iqInstsAdded 20445 # Number of instructions added to the IQ (excludes non-spec) 328system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ 329system.cpu.iq.iqInstsIssued 17161 # Number of instructions issued 330system.cpu.iq.iqSquashedInstsIssued 65 # Number of squashed instructions issued 331system.cpu.iq.iqSquashedInstsExamined 10724 # Number of squashed instructions iterated over during squash; mainly for profiling 332system.cpu.iq.iqSquashedOperandsExamined 15317 # Number of squashed operands that are examined and possibly removed from graph 333system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed 334system.cpu.iq.issued_per_cycle::samples 22725 # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::mean 0.755160 # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::stdev 1.702113 # Number of insts issued each cycle | 324system.cpu.rename.UndoneMaps 17082 # Number of HB maps that are undone due to squashing 325system.cpu.rename.serializingInsts 25 # count of serializing insts renamed 326system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed 327system.cpu.rename.skidInsts 1412 # count of insts added to the skid buffer 328system.cpu.memDep0.insertedLoads 2736 # Number of loads inserted to the mem dependence unit. 329system.cpu.memDep0.insertedStores 1550 # Number of stores inserted to the mem dependence unit. 330system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. 331system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. 332system.cpu.iq.iqInstsAdded 21864 # Number of instructions added to the IQ (excludes non-spec) 333system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ 334system.cpu.iq.iqInstsIssued 18142 # Number of instructions issued 335system.cpu.iq.iqSquashedInstsIssued 143 # Number of squashed instructions issued 336system.cpu.iq.iqSquashedInstsExamined 12140 # Number of squashed instructions iterated over during squash; mainly for profiling 337system.cpu.iq.iqSquashedOperandsExamined 16726 # Number of squashed operands that are examined and possibly removed from graph 338system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed 339system.cpu.iq.issued_per_cycle::samples 23302 # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::mean 0.778560 # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::stdev 1.752623 # Number of insts issued each cycle |
| 337system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 342system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 338system.cpu.iq.issued_per_cycle::0 17737 78.05% 78.05% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::1 1126 4.95% 83.01% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::2 880 3.87% 86.88% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::3 631 2.78% 89.65% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::4 810 3.56% 93.22% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::5 590 2.60% 95.82% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::6 568 2.50% 98.31% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::7 280 1.23% 99.55% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::8 103 0.45% 100.00% # Number of insts issued each cycle | 343system.cpu.iq.issued_per_cycle::0 18136 77.83% 77.83% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::1 1211 5.20% 83.03% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::2 861 3.69% 86.72% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::3 568 2.44% 89.16% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::4 833 3.57% 92.73% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::5 596 2.56% 95.29% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::6 620 2.66% 97.95% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::7 343 1.47% 99.42% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::8 134 0.58% 100.00% # Number of insts issued each cycle |
| 347system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 352system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 350system.cpu.iq.issued_per_cycle::total 22725 # Number of insts issued each cycle | 355system.cpu.iq.issued_per_cycle::total 23302 # Number of insts issued each cycle |
| 351system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 356system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 352system.cpu.iq.fu_full::IntAlu 151 71.23% 71.23% # attempts to use FU when none available 353system.cpu.iq.fu_full::IntMult 0 0.00% 71.23% # attempts to use FU when none available 354system.cpu.iq.fu_full::IntDiv 0 0.00% 71.23% # attempts to use FU when none available 355system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.23% # attempts to use FU when none available 356system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.23% # attempts to use FU when none available 357system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.23% # attempts to use FU when none available 358system.cpu.iq.fu_full::FloatMult 0 0.00% 71.23% # attempts to use FU when none available 359system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.23% # attempts to use FU when none available 360system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.23% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.23% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.23% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.23% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.23% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.23% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.23% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdMult 0 0.00% 71.23% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.23% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdShift 0 0.00% 71.23% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.23% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.23% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.23% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.23% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.23% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.23% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.23% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.23% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.23% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.23% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.23% # attempts to use FU when none available 381system.cpu.iq.fu_full::MemRead 43 20.28% 91.51% # attempts to use FU when none available 382system.cpu.iq.fu_full::MemWrite 18 8.49% 100.00% # attempts to use FU when none available | 357system.cpu.iq.fu_full::IntAlu 211 76.17% 76.17% # attempts to use FU when none available 358system.cpu.iq.fu_full::IntMult 0 0.00% 76.17% # attempts to use FU when none available 359system.cpu.iq.fu_full::IntDiv 0 0.00% 76.17% # attempts to use FU when none available 360system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.17% # attempts to use FU when none available 361system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.17% # attempts to use FU when none available 362system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.17% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatMult 0 0.00% 76.17% # attempts to use FU when none available 364system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.17% # attempts to use FU when none available 365system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.17% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.17% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.17% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.17% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.17% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.17% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.17% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdMult 0 0.00% 76.17% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.17% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdShift 0 0.00% 76.17% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.17% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.17% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.17% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.17% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.17% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.17% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.17% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.17% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.17% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.17% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.17% # attempts to use FU when none available 386system.cpu.iq.fu_full::MemRead 50 18.05% 94.22% # attempts to use FU when none available 387system.cpu.iq.fu_full::MemWrite 16 5.78% 100.00% # attempts to use FU when none available |
| 383system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 384system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 388system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 389system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 385system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued 386system.cpu.iq.FU_type_0::IntAlu 13707 79.87% 79.89% # Type of FU issued 387system.cpu.iq.FU_type_0::IntMult 4 0.02% 79.91% # Type of FU issued 388system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.95% # Type of FU issued 389system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.95% # Type of FU issued 390system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.95% # Type of FU issued 391system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.95% # Type of FU issued 392system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.95% # Type of FU issued 393system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.95% # Type of FU issued 394system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.95% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.95% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.95% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.95% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.95% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.95% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.95% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.95% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.95% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.95% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.95% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.95% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.95% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.95% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.95% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.95% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.95% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.95% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.95% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.95% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.95% # Type of FU issued 415system.cpu.iq.FU_type_0::MemRead 2071 12.07% 92.02% # Type of FU issued 416system.cpu.iq.FU_type_0::MemWrite 1369 7.98% 100.00% # Type of FU issued | 390system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued 391system.cpu.iq.FU_type_0::IntAlu 14465 79.73% 79.74% # Type of FU issued 392system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.78% # Type of FU issued 393system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.81% # Type of FU issued 394system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.81% # Type of FU issued 395system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.81% # Type of FU issued 396system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.81% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.81% # Type of FU issued 398system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.81% # Type of FU issued 399system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.81% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.81% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.81% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.81% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.81% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.81% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.81% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.81% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.81% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.81% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.81% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.81% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.81% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.81% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.81% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.81% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.81% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.81% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.81% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.81% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.81% # Type of FU issued 420system.cpu.iq.FU_type_0::MemRead 2325 12.82% 92.63% # Type of FU issued 421system.cpu.iq.FU_type_0::MemWrite 1337 7.37% 100.00% # Type of FU issued |
| 417system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 418system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 422system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 423system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 419system.cpu.iq.FU_type_0::total 17161 # Type of FU issued 420system.cpu.iq.rate 0.412157 # Inst issue rate 421system.cpu.iq.fu_busy_cnt 212 # FU busy when requested 422system.cpu.iq.fu_busy_rate 0.012354 # FU busy rate (busy events/executed inst) 423system.cpu.iq.int_inst_queue_reads 57316 # Number of integer instruction queue reads 424system.cpu.iq.int_inst_queue_writes 31202 # Number of integer instruction queue writes 425system.cpu.iq.int_inst_queue_wakeup_accesses 15767 # Number of integer instruction queue wakeup accesses | 424system.cpu.iq.FU_type_0::total 18142 # Type of FU issued 425system.cpu.iq.rate 0.426389 # Inst issue rate 426system.cpu.iq.fu_busy_cnt 277 # FU busy when requested 427system.cpu.iq.fu_busy_rate 0.015268 # FU busy rate (busy events/executed inst) 428system.cpu.iq.int_inst_queue_reads 59998 # Number of integer instruction queue reads 429system.cpu.iq.int_inst_queue_writes 34032 # Number of integer instruction queue writes 430system.cpu.iq.int_inst_queue_wakeup_accesses 16436 # Number of integer instruction queue wakeup accesses |
| 426system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 427system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes 428system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses | 431system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 432system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes 433system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses |
| 429system.cpu.iq.int_alu_accesses 17366 # Number of integer alu accesses | 434system.cpu.iq.int_alu_accesses 18413 # Number of integer alu accesses |
| 430system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses | 435system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses |
| 431system.cpu.iew.lsq.thread0.forwLoads 220 # Number of loads that had data forwarded from stores | 436system.cpu.iew.lsq.thread0.forwLoads 190 # Number of loads that had data forwarded from stores |
| 432system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 437system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 433system.cpu.iew.lsq.thread0.squashedLoads 1318 # Number of loads squashed | 438system.cpu.iew.lsq.thread0.squashedLoads 1683 # Number of loads squashed |
| 434system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed | 439system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed |
| 435system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations 436system.cpu.iew.lsq.thread0.squashedStores 639 # Number of stores squashed | 440system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations 441system.cpu.iew.lsq.thread0.squashedStores 615 # Number of stores squashed |
| 437system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 438system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 439system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled | 442system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 443system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 444system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled |
| 440system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked | 445system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked |
| 441system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 446system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 442system.cpu.iew.iewSquashCycles 579 # Number of cycles IEW is squashing 443system.cpu.iew.iewBlockCycles 1449 # Number of cycles IEW is blocking 444system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking 445system.cpu.iew.iewDispatchedInsts 20471 # Number of instructions dispatched to IQ 446system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch 447system.cpu.iew.iewDispLoadInsts 2371 # Number of dispatched load instructions 448system.cpu.iew.iewDispStoreInsts 1574 # Number of dispatched store instructions 449system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions 450system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall 451system.cpu.iew.iewLSQFullEvents 34 # Number of times the LSQ has become full, causing a stall 452system.cpu.iew.memOrderViolationEvents 15 # Number of memory order violations 453system.cpu.iew.predictedTakenIncorrect 136 # Number of branches that were predicted taken incorrectly 454system.cpu.iew.predictedNotTakenIncorrect 524 # Number of branches that were predicted not taken incorrectly 455system.cpu.iew.branchMispredicts 660 # Number of branch mispredicts detected at execute 456system.cpu.iew.iewExecutedInsts 16265 # Number of executed instructions 457system.cpu.iew.iewExecLoadInsts 1913 # Number of load instructions executed 458system.cpu.iew.iewExecSquashedInsts 896 # Number of squashed instructions skipped in execute | 447system.cpu.iew.iewSquashCycles 664 # Number of cycles IEW is squashing 448system.cpu.iew.iewBlockCycles 1478 # Number of cycles IEW is blocking 449system.cpu.iew.iewUnblockCycles 139 # Number of cycles IEW is unblocking 450system.cpu.iew.iewDispatchedInsts 21887 # Number of instructions dispatched to IQ 451system.cpu.iew.iewDispSquashedInsts 9 # Number of squashed instructions skipped by dispatch 452system.cpu.iew.iewDispLoadInsts 2736 # Number of dispatched load instructions 453system.cpu.iew.iewDispStoreInsts 1550 # Number of dispatched store instructions 454system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions 455system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 456system.cpu.iew.iewLSQFullEvents 138 # Number of times the LSQ has become full, causing a stall 457system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations 458system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly 459system.cpu.iew.predictedNotTakenIncorrect 682 # Number of branches that were predicted not taken incorrectly 460system.cpu.iew.branchMispredicts 801 # Number of branch mispredicts detected at execute 461system.cpu.iew.iewExecutedInsts 17060 # Number of executed instructions 462system.cpu.iew.iewExecLoadInsts 2081 # Number of load instructions executed 463system.cpu.iew.iewExecSquashedInsts 1082 # Number of squashed instructions skipped in execute |
| 459system.cpu.iew.exec_swp 0 # number of swp insts executed 460system.cpu.iew.exec_nop 0 # number of nop insts executed | 464system.cpu.iew.exec_swp 0 # number of swp insts executed 465system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 461system.cpu.iew.exec_refs 3175 # number of memory reference insts executed 462system.cpu.iew.exec_branches 1626 # Number of branches executed 463system.cpu.iew.exec_stores 1262 # Number of stores executed 464system.cpu.iew.exec_rate 0.390638 # Inst execution rate 465system.cpu.iew.wb_sent 16001 # cumulative count of insts sent to commit 466system.cpu.iew.wb_count 15771 # cumulative count of insts written-back 467system.cpu.iew.wb_producers 10637 # num instructions producing a value 468system.cpu.iew.wb_consumers 16589 # num instructions consuming a value 469system.cpu.iew.wb_rate 0.378774 # insts written-back per cycle 470system.cpu.iew.wb_fanout 0.641208 # average fanout of values written-back 471system.cpu.commit.commitSquashedInsts 10723 # The number of squashed insts skipped by commit | 466system.cpu.iew.exec_refs 3326 # number of memory reference insts executed 467system.cpu.iew.exec_branches 1722 # Number of branches executed 468system.cpu.iew.exec_stores 1245 # Number of stores executed 469system.cpu.iew.exec_rate 0.400959 # Inst execution rate 470system.cpu.iew.wb_sent 16760 # cumulative count of insts sent to commit 471system.cpu.iew.wb_count 16440 # cumulative count of insts written-back 472system.cpu.iew.wb_producers 11045 # num instructions producing a value 473system.cpu.iew.wb_consumers 17238 # num instructions consuming a value 474system.cpu.iew.wb_rate 0.386387 # insts written-back per cycle 475system.cpu.iew.wb_fanout 0.640736 # average fanout of values written-back 476system.cpu.commit.commitSquashedInsts 12139 # The number of squashed insts skipped by commit |
| 472system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards | 477system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards |
| 473system.cpu.commit.branchMispredicts 565 # The number of times a branch was mispredicted 474system.cpu.commit.committed_per_cycle::samples 20943 # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::mean 0.465406 # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::stdev 1.357230 # Number of insts commited each cycle | 478system.cpu.commit.branchMispredicts 652 # The number of times a branch was mispredicted 479system.cpu.commit.committed_per_cycle::samples 21245 # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::mean 0.458790 # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::stdev 1.350767 # Number of insts commited each cycle |
| 477system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 482system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 478system.cpu.commit.committed_per_cycle::0 17686 84.45% 84.45% # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::1 994 4.75% 89.19% # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::2 561 2.68% 91.87% # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::3 764 3.65% 95.52% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::4 370 1.77% 97.29% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::5 129 0.62% 97.90% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::6 114 0.54% 98.45% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::7 70 0.33% 98.78% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::8 255 1.22% 100.00% # Number of insts commited each cycle | 483system.cpu.commit.committed_per_cycle::0 17995 84.70% 84.70% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::1 991 4.66% 89.37% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::2 576 2.71% 92.08% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::3 726 3.42% 95.50% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::4 383 1.80% 97.30% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::5 128 0.60% 97.90% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::6 121 0.57% 98.47% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::7 72 0.34% 98.81% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::8 253 1.19% 100.00% # Number of insts commited each cycle |
| 487system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 492system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 490system.cpu.commit.committed_per_cycle::total 20943 # Number of insts commited each cycle | 495system.cpu.commit.committed_per_cycle::total 21245 # Number of insts commited each cycle |
| 491system.cpu.commit.committedInsts 5380 # Number of instructions committed 492system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed 493system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 494system.cpu.commit.refs 1988 # Number of memory references committed 495system.cpu.commit.loads 1053 # Number of loads committed 496system.cpu.commit.membars 0 # Number of memory barriers committed 497system.cpu.commit.branches 1208 # Number of branches committed 498system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 528system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction 530system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction 531system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction 532system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction 533system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 534system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 535system.cpu.commit.op_class_0::total 9747 # Class of committed instruction | 496system.cpu.commit.committedInsts 5380 # Number of instructions committed 497system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed 498system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 499system.cpu.commit.refs 1988 # Number of memory references committed 500system.cpu.commit.loads 1053 # Number of loads committed 501system.cpu.commit.membars 0 # Number of memory barriers committed 502system.cpu.commit.branches 1208 # Number of branches committed 503system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 533system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction 536system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction 537system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction 538system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 539system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 540system.cpu.commit.op_class_0::total 9747 # Class of committed instruction |
| 536system.cpu.commit.bw_lim_events 255 # number cycles where commit BW limit reached 537system.cpu.rob.rob_reads 41158 # The number of ROB reads 538system.cpu.rob.rob_writes 42744 # The number of ROB writes 539system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself 540system.cpu.idleCycles 18912 # Total number of cycles that the CPU has spent unscheduled due to idling | 541system.cpu.commit.bw_lim_events 253 # number cycles where commit BW limit reached 542system.cpu.rob.rob_reads 42878 # The number of ROB reads 543system.cpu.rob.rob_writes 45859 # The number of ROB writes 544system.cpu.timesIdled 160 # Number of times that the entire CPU went into an idle state and unscheduled itself 545system.cpu.idleCycles 19246 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 541system.cpu.committedInsts 5380 # Number of Instructions Simulated 542system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated | 546system.cpu.committedInsts 5380 # Number of Instructions Simulated 547system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated |
| 543system.cpu.cpi 7.739219 # CPI: Cycles Per Instruction 544system.cpu.cpi_total 7.739219 # CPI: Total CPI of All Threads 545system.cpu.ipc 0.129212 # IPC: Instructions Per Cycle 546system.cpu.ipc_total 0.129212 # IPC: Total IPC of All Threads 547system.cpu.int_regfile_reads 20872 # number of integer regfile reads 548system.cpu.int_regfile_writes 12651 # number of integer regfile writes | 548system.cpu.cpi 7.908550 # CPI: Cycles Per Instruction 549system.cpu.cpi_total 7.908550 # CPI: Total CPI of All Threads 550system.cpu.ipc 0.126445 # IPC: Instructions Per Cycle 551system.cpu.ipc_total 0.126445 # IPC: Total IPC of All Threads 552system.cpu.int_regfile_reads 21687 # number of integer regfile reads 553system.cpu.int_regfile_writes 13280 # number of integer regfile writes |
| 549system.cpu.fp_regfile_reads 4 # number of floating regfile reads | 554system.cpu.fp_regfile_reads 4 # number of floating regfile reads |
| 550system.cpu.cc_regfile_reads 8081 # number of cc regfile reads 551system.cpu.cc_regfile_writes 4880 # number of cc regfile writes 552system.cpu.misc_regfile_reads 7277 # number of misc regfile reads | 555system.cpu.cc_regfile_reads 8296 # number of cc regfile reads 556system.cpu.cc_regfile_writes 5092 # number of cc regfile writes 557system.cpu.misc_regfile_reads 7660 # number of misc regfile reads |
| 553system.cpu.misc_regfile_writes 1 # number of misc regfile writes 554system.cpu.dcache.tags.replacements 0 # number of replacements | 558system.cpu.misc_regfile_writes 1 # number of misc regfile writes 559system.cpu.dcache.tags.replacements 0 # number of replacements |
| 555system.cpu.dcache.tags.tagsinuse 81.973847 # Cycle average of tags in use 556system.cpu.dcache.tags.total_refs 2383 # Total number of references to valid blocks. | 560system.cpu.dcache.tags.tagsinuse 81.534494 # Cycle average of tags in use 561system.cpu.dcache.tags.total_refs 2583 # Total number of references to valid blocks. |
| 557system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks. | 562system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks. |
| 558system.cpu.dcache.tags.avg_refs 17.143885 # Average number of references to valid blocks. | 563system.cpu.dcache.tags.avg_refs 18.582734 # Average number of references to valid blocks. |
| 559system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 564system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 560system.cpu.dcache.tags.occ_blocks::cpu.data 81.973847 # Average occupied blocks per requestor 561system.cpu.dcache.tags.occ_percent::cpu.data 0.020013 # Average percentage of cache occupancy 562system.cpu.dcache.tags.occ_percent::total 0.020013 # Average percentage of cache occupancy | 565system.cpu.dcache.tags.occ_blocks::cpu.data 81.534494 # Average occupied blocks per requestor 566system.cpu.dcache.tags.occ_percent::cpu.data 0.019906 # Average percentage of cache occupancy 567system.cpu.dcache.tags.occ_percent::total 0.019906 # Average percentage of cache occupancy |
| 563system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id | 568system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id |
| 564system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 565system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id | 569system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 570system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id |
| 566system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id | 571system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id |
| 567system.cpu.dcache.tags.tag_accesses 5305 # Number of tag accesses 568system.cpu.dcache.tags.data_accesses 5305 # Number of data accesses 569system.cpu.dcache.ReadReq_hits::cpu.data 1525 # number of ReadReq hits 570system.cpu.dcache.ReadReq_hits::total 1525 # number of ReadReq hits 571system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits 572system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits 573system.cpu.dcache.demand_hits::cpu.data 2383 # number of demand (read+write) hits 574system.cpu.dcache.demand_hits::total 2383 # number of demand (read+write) hits 575system.cpu.dcache.overall_hits::cpu.data 2383 # number of overall hits 576system.cpu.dcache.overall_hits::total 2383 # number of overall hits 577system.cpu.dcache.ReadReq_misses::cpu.data 123 # number of ReadReq misses 578system.cpu.dcache.ReadReq_misses::total 123 # number of ReadReq misses 579system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses 580system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses 581system.cpu.dcache.demand_misses::cpu.data 200 # number of demand (read+write) misses 582system.cpu.dcache.demand_misses::total 200 # number of demand (read+write) misses 583system.cpu.dcache.overall_misses::cpu.data 200 # number of overall misses 584system.cpu.dcache.overall_misses::total 200 # number of overall misses 585system.cpu.dcache.ReadReq_miss_latency::cpu.data 9653500 # number of ReadReq miss cycles 586system.cpu.dcache.ReadReq_miss_latency::total 9653500 # number of ReadReq miss cycles 587system.cpu.dcache.WriteReq_miss_latency::cpu.data 6433000 # number of WriteReq miss cycles 588system.cpu.dcache.WriteReq_miss_latency::total 6433000 # number of WriteReq miss cycles 589system.cpu.dcache.demand_miss_latency::cpu.data 16086500 # number of demand (read+write) miss cycles 590system.cpu.dcache.demand_miss_latency::total 16086500 # number of demand (read+write) miss cycles 591system.cpu.dcache.overall_miss_latency::cpu.data 16086500 # number of overall miss cycles 592system.cpu.dcache.overall_miss_latency::total 16086500 # number of overall miss cycles 593system.cpu.dcache.ReadReq_accesses::cpu.data 1648 # number of ReadReq accesses(hits+misses) 594system.cpu.dcache.ReadReq_accesses::total 1648 # number of ReadReq accesses(hits+misses) | 572system.cpu.dcache.tags.tag_accesses 5685 # Number of tag accesses 573system.cpu.dcache.tags.data_accesses 5685 # Number of data accesses 574system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits 575system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits 576system.cpu.dcache.WriteReq_hits::cpu.data 860 # number of WriteReq hits 577system.cpu.dcache.WriteReq_hits::total 860 # number of WriteReq hits 578system.cpu.dcache.demand_hits::cpu.data 2583 # number of demand (read+write) hits 579system.cpu.dcache.demand_hits::total 2583 # number of demand (read+write) hits 580system.cpu.dcache.overall_hits::cpu.data 2583 # number of overall hits 581system.cpu.dcache.overall_hits::total 2583 # number of overall hits 582system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses 583system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses 584system.cpu.dcache.WriteReq_misses::cpu.data 75 # number of WriteReq misses 585system.cpu.dcache.WriteReq_misses::total 75 # number of WriteReq misses 586system.cpu.dcache.demand_misses::cpu.data 190 # number of demand (read+write) misses 587system.cpu.dcache.demand_misses::total 190 # number of demand (read+write) misses 588system.cpu.dcache.overall_misses::cpu.data 190 # number of overall misses 589system.cpu.dcache.overall_misses::total 190 # number of overall misses 590system.cpu.dcache.ReadReq_miss_latency::cpu.data 9038500 # number of ReadReq miss cycles 591system.cpu.dcache.ReadReq_miss_latency::total 9038500 # number of ReadReq miss cycles 592system.cpu.dcache.WriteReq_miss_latency::cpu.data 6225500 # number of WriteReq miss cycles 593system.cpu.dcache.WriteReq_miss_latency::total 6225500 # number of WriteReq miss cycles 594system.cpu.dcache.demand_miss_latency::cpu.data 15264000 # number of demand (read+write) miss cycles 595system.cpu.dcache.demand_miss_latency::total 15264000 # number of demand (read+write) miss cycles 596system.cpu.dcache.overall_miss_latency::cpu.data 15264000 # number of overall miss cycles 597system.cpu.dcache.overall_miss_latency::total 15264000 # number of overall miss cycles 598system.cpu.dcache.ReadReq_accesses::cpu.data 1838 # number of ReadReq accesses(hits+misses) 599system.cpu.dcache.ReadReq_accesses::total 1838 # number of ReadReq accesses(hits+misses) |
| 595system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 596system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) | 600system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 601system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) |
| 597system.cpu.dcache.demand_accesses::cpu.data 2583 # number of demand (read+write) accesses 598system.cpu.dcache.demand_accesses::total 2583 # number of demand (read+write) accesses 599system.cpu.dcache.overall_accesses::cpu.data 2583 # number of overall (read+write) accesses 600system.cpu.dcache.overall_accesses::total 2583 # number of overall (read+write) accesses 601system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074636 # miss rate for ReadReq accesses 602system.cpu.dcache.ReadReq_miss_rate::total 0.074636 # miss rate for ReadReq accesses 603system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses 604system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses 605system.cpu.dcache.demand_miss_rate::cpu.data 0.077429 # miss rate for demand accesses 606system.cpu.dcache.demand_miss_rate::total 0.077429 # miss rate for demand accesses 607system.cpu.dcache.overall_miss_rate::cpu.data 0.077429 # miss rate for overall accesses 608system.cpu.dcache.overall_miss_rate::total 0.077429 # miss rate for overall accesses 609system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78483.739837 # average ReadReq miss latency 610system.cpu.dcache.ReadReq_avg_miss_latency::total 78483.739837 # average ReadReq miss latency 611system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83545.454545 # average WriteReq miss latency 612system.cpu.dcache.WriteReq_avg_miss_latency::total 83545.454545 # average WriteReq miss latency 613system.cpu.dcache.demand_avg_miss_latency::cpu.data 80432.500000 # average overall miss latency 614system.cpu.dcache.demand_avg_miss_latency::total 80432.500000 # average overall miss latency 615system.cpu.dcache.overall_avg_miss_latency::cpu.data 80432.500000 # average overall miss latency 616system.cpu.dcache.overall_avg_miss_latency::total 80432.500000 # average overall miss latency 617system.cpu.dcache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked | 602system.cpu.dcache.demand_accesses::cpu.data 2773 # number of demand (read+write) accesses 603system.cpu.dcache.demand_accesses::total 2773 # number of demand (read+write) accesses 604system.cpu.dcache.overall_accesses::cpu.data 2773 # number of overall (read+write) accesses 605system.cpu.dcache.overall_accesses::total 2773 # number of overall (read+write) accesses 606system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062568 # miss rate for ReadReq accesses 607system.cpu.dcache.ReadReq_miss_rate::total 0.062568 # miss rate for ReadReq accesses 608system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080214 # miss rate for WriteReq accesses 609system.cpu.dcache.WriteReq_miss_rate::total 0.080214 # miss rate for WriteReq accesses 610system.cpu.dcache.demand_miss_rate::cpu.data 0.068518 # miss rate for demand accesses 611system.cpu.dcache.demand_miss_rate::total 0.068518 # miss rate for demand accesses 612system.cpu.dcache.overall_miss_rate::cpu.data 0.068518 # miss rate for overall accesses 613system.cpu.dcache.overall_miss_rate::total 0.068518 # miss rate for overall accesses 614system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78595.652174 # average ReadReq miss latency 615system.cpu.dcache.ReadReq_avg_miss_latency::total 78595.652174 # average ReadReq miss latency 616system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83006.666667 # average WriteReq miss latency 617system.cpu.dcache.WriteReq_avg_miss_latency::total 83006.666667 # average WriteReq miss latency 618system.cpu.dcache.demand_avg_miss_latency::cpu.data 80336.842105 # average overall miss latency 619system.cpu.dcache.demand_avg_miss_latency::total 80336.842105 # average overall miss latency 620system.cpu.dcache.overall_avg_miss_latency::cpu.data 80336.842105 # average overall miss latency 621system.cpu.dcache.overall_avg_miss_latency::total 80336.842105 # average overall miss latency 622system.cpu.dcache.blocked_cycles::no_mshrs 122 # number of cycles access was blocked |
| 618system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 623system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 619system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked | 624system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked |
| 620system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 625system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 621system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.250000 # average number of cycles each access was blocked | 626system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.666667 # average number of cycles each access was blocked |
| 622system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 623system.cpu.dcache.fast_writes 0 # number of fast writes performed 624system.cpu.dcache.cache_copies 0 # number of cache copies performed | 627system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 628system.cpu.dcache.fast_writes 0 # number of fast writes performed 629system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 625system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits 626system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits 627system.cpu.dcache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits 628system.cpu.dcache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits 629system.cpu.dcache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits 630system.cpu.dcache.overall_mshr_hits::total 61 # number of overall MSHR hits 631system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses 632system.cpu.dcache.ReadReq_mshr_misses::total 62 # number of ReadReq MSHR misses 633system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses 634system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses | 630system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits 631system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits 632system.cpu.dcache.demand_mshr_hits::cpu.data 51 # number of demand (read+write) MSHR hits 633system.cpu.dcache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits 634system.cpu.dcache.overall_mshr_hits::cpu.data 51 # number of overall MSHR hits 635system.cpu.dcache.overall_mshr_hits::total 51 # number of overall MSHR hits 636system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 637system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses 638system.cpu.dcache.WriteReq_mshr_misses::cpu.data 75 # number of WriteReq MSHR misses 639system.cpu.dcache.WriteReq_mshr_misses::total 75 # number of WriteReq MSHR misses |
| 635system.cpu.dcache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses 636system.cpu.dcache.demand_mshr_misses::total 139 # number of demand (read+write) MSHR misses 637system.cpu.dcache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses 638system.cpu.dcache.overall_mshr_misses::total 139 # number of overall MSHR misses | 640system.cpu.dcache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses 641system.cpu.dcache.demand_mshr_misses::total 139 # number of demand (read+write) MSHR misses 642system.cpu.dcache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses 643system.cpu.dcache.overall_mshr_misses::total 139 # number of overall MSHR misses |
| 639system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5286500 # number of ReadReq MSHR miss cycles 640system.cpu.dcache.ReadReq_mshr_miss_latency::total 5286500 # number of ReadReq MSHR miss cycles 641system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6356000 # number of WriteReq MSHR miss cycles 642system.cpu.dcache.WriteReq_mshr_miss_latency::total 6356000 # number of WriteReq MSHR miss cycles 643system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11642500 # number of demand (read+write) MSHR miss cycles 644system.cpu.dcache.demand_mshr_miss_latency::total 11642500 # number of demand (read+write) MSHR miss cycles 645system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11642500 # number of overall MSHR miss cycles 646system.cpu.dcache.overall_mshr_miss_latency::total 11642500 # number of overall MSHR miss cycles 647system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.037621 # mshr miss rate for ReadReq accesses 648system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.037621 # mshr miss rate for ReadReq accesses 649system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses 650system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses 651system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.053813 # mshr miss rate for demand accesses 652system.cpu.dcache.demand_mshr_miss_rate::total 0.053813 # mshr miss rate for demand accesses 653system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.053813 # mshr miss rate for overall accesses 654system.cpu.dcache.overall_mshr_miss_rate::total 0.053813 # mshr miss rate for overall accesses 655system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85266.129032 # average ReadReq mshr miss latency 656system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85266.129032 # average ReadReq mshr miss latency 657system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82545.454545 # average WriteReq mshr miss latency 658system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82545.454545 # average WriteReq mshr miss latency 659system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83758.992806 # average overall mshr miss latency 660system.cpu.dcache.demand_avg_mshr_miss_latency::total 83758.992806 # average overall mshr miss latency 661system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83758.992806 # average overall mshr miss latency 662system.cpu.dcache.overall_avg_mshr_miss_latency::total 83758.992806 # average overall mshr miss latency | 644system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5459500 # number of ReadReq MSHR miss cycles 645system.cpu.dcache.ReadReq_mshr_miss_latency::total 5459500 # number of ReadReq MSHR miss cycles 646system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6150500 # number of WriteReq MSHR miss cycles 647system.cpu.dcache.WriteReq_mshr_miss_latency::total 6150500 # number of WriteReq MSHR miss cycles 648system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11610000 # number of demand (read+write) MSHR miss cycles 649system.cpu.dcache.demand_mshr_miss_latency::total 11610000 # number of demand (read+write) MSHR miss cycles 650system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11610000 # number of overall MSHR miss cycles 651system.cpu.dcache.overall_mshr_miss_latency::total 11610000 # number of overall MSHR miss cycles 652system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034820 # mshr miss rate for ReadReq accesses 653system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034820 # mshr miss rate for ReadReq accesses 654system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.080214 # mshr miss rate for WriteReq accesses 655system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.080214 # mshr miss rate for WriteReq accesses 656system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050126 # mshr miss rate for demand accesses 657system.cpu.dcache.demand_mshr_miss_rate::total 0.050126 # mshr miss rate for demand accesses 658system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050126 # mshr miss rate for overall accesses 659system.cpu.dcache.overall_mshr_miss_rate::total 0.050126 # mshr miss rate for overall accesses 660system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85304.687500 # average ReadReq mshr miss latency 661system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85304.687500 # average ReadReq mshr miss latency 662system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82006.666667 # average WriteReq mshr miss latency 663system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82006.666667 # average WriteReq mshr miss latency 664system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency 665system.cpu.dcache.demand_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency 666system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency 667system.cpu.dcache.overall_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency |
| 663system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 664system.cpu.icache.tags.replacements 0 # number of replacements | 668system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 669system.cpu.icache.tags.replacements 0 # number of replacements |
| 665system.cpu.icache.tags.tagsinuse 130.304167 # Cycle average of tags in use 666system.cpu.icache.tags.total_refs 1706 # Total number of references to valid blocks. 667system.cpu.icache.tags.sampled_refs 277 # Sample count of references to valid blocks. 668system.cpu.icache.tags.avg_refs 6.158845 # Average number of references to valid blocks. | 670system.cpu.icache.tags.tagsinuse 130.801873 # Cycle average of tags in use 671system.cpu.icache.tags.total_refs 1651 # Total number of references to valid blocks. 672system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. 673system.cpu.icache.tags.avg_refs 5.938849 # Average number of references to valid blocks. |
| 669system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 674system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 670system.cpu.icache.tags.occ_blocks::cpu.inst 130.304167 # Average occupied blocks per requestor 671system.cpu.icache.tags.occ_percent::cpu.inst 0.063625 # Average percentage of cache occupancy 672system.cpu.icache.tags.occ_percent::total 0.063625 # Average percentage of cache occupancy 673system.cpu.icache.tags.occ_task_id_blocks::1024 277 # Occupied blocks per task id 674system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id 675system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id 676system.cpu.icache.tags.occ_task_id_percent::1024 0.135254 # Percentage of cache occupancy per task id 677system.cpu.icache.tags.tag_accesses 4427 # Number of tag accesses 678system.cpu.icache.tags.data_accesses 4427 # Number of data accesses 679system.cpu.icache.ReadReq_hits::cpu.inst 1706 # number of ReadReq hits 680system.cpu.icache.ReadReq_hits::total 1706 # number of ReadReq hits 681system.cpu.icache.demand_hits::cpu.inst 1706 # number of demand (read+write) hits 682system.cpu.icache.demand_hits::total 1706 # number of demand (read+write) hits 683system.cpu.icache.overall_hits::cpu.inst 1706 # number of overall hits 684system.cpu.icache.overall_hits::total 1706 # number of overall hits 685system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses 686system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses 687system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses 688system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses 689system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses 690system.cpu.icache.overall_misses::total 369 # number of overall misses 691system.cpu.icache.ReadReq_miss_latency::cpu.inst 28132500 # number of ReadReq miss cycles 692system.cpu.icache.ReadReq_miss_latency::total 28132500 # number of ReadReq miss cycles 693system.cpu.icache.demand_miss_latency::cpu.inst 28132500 # number of demand (read+write) miss cycles 694system.cpu.icache.demand_miss_latency::total 28132500 # number of demand (read+write) miss cycles 695system.cpu.icache.overall_miss_latency::cpu.inst 28132500 # number of overall miss cycles 696system.cpu.icache.overall_miss_latency::total 28132500 # number of overall miss cycles 697system.cpu.icache.ReadReq_accesses::cpu.inst 2075 # number of ReadReq accesses(hits+misses) 698system.cpu.icache.ReadReq_accesses::total 2075 # number of ReadReq accesses(hits+misses) 699system.cpu.icache.demand_accesses::cpu.inst 2075 # number of demand (read+write) accesses 700system.cpu.icache.demand_accesses::total 2075 # number of demand (read+write) accesses 701system.cpu.icache.overall_accesses::cpu.inst 2075 # number of overall (read+write) accesses 702system.cpu.icache.overall_accesses::total 2075 # number of overall (read+write) accesses 703system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.177831 # miss rate for ReadReq accesses 704system.cpu.icache.ReadReq_miss_rate::total 0.177831 # miss rate for ReadReq accesses 705system.cpu.icache.demand_miss_rate::cpu.inst 0.177831 # miss rate for demand accesses 706system.cpu.icache.demand_miss_rate::total 0.177831 # miss rate for demand accesses 707system.cpu.icache.overall_miss_rate::cpu.inst 0.177831 # miss rate for overall accesses 708system.cpu.icache.overall_miss_rate::total 0.177831 # miss rate for overall accesses 709system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76239.837398 # average ReadReq miss latency 710system.cpu.icache.ReadReq_avg_miss_latency::total 76239.837398 # average ReadReq miss latency 711system.cpu.icache.demand_avg_miss_latency::cpu.inst 76239.837398 # average overall miss latency 712system.cpu.icache.demand_avg_miss_latency::total 76239.837398 # average overall miss latency 713system.cpu.icache.overall_avg_miss_latency::cpu.inst 76239.837398 # average overall miss latency 714system.cpu.icache.overall_avg_miss_latency::total 76239.837398 # average overall miss latency 715system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 675system.cpu.icache.tags.occ_blocks::cpu.inst 130.801873 # Average occupied blocks per requestor 676system.cpu.icache.tags.occ_percent::cpu.inst 0.063868 # Average percentage of cache occupancy 677system.cpu.icache.tags.occ_percent::total 0.063868 # Average percentage of cache occupancy 678system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id 679system.cpu.icache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id 680system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 681system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id 682system.cpu.icache.tags.tag_accesses 4350 # Number of tag accesses 683system.cpu.icache.tags.data_accesses 4350 # Number of data accesses 684system.cpu.icache.ReadReq_hits::cpu.inst 1651 # number of ReadReq hits 685system.cpu.icache.ReadReq_hits::total 1651 # number of ReadReq hits 686system.cpu.icache.demand_hits::cpu.inst 1651 # number of demand (read+write) hits 687system.cpu.icache.demand_hits::total 1651 # number of demand (read+write) hits 688system.cpu.icache.overall_hits::cpu.inst 1651 # number of overall hits 689system.cpu.icache.overall_hits::total 1651 # number of overall hits 690system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses 691system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses 692system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses 693system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses 694system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses 695system.cpu.icache.overall_misses::total 385 # number of overall misses 696system.cpu.icache.ReadReq_miss_latency::cpu.inst 28516500 # number of ReadReq miss cycles 697system.cpu.icache.ReadReq_miss_latency::total 28516500 # number of ReadReq miss cycles 698system.cpu.icache.demand_miss_latency::cpu.inst 28516500 # number of demand (read+write) miss cycles 699system.cpu.icache.demand_miss_latency::total 28516500 # number of demand (read+write) miss cycles 700system.cpu.icache.overall_miss_latency::cpu.inst 28516500 # number of overall miss cycles 701system.cpu.icache.overall_miss_latency::total 28516500 # number of overall miss cycles 702system.cpu.icache.ReadReq_accesses::cpu.inst 2036 # number of ReadReq accesses(hits+misses) 703system.cpu.icache.ReadReq_accesses::total 2036 # number of ReadReq accesses(hits+misses) 704system.cpu.icache.demand_accesses::cpu.inst 2036 # number of demand (read+write) accesses 705system.cpu.icache.demand_accesses::total 2036 # number of demand (read+write) accesses 706system.cpu.icache.overall_accesses::cpu.inst 2036 # number of overall (read+write) accesses 707system.cpu.icache.overall_accesses::total 2036 # number of overall (read+write) accesses 708system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.189096 # miss rate for ReadReq accesses 709system.cpu.icache.ReadReq_miss_rate::total 0.189096 # miss rate for ReadReq accesses 710system.cpu.icache.demand_miss_rate::cpu.inst 0.189096 # miss rate for demand accesses 711system.cpu.icache.demand_miss_rate::total 0.189096 # miss rate for demand accesses 712system.cpu.icache.overall_miss_rate::cpu.inst 0.189096 # miss rate for overall accesses 713system.cpu.icache.overall_miss_rate::total 0.189096 # miss rate for overall accesses 714system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74068.831169 # average ReadReq miss latency 715system.cpu.icache.ReadReq_avg_miss_latency::total 74068.831169 # average ReadReq miss latency 716system.cpu.icache.demand_avg_miss_latency::cpu.inst 74068.831169 # average overall miss latency 717system.cpu.icache.demand_avg_miss_latency::total 74068.831169 # average overall miss latency 718system.cpu.icache.overall_avg_miss_latency::cpu.inst 74068.831169 # average overall miss latency 719system.cpu.icache.overall_avg_miss_latency::total 74068.831169 # average overall miss latency 720system.cpu.icache.blocked_cycles::no_mshrs 142 # number of cycles access was blocked |
| 716system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 721system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 717system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked | 722system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked |
| 718system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 723system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 719system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 724system.cpu.icache.avg_blocked_cycles::no_mshrs 47.333333 # average number of cycles each access was blocked |
| 720system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 721system.cpu.icache.fast_writes 0 # number of fast writes performed 722system.cpu.icache.cache_copies 0 # number of cache copies performed | 725system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 726system.cpu.icache.fast_writes 0 # number of fast writes performed 727system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 723system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits 724system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits 725system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits 726system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits 727system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits 728system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits 729system.cpu.icache.ReadReq_mshr_misses::cpu.inst 277 # number of ReadReq MSHR misses 730system.cpu.icache.ReadReq_mshr_misses::total 277 # number of ReadReq MSHR misses 731system.cpu.icache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses 732system.cpu.icache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses 733system.cpu.icache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses 734system.cpu.icache.overall_mshr_misses::total 277 # number of overall MSHR misses 735system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22319000 # number of ReadReq MSHR miss cycles 736system.cpu.icache.ReadReq_mshr_miss_latency::total 22319000 # number of ReadReq MSHR miss cycles 737system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22319000 # number of demand (read+write) MSHR miss cycles 738system.cpu.icache.demand_mshr_miss_latency::total 22319000 # number of demand (read+write) MSHR miss cycles 739system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22319000 # number of overall MSHR miss cycles 740system.cpu.icache.overall_mshr_miss_latency::total 22319000 # number of overall MSHR miss cycles 741system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for ReadReq accesses 742system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133494 # mshr miss rate for ReadReq accesses 743system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for demand accesses 744system.cpu.icache.demand_mshr_miss_rate::total 0.133494 # mshr miss rate for demand accesses 745system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for overall accesses 746system.cpu.icache.overall_mshr_miss_rate::total 0.133494 # mshr miss rate for overall accesses 747system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80574.007220 # average ReadReq mshr miss latency 748system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80574.007220 # average ReadReq mshr miss latency 749system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80574.007220 # average overall mshr miss latency 750system.cpu.icache.demand_avg_mshr_miss_latency::total 80574.007220 # average overall mshr miss latency 751system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80574.007220 # average overall mshr miss latency 752system.cpu.icache.overall_avg_mshr_miss_latency::total 80574.007220 # average overall mshr miss latency | 728system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # number of ReadReq MSHR hits 729system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits 730system.cpu.icache.demand_mshr_hits::cpu.inst 107 # number of demand (read+write) MSHR hits 731system.cpu.icache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits 732system.cpu.icache.overall_mshr_hits::cpu.inst 107 # number of overall MSHR hits 733system.cpu.icache.overall_mshr_hits::total 107 # number of overall MSHR hits 734system.cpu.icache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 735system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses 736system.cpu.icache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 737system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses 738system.cpu.icache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 739system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses 740system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21868500 # number of ReadReq MSHR miss cycles 741system.cpu.icache.ReadReq_mshr_miss_latency::total 21868500 # number of ReadReq MSHR miss cycles 742system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21868500 # number of demand (read+write) MSHR miss cycles 743system.cpu.icache.demand_mshr_miss_latency::total 21868500 # number of demand (read+write) MSHR miss cycles 744system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21868500 # number of overall MSHR miss cycles 745system.cpu.icache.overall_mshr_miss_latency::total 21868500 # number of overall MSHR miss cycles 746system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for ReadReq accesses 747system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136542 # mshr miss rate for ReadReq accesses 748system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for demand accesses 749system.cpu.icache.demand_mshr_miss_rate::total 0.136542 # mshr miss rate for demand accesses 750system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for overall accesses 751system.cpu.icache.overall_mshr_miss_rate::total 0.136542 # mshr miss rate for overall accesses 752system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78663.669065 # average ReadReq mshr miss latency 753system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78663.669065 # average ReadReq mshr miss latency 754system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency 755system.cpu.icache.demand_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency 756system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency 757system.cpu.icache.overall_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency |
| 753system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 754system.cpu.l2cache.tags.replacements 0 # number of replacements | 758system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 759system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 755system.cpu.l2cache.tags.tagsinuse 162.380689 # Cycle average of tags in use | 760system.cpu.l2cache.tags.tagsinuse 163.058861 # Cycle average of tags in use |
| 756system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. | 761system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. |
| 757system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. 758system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. | 762system.cpu.l2cache.tags.sampled_refs 341 # Sample count of references to valid blocks. 763system.cpu.l2cache.tags.avg_refs 0.002933 # Average number of references to valid blocks. |
| 759system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 764system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 760system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.343988 # Average occupied blocks per requestor 761system.cpu.l2cache.tags.occ_blocks::cpu.data 32.036700 # Average occupied blocks per requestor 762system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003978 # Average percentage of cache occupancy 763system.cpu.l2cache.tags.occ_percent::cpu.data 0.000978 # Average percentage of cache occupancy 764system.cpu.l2cache.tags.occ_percent::total 0.004955 # Average percentage of cache occupancy 765system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id | 765system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.841735 # Average occupied blocks per requestor 766system.cpu.l2cache.tags.occ_blocks::cpu.data 32.217126 # Average occupied blocks per requestor 767system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003993 # Average percentage of cache occupancy 768system.cpu.l2cache.tags.occ_percent::cpu.data 0.000983 # Average percentage of cache occupancy 769system.cpu.l2cache.tags.occ_percent::total 0.004976 # Average percentage of cache occupancy 770system.cpu.l2cache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id |
| 766system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id | 771system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id |
| 767system.cpu.l2cache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id 768system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010315 # Percentage of cache occupancy per task id 769system.cpu.l2cache.tags.tag_accesses 3743 # Number of tag accesses 770system.cpu.l2cache.tags.data_accesses 3743 # Number of data accesses | 772system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 773system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010406 # Percentage of cache occupancy per task id 774system.cpu.l2cache.tags.tag_accesses 3752 # Number of tag accesses 775system.cpu.l2cache.tags.data_accesses 3752 # Number of data accesses |
| 771system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 772system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 773system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 774system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 775system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 776system.cpu.l2cache.overall_hits::total 1 # number of overall hits | 776system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 777system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 778system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 779system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 780system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 781system.cpu.l2cache.overall_hits::total 1 # number of overall hits |
| 777system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses 778system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses 779system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 276 # number of ReadCleanReq misses 780system.cpu.l2cache.ReadCleanReq_misses::total 276 # number of ReadCleanReq misses 781system.cpu.l2cache.ReadSharedReq_misses::cpu.data 62 # number of ReadSharedReq misses 782system.cpu.l2cache.ReadSharedReq_misses::total 62 # number of ReadSharedReq misses 783system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses | 782system.cpu.l2cache.ReadExReq_misses::cpu.data 75 # number of ReadExReq misses 783system.cpu.l2cache.ReadExReq_misses::total 75 # number of ReadExReq misses 784system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 277 # number of ReadCleanReq misses 785system.cpu.l2cache.ReadCleanReq_misses::total 277 # number of ReadCleanReq misses 786system.cpu.l2cache.ReadSharedReq_misses::cpu.data 64 # number of ReadSharedReq misses 787system.cpu.l2cache.ReadSharedReq_misses::total 64 # number of ReadSharedReq misses 788system.cpu.l2cache.demand_misses::cpu.inst 277 # number of demand (read+write) misses |
| 784system.cpu.l2cache.demand_misses::cpu.data 139 # number of demand (read+write) misses | 789system.cpu.l2cache.demand_misses::cpu.data 139 # number of demand (read+write) misses |
| 785system.cpu.l2cache.demand_misses::total 415 # number of demand (read+write) misses 786system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses | 790system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses 791system.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses |
| 787system.cpu.l2cache.overall_misses::cpu.data 139 # number of overall misses | 792system.cpu.l2cache.overall_misses::cpu.data 139 # number of overall misses |
| 788system.cpu.l2cache.overall_misses::total 415 # number of overall misses 789system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6240500 # number of ReadExReq miss cycles 790system.cpu.l2cache.ReadExReq_miss_latency::total 6240500 # number of ReadExReq miss cycles 791system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21891500 # number of ReadCleanReq miss cycles 792system.cpu.l2cache.ReadCleanReq_miss_latency::total 21891500 # number of ReadCleanReq miss cycles 793system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5193000 # number of ReadSharedReq miss cycles 794system.cpu.l2cache.ReadSharedReq_miss_latency::total 5193000 # number of ReadSharedReq miss cycles 795system.cpu.l2cache.demand_miss_latency::cpu.inst 21891500 # number of demand (read+write) miss cycles 796system.cpu.l2cache.demand_miss_latency::cpu.data 11433500 # number of demand (read+write) miss cycles 797system.cpu.l2cache.demand_miss_latency::total 33325000 # number of demand (read+write) miss cycles 798system.cpu.l2cache.overall_miss_latency::cpu.inst 21891500 # number of overall miss cycles 799system.cpu.l2cache.overall_miss_latency::cpu.data 11433500 # number of overall miss cycles 800system.cpu.l2cache.overall_miss_latency::total 33325000 # number of overall miss cycles 801system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses) 802system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses) 803system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 277 # number of ReadCleanReq accesses(hits+misses) 804system.cpu.l2cache.ReadCleanReq_accesses::total 277 # number of ReadCleanReq accesses(hits+misses) 805system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 62 # number of ReadSharedReq accesses(hits+misses) 806system.cpu.l2cache.ReadSharedReq_accesses::total 62 # number of ReadSharedReq accesses(hits+misses) 807system.cpu.l2cache.demand_accesses::cpu.inst 277 # number of demand (read+write) accesses | 793system.cpu.l2cache.overall_misses::total 416 # number of overall misses 794system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6037500 # number of ReadExReq miss cycles 795system.cpu.l2cache.ReadExReq_miss_latency::total 6037500 # number of ReadExReq miss cycles 796system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21439500 # number of ReadCleanReq miss cycles 797system.cpu.l2cache.ReadCleanReq_miss_latency::total 21439500 # number of ReadCleanReq miss cycles 798system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5362500 # number of ReadSharedReq miss cycles 799system.cpu.l2cache.ReadSharedReq_miss_latency::total 5362500 # number of ReadSharedReq miss cycles 800system.cpu.l2cache.demand_miss_latency::cpu.inst 21439500 # number of demand (read+write) miss cycles 801system.cpu.l2cache.demand_miss_latency::cpu.data 11400000 # number of demand (read+write) miss cycles 802system.cpu.l2cache.demand_miss_latency::total 32839500 # number of demand (read+write) miss cycles 803system.cpu.l2cache.overall_miss_latency::cpu.inst 21439500 # number of overall miss cycles 804system.cpu.l2cache.overall_miss_latency::cpu.data 11400000 # number of overall miss cycles 805system.cpu.l2cache.overall_miss_latency::total 32839500 # number of overall miss cycles 806system.cpu.l2cache.ReadExReq_accesses::cpu.data 75 # number of ReadExReq accesses(hits+misses) 807system.cpu.l2cache.ReadExReq_accesses::total 75 # number of ReadExReq accesses(hits+misses) 808system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 278 # number of ReadCleanReq accesses(hits+misses) 809system.cpu.l2cache.ReadCleanReq_accesses::total 278 # number of ReadCleanReq accesses(hits+misses) 810system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64 # number of ReadSharedReq accesses(hits+misses) 811system.cpu.l2cache.ReadSharedReq_accesses::total 64 # number of ReadSharedReq accesses(hits+misses) 812system.cpu.l2cache.demand_accesses::cpu.inst 278 # number of demand (read+write) accesses |
| 808system.cpu.l2cache.demand_accesses::cpu.data 139 # number of demand (read+write) accesses | 813system.cpu.l2cache.demand_accesses::cpu.data 139 # number of demand (read+write) accesses |
| 809system.cpu.l2cache.demand_accesses::total 416 # number of demand (read+write) accesses 810system.cpu.l2cache.overall_accesses::cpu.inst 277 # number of overall (read+write) accesses | 814system.cpu.l2cache.demand_accesses::total 417 # number of demand (read+write) accesses 815system.cpu.l2cache.overall_accesses::cpu.inst 278 # number of overall (read+write) accesses |
| 811system.cpu.l2cache.overall_accesses::cpu.data 139 # number of overall (read+write) accesses | 816system.cpu.l2cache.overall_accesses::cpu.data 139 # number of overall (read+write) accesses |
| 812system.cpu.l2cache.overall_accesses::total 416 # number of overall (read+write) accesses | 817system.cpu.l2cache.overall_accesses::total 417 # number of overall (read+write) accesses |
| 813system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 814system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 818system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 819system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 815system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996390 # miss rate for ReadCleanReq accesses 816system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996390 # miss rate for ReadCleanReq accesses | 820system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996403 # miss rate for ReadCleanReq accesses 821system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996403 # miss rate for ReadCleanReq accesses |
| 817system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 818system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses | 822system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 823system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses |
| 819system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996390 # miss rate for demand accesses | 824system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996403 # miss rate for demand accesses |
| 820system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses | 825system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
| 821system.cpu.l2cache.demand_miss_rate::total 0.997596 # miss rate for demand accesses 822system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996390 # miss rate for overall accesses | 826system.cpu.l2cache.demand_miss_rate::total 0.997602 # miss rate for demand accesses 827system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996403 # miss rate for overall accesses |
| 823system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses | 828system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
| 824system.cpu.l2cache.overall_miss_rate::total 0.997596 # miss rate for overall accesses 825system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81045.454545 # average ReadExReq miss latency 826system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81045.454545 # average ReadExReq miss latency 827system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79317.028986 # average ReadCleanReq miss latency 828system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79317.028986 # average ReadCleanReq miss latency 829system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83758.064516 # average ReadSharedReq miss latency 830system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83758.064516 # average ReadSharedReq miss latency 831system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79317.028986 # average overall miss latency 832system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82255.395683 # average overall miss latency 833system.cpu.l2cache.demand_avg_miss_latency::total 80301.204819 # average overall miss latency 834system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79317.028986 # average overall miss latency 835system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82255.395683 # average overall miss latency 836system.cpu.l2cache.overall_avg_miss_latency::total 80301.204819 # average overall miss latency | 829system.cpu.l2cache.overall_miss_rate::total 0.997602 # miss rate for overall accesses 830system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80500 # average ReadExReq miss latency 831system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80500 # average ReadExReq miss latency 832system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77398.916968 # average ReadCleanReq miss latency 833system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77398.916968 # average ReadCleanReq miss latency 834system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83789.062500 # average ReadSharedReq miss latency 835system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83789.062500 # average ReadSharedReq miss latency 836system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77398.916968 # average overall miss latency 837system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82014.388489 # average overall miss latency 838system.cpu.l2cache.demand_avg_miss_latency::total 78941.105769 # average overall miss latency 839system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77398.916968 # average overall miss latency 840system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82014.388489 # average overall miss latency 841system.cpu.l2cache.overall_avg_miss_latency::total 78941.105769 # average overall miss latency |
| 837system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 838system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 839system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 840system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 841system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 842system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 843system.cpu.l2cache.fast_writes 0 # number of fast writes performed 844system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 842system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 843system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 844system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 845system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 846system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 847system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 848system.cpu.l2cache.fast_writes 0 # number of fast writes performed 849system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 845system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses 846system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses 847system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 276 # number of ReadCleanReq MSHR misses 848system.cpu.l2cache.ReadCleanReq_mshr_misses::total 276 # number of ReadCleanReq MSHR misses 849system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 62 # number of ReadSharedReq MSHR misses 850system.cpu.l2cache.ReadSharedReq_mshr_misses::total 62 # number of ReadSharedReq MSHR misses 851system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses | 850system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 75 # number of ReadExReq MSHR misses 851system.cpu.l2cache.ReadExReq_mshr_misses::total 75 # number of ReadExReq MSHR misses 852system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses 853system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses 854system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses 855system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses 856system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses |
| 852system.cpu.l2cache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses | 857system.cpu.l2cache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses |
| 853system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses 854system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses | 858system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses 859system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses |
| 855system.cpu.l2cache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses | 860system.cpu.l2cache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses |
| 856system.cpu.l2cache.overall_mshr_misses::total 415 # number of overall MSHR misses 857system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5470500 # number of ReadExReq MSHR miss cycles 858system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5470500 # number of ReadExReq MSHR miss cycles 859system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19131500 # number of ReadCleanReq MSHR miss cycles 860system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19131500 # number of ReadCleanReq MSHR miss cycles 861system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4573000 # number of ReadSharedReq MSHR miss cycles 862system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4573000 # number of ReadSharedReq MSHR miss cycles 863system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19131500 # number of demand (read+write) MSHR miss cycles 864system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10043500 # number of demand (read+write) MSHR miss cycles 865system.cpu.l2cache.demand_mshr_miss_latency::total 29175000 # number of demand (read+write) MSHR miss cycles 866system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19131500 # number of overall MSHR miss cycles 867system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10043500 # number of overall MSHR miss cycles 868system.cpu.l2cache.overall_mshr_miss_latency::total 29175000 # number of overall MSHR miss cycles | 861system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses 862system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5287500 # number of ReadExReq MSHR miss cycles 863system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5287500 # number of ReadExReq MSHR miss cycles 864system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18669500 # number of ReadCleanReq MSHR miss cycles 865system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18669500 # number of ReadCleanReq MSHR miss cycles 866system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4722500 # number of ReadSharedReq MSHR miss cycles 867system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4722500 # number of ReadSharedReq MSHR miss cycles 868system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18669500 # number of demand (read+write) MSHR miss cycles 869system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10010000 # number of demand (read+write) MSHR miss cycles 870system.cpu.l2cache.demand_mshr_miss_latency::total 28679500 # number of demand (read+write) MSHR miss cycles 871system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18669500 # number of overall MSHR miss cycles 872system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10010000 # number of overall MSHR miss cycles 873system.cpu.l2cache.overall_mshr_miss_latency::total 28679500 # number of overall MSHR miss cycles |
| 869system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 870system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 874system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 875system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 871system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for ReadCleanReq accesses 872system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996390 # mshr miss rate for ReadCleanReq accesses | 876system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses 877system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996403 # mshr miss rate for ReadCleanReq accesses |
| 873system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 874system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses | 878system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 879system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses |
| 875system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for demand accesses | 880system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses |
| 876system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses | 881system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
| 877system.cpu.l2cache.demand_mshr_miss_rate::total 0.997596 # mshr miss rate for demand accesses 878system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for overall accesses | 882system.cpu.l2cache.demand_mshr_miss_rate::total 0.997602 # mshr miss rate for demand accesses 883system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses |
| 879system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses | 884system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
| 880system.cpu.l2cache.overall_mshr_miss_rate::total 0.997596 # mshr miss rate for overall accesses 881system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71045.454545 # average ReadExReq mshr miss latency 882system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71045.454545 # average ReadExReq mshr miss latency 883system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69317.028986 # average ReadCleanReq mshr miss latency 884system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69317.028986 # average ReadCleanReq mshr miss latency 885system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73758.064516 # average ReadSharedReq mshr miss latency 886system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73758.064516 # average ReadSharedReq mshr miss latency 887system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69317.028986 # average overall mshr miss latency 888system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency 889system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency 890system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69317.028986 # average overall mshr miss latency 891system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency 892system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency | 885system.cpu.l2cache.overall_mshr_miss_rate::total 0.997602 # mshr miss rate for overall accesses 886system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70500 # average ReadExReq mshr miss latency 887system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70500 # average ReadExReq mshr miss latency 888system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67398.916968 # average ReadCleanReq mshr miss latency 889system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67398.916968 # average ReadCleanReq mshr miss latency 890system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73789.062500 # average ReadSharedReq mshr miss latency 891system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73789.062500 # average ReadSharedReq mshr miss latency 892system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency 893system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency 894system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency 895system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency 896system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency 897system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency |
| 893system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 898system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 894system.cpu.toL2Bus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter. | 899system.cpu.toL2Bus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. |
| 895system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 896system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 897system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 898system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 899system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 900system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 901system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 902system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 903system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 904system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 900system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 901system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution 902system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution 903system.cpu.toL2Bus.trans_dist::ReadCleanReq 277 # Transaction distribution 904system.cpu.toL2Bus.trans_dist::ReadSharedReq 62 # Transaction distribution 905system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 554 # Packet count per connected master and slave (bytes) | 905system.cpu.toL2Bus.trans_dist::ReadResp 342 # Transaction distribution 906system.cpu.toL2Bus.trans_dist::ReadExReq 75 # Transaction distribution 907system.cpu.toL2Bus.trans_dist::ReadExResp 75 # Transaction distribution 908system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution 909system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution 910system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes) |
| 906system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes) | 911system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes) |
| 907system.cpu.toL2Bus.pkt_count::total 832 # Packet count per connected master and slave (bytes) 908system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17728 # Cumulative packet size per connected master and slave (bytes) | 912system.cpu.toL2Bus.pkt_count::total 834 # Packet count per connected master and slave (bytes) 913system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes) |
| 909system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8896 # Cumulative packet size per connected master and slave (bytes) | 914system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8896 # Cumulative packet size per connected master and slave (bytes) |
| 910system.cpu.toL2Bus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) | 915system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) |
| 911system.cpu.toL2Bus.snoops 0 # Total snoops (count) | 916system.cpu.toL2Bus.snoops 0 # Total snoops (count) |
| 912system.cpu.toL2Bus.snoop_fanout::samples 416 # Request fanout histogram 913system.cpu.toL2Bus.snoop_fanout::mean 0.002404 # Request fanout histogram 914system.cpu.toL2Bus.snoop_fanout::stdev 0.049029 # Request fanout histogram | 917system.cpu.toL2Bus.snoop_fanout::samples 417 # Request fanout histogram 918system.cpu.toL2Bus.snoop_fanout::mean 0.002398 # Request fanout histogram 919system.cpu.toL2Bus.snoop_fanout::stdev 0.048970 # Request fanout histogram |
| 915system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 920system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 916system.cpu.toL2Bus.snoop_fanout::0 415 99.76% 99.76% # Request fanout histogram | 921system.cpu.toL2Bus.snoop_fanout::0 416 99.76% 99.76% # Request fanout histogram |
| 917system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram 918system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 919system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 920system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 921system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 922system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram 923system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 924system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 925system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 926system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 922system.cpu.toL2Bus.snoop_fanout::total 416 # Request fanout histogram 923system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks) | 927system.cpu.toL2Bus.snoop_fanout::total 417 # Request fanout histogram 928system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) |
| 924system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) | 929system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) |
| 925system.cpu.toL2Bus.respLayer0.occupancy 415500 # Layer occupancy (ticks) | 930system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks) |
| 926system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 927system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks) 928system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) | 931system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 932system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks) 933system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) |
| 929system.membus.trans_dist::ReadResp 338 # Transaction distribution 930system.membus.trans_dist::ReadExReq 77 # Transaction distribution 931system.membus.trans_dist::ReadExResp 77 # Transaction distribution 932system.membus.trans_dist::ReadSharedReq 338 # Transaction distribution 933system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 830 # Packet count per connected master and slave (bytes) 934system.membus.pkt_count_system.cpu.l2cache.mem_side::total 830 # Packet count per connected master and slave (bytes) 935system.membus.pkt_count::total 830 # Packet count per connected master and slave (bytes) 936system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26560 # Cumulative packet size per connected master and slave (bytes) 937system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26560 # Cumulative packet size per connected master and slave (bytes) 938system.membus.pkt_size::total 26560 # Cumulative packet size per connected master and slave (bytes) | 934system.membus.trans_dist::ReadResp 341 # Transaction distribution 935system.membus.trans_dist::ReadExReq 75 # Transaction distribution 936system.membus.trans_dist::ReadExResp 75 # Transaction distribution 937system.membus.trans_dist::ReadSharedReq 341 # Transaction distribution 938system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) 939system.membus.pkt_count_system.cpu.l2cache.mem_side::total 832 # Packet count per connected master and slave (bytes) 940system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) 941system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) 942system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) 943system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) |
| 939system.membus.snoops 0 # Total snoops (count) | 944system.membus.snoops 0 # Total snoops (count) |
| 940system.membus.snoop_fanout::samples 415 # Request fanout histogram | 945system.membus.snoop_fanout::samples 416 # Request fanout histogram |
| 941system.membus.snoop_fanout::mean 0 # Request fanout histogram 942system.membus.snoop_fanout::stdev 0 # Request fanout histogram 943system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 946system.membus.snoop_fanout::mean 0 # Request fanout histogram 947system.membus.snoop_fanout::stdev 0 # Request fanout histogram 948system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 944system.membus.snoop_fanout::0 415 100.00% 100.00% # Request fanout histogram | 949system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram |
| 945system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 946system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 947system.membus.snoop_fanout::min_value 0 # Request fanout histogram 948system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 950system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 951system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 952system.membus.snoop_fanout::min_value 0 # Request fanout histogram 953system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 949system.membus.snoop_fanout::total 415 # Request fanout histogram 950system.membus.reqLayer0.occupancy 500000 # Layer occupancy (ticks) | 954system.membus.snoop_fanout::total 416 # Request fanout histogram 955system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks) |
| 951system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) | 956system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) |
| 952system.membus.respLayer1.occupancy 2216750 # Layer occupancy (ticks) 953system.membus.respLayer1.utilization 10.6 # Layer utilization (%) | 957system.membus.respLayer1.occupancy 2222250 # Layer occupancy (ticks) 958system.membus.respLayer1.utilization 10.4 # Layer utilization (%) |
| 954 955---------- End Simulation Statistics ---------- | 959 960---------- End Simulation Statistics ---------- |