| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated |
| 4sim_ticks 20817000 # Number of ticks simulated 5final_tick 20817000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 20818000 # Number of ticks simulated 5final_tick 20818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 31285 # Simulator instruction rate (inst/s) 8host_op_rate 56673 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 121026192 # Simulator tick rate (ticks/s) 10host_mem_usage 306568 # Number of bytes of host memory used 11host_seconds 0.17 # Real time elapsed on the host | 7host_inst_rate 48919 # Simulator instruction rate (inst/s) 8host_op_rate 88616 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 189245943 # Simulator tick rate (ticks/s) 10host_mem_usage 313416 # Number of bytes of host memory used 11host_seconds 0.11 # Real time elapsed on the host |
| 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26560 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 415 # Number of read requests responded to by this memory | 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26560 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 415 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 848537253 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 427343037 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1275880290 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 848537253 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 848537253 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 848537253 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 427343037 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1275880290 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 848496493 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 427322509 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1275819003 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 848496493 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 848496493 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 848496493 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 427322509 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1275819003 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 415 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 415 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 20721000 # Total gap between requests | 78system.physmem.totGap 20722000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 415 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 114 unchanged lines hidden (view full) --- 201system.physmem.bytesPerActivate::1024-1151 5 5.21% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 96 # Bytes accessed per row activation 203system.physmem.totQLat 4745000 # Total ticks spent queuing 204system.physmem.totMemAccLat 12526250 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 11433.73 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 30183.73 # Average memory access latency per DRAM burst | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 415 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 114 unchanged lines hidden (view full) --- 201system.physmem.bytesPerActivate::1024-1151 5 5.21% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 96 # Bytes accessed per row activation 203system.physmem.totQLat 4745000 # Total ticks spent queuing 204system.physmem.totMemAccLat 12526250 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 11433.73 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 30183.73 # Average memory access latency per DRAM burst |
| 209system.physmem.avgRdBW 1275.88 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgRdBW 1275.82 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 1275.88 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 1275.82 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 9.97 # Data bus utilization in percentage 215system.physmem.busUtilRead 9.97 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 309 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 74.46 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 9.97 # Data bus utilization in percentage 215system.physmem.busUtilRead 9.97 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 309 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 74.46 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 49930.12 # Average gap between requests | 223system.physmem.avgGap 49932.53 # Average gap between requests |
| 224system.physmem.pageHitRate 74.46 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 959400 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) --- 25 unchanged lines hidden (view full) --- 257system.cpu.branchPred.BTBHits 881 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 34.454439 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 280 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 86 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 264system.cpu.workload.num_syscalls 11 # Number of system calls | 224system.physmem.pageHitRate 74.46 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 959400 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) --- 25 unchanged lines hidden (view full) --- 257system.cpu.branchPred.BTBHits 881 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 34.454439 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 280 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 86 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 264system.cpu.workload.num_syscalls 11 # Number of system calls |
| 265system.cpu.numCycles 41635 # number of cpu cycles simulated | 265system.cpu.numCycles 41637 # number of cpu cycles simulated |
| 266system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 267system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 268system.cpu.fetch.icacheStallCycles 11661 # Number of cycles fetch is stalled on an Icache miss 269system.cpu.fetch.Insts 14637 # Number of instructions fetch has processed 270system.cpu.fetch.Branches 3234 # Number of branches that fetch encountered 271system.cpu.fetch.predictedBranches 1161 # Number of branches that fetch has predicted taken 272system.cpu.fetch.Cycles 9674 # Number of cycles fetch has run and was not squashing or blocked 273system.cpu.fetch.SquashCycles 1159 # Number of cycles fetch has spent squashing --- 14 unchanged lines hidden (view full) --- 288system.cpu.fetch.rateDist::5 258 1.14% 86.99% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::6 336 1.48% 88.47% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::7 205 0.90% 89.37% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::8 2415 10.63% 100.00% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::total 22725 # Number of instructions fetched each cycle (Total) | 266system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 267system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 268system.cpu.fetch.icacheStallCycles 11661 # Number of cycles fetch is stalled on an Icache miss 269system.cpu.fetch.Insts 14637 # Number of instructions fetch has processed 270system.cpu.fetch.Branches 3234 # Number of branches that fetch encountered 271system.cpu.fetch.predictedBranches 1161 # Number of branches that fetch has predicted taken 272system.cpu.fetch.Cycles 9674 # Number of cycles fetch has run and was not squashing or blocked 273system.cpu.fetch.SquashCycles 1159 # Number of cycles fetch has spent squashing --- 14 unchanged lines hidden (view full) --- 288system.cpu.fetch.rateDist::5 258 1.14% 86.99% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::6 336 1.48% 88.47% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::7 205 0.90% 89.37% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::8 2415 10.63% 100.00% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::total 22725 # Number of instructions fetched each cycle (Total) |
| 296system.cpu.fetch.branchRate 0.077675 # Number of branch fetches per cycle 297system.cpu.fetch.rate 0.351555 # Number of inst fetches per cycle | 296system.cpu.fetch.branchRate 0.077671 # Number of branch fetches per cycle 297system.cpu.fetch.rate 0.351538 # Number of inst fetches per cycle |
| 298system.cpu.decode.IdleCycles 11462 # Number of cycles decode is idle 299system.cpu.decode.BlockedCycles 7072 # Number of cycles decode is blocked 300system.cpu.decode.RunCycles 3206 # Number of cycles decode is running 301system.cpu.decode.UnblockCycles 406 # Number of cycles decode is unblocking 302system.cpu.decode.SquashCycles 579 # Number of cycles decode is squashing 303system.cpu.decode.DecodedInsts 24310 # Number of instructions handled by decode 304system.cpu.rename.SquashCycles 579 # Number of cycles rename is squashing 305system.cpu.rename.IdleCycles 11710 # Number of cycles rename is idle --- 106 unchanged lines hidden (view full) --- 412system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.95% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.95% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.95% # Type of FU issued 415system.cpu.iq.FU_type_0::MemRead 2071 12.07% 92.02% # Type of FU issued 416system.cpu.iq.FU_type_0::MemWrite 1369 7.98% 100.00% # Type of FU issued 417system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 418system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 419system.cpu.iq.FU_type_0::total 17161 # Type of FU issued | 298system.cpu.decode.IdleCycles 11462 # Number of cycles decode is idle 299system.cpu.decode.BlockedCycles 7072 # Number of cycles decode is blocked 300system.cpu.decode.RunCycles 3206 # Number of cycles decode is running 301system.cpu.decode.UnblockCycles 406 # Number of cycles decode is unblocking 302system.cpu.decode.SquashCycles 579 # Number of cycles decode is squashing 303system.cpu.decode.DecodedInsts 24310 # Number of instructions handled by decode 304system.cpu.rename.SquashCycles 579 # Number of cycles rename is squashing 305system.cpu.rename.IdleCycles 11710 # Number of cycles rename is idle --- 106 unchanged lines hidden (view full) --- 412system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.95% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.95% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.95% # Type of FU issued 415system.cpu.iq.FU_type_0::MemRead 2071 12.07% 92.02% # Type of FU issued 416system.cpu.iq.FU_type_0::MemWrite 1369 7.98% 100.00% # Type of FU issued 417system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 418system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 419system.cpu.iq.FU_type_0::total 17161 # Type of FU issued |
| 420system.cpu.iq.rate 0.412177 # Inst issue rate | 420system.cpu.iq.rate 0.412157 # Inst issue rate |
| 421system.cpu.iq.fu_busy_cnt 212 # FU busy when requested 422system.cpu.iq.fu_busy_rate 0.012354 # FU busy rate (busy events/executed inst) 423system.cpu.iq.int_inst_queue_reads 57316 # Number of integer instruction queue reads 424system.cpu.iq.int_inst_queue_writes 31202 # Number of integer instruction queue writes 425system.cpu.iq.int_inst_queue_wakeup_accesses 15767 # Number of integer instruction queue wakeup accesses 426system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 427system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes 428system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses --- 27 unchanged lines hidden (view full) --- 456system.cpu.iew.iewExecutedInsts 16265 # Number of executed instructions 457system.cpu.iew.iewExecLoadInsts 1913 # Number of load instructions executed 458system.cpu.iew.iewExecSquashedInsts 896 # Number of squashed instructions skipped in execute 459system.cpu.iew.exec_swp 0 # number of swp insts executed 460system.cpu.iew.exec_nop 0 # number of nop insts executed 461system.cpu.iew.exec_refs 3175 # number of memory reference insts executed 462system.cpu.iew.exec_branches 1626 # Number of branches executed 463system.cpu.iew.exec_stores 1262 # Number of stores executed | 421system.cpu.iq.fu_busy_cnt 212 # FU busy when requested 422system.cpu.iq.fu_busy_rate 0.012354 # FU busy rate (busy events/executed inst) 423system.cpu.iq.int_inst_queue_reads 57316 # Number of integer instruction queue reads 424system.cpu.iq.int_inst_queue_writes 31202 # Number of integer instruction queue writes 425system.cpu.iq.int_inst_queue_wakeup_accesses 15767 # Number of integer instruction queue wakeup accesses 426system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 427system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes 428system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses --- 27 unchanged lines hidden (view full) --- 456system.cpu.iew.iewExecutedInsts 16265 # Number of executed instructions 457system.cpu.iew.iewExecLoadInsts 1913 # Number of load instructions executed 458system.cpu.iew.iewExecSquashedInsts 896 # Number of squashed instructions skipped in execute 459system.cpu.iew.exec_swp 0 # number of swp insts executed 460system.cpu.iew.exec_nop 0 # number of nop insts executed 461system.cpu.iew.exec_refs 3175 # number of memory reference insts executed 462system.cpu.iew.exec_branches 1626 # Number of branches executed 463system.cpu.iew.exec_stores 1262 # Number of stores executed |
| 464system.cpu.iew.exec_rate 0.390657 # Inst execution rate | 464system.cpu.iew.exec_rate 0.390638 # Inst execution rate |
| 465system.cpu.iew.wb_sent 16001 # cumulative count of insts sent to commit 466system.cpu.iew.wb_count 15771 # cumulative count of insts written-back 467system.cpu.iew.wb_producers 10637 # num instructions producing a value 468system.cpu.iew.wb_consumers 16589 # num instructions consuming a value 469system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 465system.cpu.iew.wb_sent 16001 # cumulative count of insts sent to commit 466system.cpu.iew.wb_count 15771 # cumulative count of insts written-back 467system.cpu.iew.wb_producers 10637 # num instructions producing a value 468system.cpu.iew.wb_consumers 16589 # num instructions consuming a value 469system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 470system.cpu.iew.wb_rate 0.378792 # insts written-back per cycle | 470system.cpu.iew.wb_rate 0.378774 # insts written-back per cycle |
| 471system.cpu.iew.wb_fanout 0.641208 # average fanout of values written-back 472system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 473system.cpu.commit.commitSquashedInsts 10723 # The number of squashed insts skipped by commit 474system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards 475system.cpu.commit.branchMispredicts 565 # The number of times a branch was mispredicted 476system.cpu.commit.committed_per_cycle::samples 20943 # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::mean 0.465406 # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::stdev 1.357230 # Number of insts commited each cycle --- 55 unchanged lines hidden (view full) --- 534system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction 535system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 536system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 537system.cpu.commit.op_class_0::total 9747 # Class of committed instruction 538system.cpu.commit.bw_lim_events 255 # number cycles where commit BW limit reached 539system.cpu.rob.rob_reads 41158 # The number of ROB reads 540system.cpu.rob.rob_writes 42744 # The number of ROB writes 541system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself | 471system.cpu.iew.wb_fanout 0.641208 # average fanout of values written-back 472system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 473system.cpu.commit.commitSquashedInsts 10723 # The number of squashed insts skipped by commit 474system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards 475system.cpu.commit.branchMispredicts 565 # The number of times a branch was mispredicted 476system.cpu.commit.committed_per_cycle::samples 20943 # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::mean 0.465406 # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::stdev 1.357230 # Number of insts commited each cycle --- 55 unchanged lines hidden (view full) --- 534system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction 535system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 536system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 537system.cpu.commit.op_class_0::total 9747 # Class of committed instruction 538system.cpu.commit.bw_lim_events 255 # number cycles where commit BW limit reached 539system.cpu.rob.rob_reads 41158 # The number of ROB reads 540system.cpu.rob.rob_writes 42744 # The number of ROB writes 541system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 542system.cpu.idleCycles 18910 # Total number of cycles that the CPU has spent unscheduled due to idling | 542system.cpu.idleCycles 18912 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 543system.cpu.committedInsts 5380 # Number of Instructions Simulated 544system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated | 543system.cpu.committedInsts 5380 # Number of Instructions Simulated 544system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated |
| 545system.cpu.cpi 7.738848 # CPI: Cycles Per Instruction 546system.cpu.cpi_total 7.738848 # CPI: Total CPI of All Threads 547system.cpu.ipc 0.129218 # IPC: Instructions Per Cycle 548system.cpu.ipc_total 0.129218 # IPC: Total IPC of All Threads | 545system.cpu.cpi 7.739219 # CPI: Cycles Per Instruction 546system.cpu.cpi_total 7.739219 # CPI: Total CPI of All Threads 547system.cpu.ipc 0.129212 # IPC: Instructions Per Cycle 548system.cpu.ipc_total 0.129212 # IPC: Total IPC of All Threads |
| 549system.cpu.int_regfile_reads 20871 # number of integer regfile reads 550system.cpu.int_regfile_writes 12651 # number of integer regfile writes 551system.cpu.fp_regfile_reads 4 # number of floating regfile reads 552system.cpu.cc_regfile_reads 8081 # number of cc regfile reads 553system.cpu.cc_regfile_writes 4880 # number of cc regfile writes 554system.cpu.misc_regfile_reads 7277 # number of misc regfile reads 555system.cpu.misc_regfile_writes 1 # number of misc regfile writes 556system.cpu.dcache.tags.replacements 0 # number of replacements | 549system.cpu.int_regfile_reads 20871 # number of integer regfile reads 550system.cpu.int_regfile_writes 12651 # number of integer regfile writes 551system.cpu.fp_regfile_reads 4 # number of floating regfile reads 552system.cpu.cc_regfile_reads 8081 # number of cc regfile reads 553system.cpu.cc_regfile_writes 4880 # number of cc regfile writes 554system.cpu.misc_regfile_reads 7277 # number of misc regfile reads 555system.cpu.misc_regfile_writes 1 # number of misc regfile writes 556system.cpu.dcache.tags.replacements 0 # number of replacements |
| 557system.cpu.dcache.tags.tagsinuse 81.971685 # Cycle average of tags in use | 557system.cpu.dcache.tags.tagsinuse 81.973847 # Cycle average of tags in use |
| 558system.cpu.dcache.tags.total_refs 2383 # Total number of references to valid blocks. 559system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks. 560system.cpu.dcache.tags.avg_refs 17.143885 # Average number of references to valid blocks. 561system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 558system.cpu.dcache.tags.total_refs 2383 # Total number of references to valid blocks. 559system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks. 560system.cpu.dcache.tags.avg_refs 17.143885 # Average number of references to valid blocks. 561system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 562system.cpu.dcache.tags.occ_blocks::cpu.data 81.971685 # Average occupied blocks per requestor | 562system.cpu.dcache.tags.occ_blocks::cpu.data 81.973847 # Average occupied blocks per requestor |
| 563system.cpu.dcache.tags.occ_percent::cpu.data 0.020013 # Average percentage of cache occupancy 564system.cpu.dcache.tags.occ_percent::total 0.020013 # Average percentage of cache occupancy 565system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id 566system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 567system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id 568system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id 569system.cpu.dcache.tags.tag_accesses 5305 # Number of tag accesses 570system.cpu.dcache.tags.data_accesses 5305 # Number of data accesses --- 88 unchanged lines hidden (view full) --- 659system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82545.454545 # average WriteReq mshr miss latency 660system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82545.454545 # average WriteReq mshr miss latency 661system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83758.992806 # average overall mshr miss latency 662system.cpu.dcache.demand_avg_mshr_miss_latency::total 83758.992806 # average overall mshr miss latency 663system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83758.992806 # average overall mshr miss latency 664system.cpu.dcache.overall_avg_mshr_miss_latency::total 83758.992806 # average overall mshr miss latency 665system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 666system.cpu.icache.tags.replacements 0 # number of replacements | 563system.cpu.dcache.tags.occ_percent::cpu.data 0.020013 # Average percentage of cache occupancy 564system.cpu.dcache.tags.occ_percent::total 0.020013 # Average percentage of cache occupancy 565system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id 566system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 567system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id 568system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id 569system.cpu.dcache.tags.tag_accesses 5305 # Number of tag accesses 570system.cpu.dcache.tags.data_accesses 5305 # Number of data accesses --- 88 unchanged lines hidden (view full) --- 659system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82545.454545 # average WriteReq mshr miss latency 660system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82545.454545 # average WriteReq mshr miss latency 661system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83758.992806 # average overall mshr miss latency 662system.cpu.dcache.demand_avg_mshr_miss_latency::total 83758.992806 # average overall mshr miss latency 663system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83758.992806 # average overall mshr miss latency 664system.cpu.dcache.overall_avg_mshr_miss_latency::total 83758.992806 # average overall mshr miss latency 665system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 666system.cpu.icache.tags.replacements 0 # number of replacements |
| 667system.cpu.icache.tags.tagsinuse 130.298609 # Cycle average of tags in use | 667system.cpu.icache.tags.tagsinuse 130.304167 # Cycle average of tags in use |
| 668system.cpu.icache.tags.total_refs 1706 # Total number of references to valid blocks. 669system.cpu.icache.tags.sampled_refs 277 # Sample count of references to valid blocks. 670system.cpu.icache.tags.avg_refs 6.158845 # Average number of references to valid blocks. 671system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 668system.cpu.icache.tags.total_refs 1706 # Total number of references to valid blocks. 669system.cpu.icache.tags.sampled_refs 277 # Sample count of references to valid blocks. 670system.cpu.icache.tags.avg_refs 6.158845 # Average number of references to valid blocks. 671system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 672system.cpu.icache.tags.occ_blocks::cpu.inst 130.298609 # Average occupied blocks per requestor 673system.cpu.icache.tags.occ_percent::cpu.inst 0.063622 # Average percentage of cache occupancy 674system.cpu.icache.tags.occ_percent::total 0.063622 # Average percentage of cache occupancy | 672system.cpu.icache.tags.occ_blocks::cpu.inst 130.304167 # Average occupied blocks per requestor 673system.cpu.icache.tags.occ_percent::cpu.inst 0.063625 # Average percentage of cache occupancy 674system.cpu.icache.tags.occ_percent::total 0.063625 # Average percentage of cache occupancy |
| 675system.cpu.icache.tags.occ_task_id_blocks::1024 277 # Occupied blocks per task id | 675system.cpu.icache.tags.occ_task_id_blocks::1024 277 # Occupied blocks per task id |
| 676system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id 677system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id | 676system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id 677system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id |
| 678system.cpu.icache.tags.occ_task_id_percent::1024 0.135254 # Percentage of cache occupancy per task id 679system.cpu.icache.tags.tag_accesses 4427 # Number of tag accesses 680system.cpu.icache.tags.data_accesses 4427 # Number of data accesses 681system.cpu.icache.ReadReq_hits::cpu.inst 1706 # number of ReadReq hits 682system.cpu.icache.ReadReq_hits::total 1706 # number of ReadReq hits 683system.cpu.icache.demand_hits::cpu.inst 1706 # number of demand (read+write) hits 684system.cpu.icache.demand_hits::total 1706 # number of demand (read+write) hits 685system.cpu.icache.overall_hits::cpu.inst 1706 # number of overall hits 686system.cpu.icache.overall_hits::total 1706 # number of overall hits 687system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses 688system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses 689system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses 690system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses 691system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses 692system.cpu.icache.overall_misses::total 369 # number of overall misses | 678system.cpu.icache.tags.occ_task_id_percent::1024 0.135254 # Percentage of cache occupancy per task id 679system.cpu.icache.tags.tag_accesses 4427 # Number of tag accesses 680system.cpu.icache.tags.data_accesses 4427 # Number of data accesses 681system.cpu.icache.ReadReq_hits::cpu.inst 1706 # number of ReadReq hits 682system.cpu.icache.ReadReq_hits::total 1706 # number of ReadReq hits 683system.cpu.icache.demand_hits::cpu.inst 1706 # number of demand (read+write) hits 684system.cpu.icache.demand_hits::total 1706 # number of demand (read+write) hits 685system.cpu.icache.overall_hits::cpu.inst 1706 # number of overall hits 686system.cpu.icache.overall_hits::total 1706 # number of overall hits 687system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses 688system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses 689system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses 690system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses 691system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses 692system.cpu.icache.overall_misses::total 369 # number of overall misses |
| 693system.cpu.icache.ReadReq_miss_latency::cpu.inst 28131500 # number of ReadReq miss cycles 694system.cpu.icache.ReadReq_miss_latency::total 28131500 # number of ReadReq miss cycles 695system.cpu.icache.demand_miss_latency::cpu.inst 28131500 # number of demand (read+write) miss cycles 696system.cpu.icache.demand_miss_latency::total 28131500 # number of demand (read+write) miss cycles 697system.cpu.icache.overall_miss_latency::cpu.inst 28131500 # number of overall miss cycles 698system.cpu.icache.overall_miss_latency::total 28131500 # number of overall miss cycles | 693system.cpu.icache.ReadReq_miss_latency::cpu.inst 28132500 # number of ReadReq miss cycles 694system.cpu.icache.ReadReq_miss_latency::total 28132500 # number of ReadReq miss cycles 695system.cpu.icache.demand_miss_latency::cpu.inst 28132500 # number of demand (read+write) miss cycles 696system.cpu.icache.demand_miss_latency::total 28132500 # number of demand (read+write) miss cycles 697system.cpu.icache.overall_miss_latency::cpu.inst 28132500 # number of overall miss cycles 698system.cpu.icache.overall_miss_latency::total 28132500 # number of overall miss cycles |
| 699system.cpu.icache.ReadReq_accesses::cpu.inst 2075 # number of ReadReq accesses(hits+misses) 700system.cpu.icache.ReadReq_accesses::total 2075 # number of ReadReq accesses(hits+misses) 701system.cpu.icache.demand_accesses::cpu.inst 2075 # number of demand (read+write) accesses 702system.cpu.icache.demand_accesses::total 2075 # number of demand (read+write) accesses 703system.cpu.icache.overall_accesses::cpu.inst 2075 # number of overall (read+write) accesses 704system.cpu.icache.overall_accesses::total 2075 # number of overall (read+write) accesses 705system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.177831 # miss rate for ReadReq accesses 706system.cpu.icache.ReadReq_miss_rate::total 0.177831 # miss rate for ReadReq accesses 707system.cpu.icache.demand_miss_rate::cpu.inst 0.177831 # miss rate for demand accesses 708system.cpu.icache.demand_miss_rate::total 0.177831 # miss rate for demand accesses 709system.cpu.icache.overall_miss_rate::cpu.inst 0.177831 # miss rate for overall accesses 710system.cpu.icache.overall_miss_rate::total 0.177831 # miss rate for overall accesses | 699system.cpu.icache.ReadReq_accesses::cpu.inst 2075 # number of ReadReq accesses(hits+misses) 700system.cpu.icache.ReadReq_accesses::total 2075 # number of ReadReq accesses(hits+misses) 701system.cpu.icache.demand_accesses::cpu.inst 2075 # number of demand (read+write) accesses 702system.cpu.icache.demand_accesses::total 2075 # number of demand (read+write) accesses 703system.cpu.icache.overall_accesses::cpu.inst 2075 # number of overall (read+write) accesses 704system.cpu.icache.overall_accesses::total 2075 # number of overall (read+write) accesses 705system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.177831 # miss rate for ReadReq accesses 706system.cpu.icache.ReadReq_miss_rate::total 0.177831 # miss rate for ReadReq accesses 707system.cpu.icache.demand_miss_rate::cpu.inst 0.177831 # miss rate for demand accesses 708system.cpu.icache.demand_miss_rate::total 0.177831 # miss rate for demand accesses 709system.cpu.icache.overall_miss_rate::cpu.inst 0.177831 # miss rate for overall accesses 710system.cpu.icache.overall_miss_rate::total 0.177831 # miss rate for overall accesses |
| 711system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76237.127371 # average ReadReq miss latency 712system.cpu.icache.ReadReq_avg_miss_latency::total 76237.127371 # average ReadReq miss latency 713system.cpu.icache.demand_avg_miss_latency::cpu.inst 76237.127371 # average overall miss latency 714system.cpu.icache.demand_avg_miss_latency::total 76237.127371 # average overall miss latency 715system.cpu.icache.overall_avg_miss_latency::cpu.inst 76237.127371 # average overall miss latency 716system.cpu.icache.overall_avg_miss_latency::total 76237.127371 # average overall miss latency | 711system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76239.837398 # average ReadReq miss latency 712system.cpu.icache.ReadReq_avg_miss_latency::total 76239.837398 # average ReadReq miss latency 713system.cpu.icache.demand_avg_miss_latency::cpu.inst 76239.837398 # average overall miss latency 714system.cpu.icache.demand_avg_miss_latency::total 76239.837398 # average overall miss latency 715system.cpu.icache.overall_avg_miss_latency::cpu.inst 76239.837398 # average overall miss latency 716system.cpu.icache.overall_avg_miss_latency::total 76239.837398 # average overall miss latency |
| 717system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 718system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 719system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 720system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 721system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 722system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 723system.cpu.icache.fast_writes 0 # number of fast writes performed 724system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 729system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits 730system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits 731system.cpu.icache.ReadReq_mshr_misses::cpu.inst 277 # number of ReadReq MSHR misses 732system.cpu.icache.ReadReq_mshr_misses::total 277 # number of ReadReq MSHR misses 733system.cpu.icache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses 734system.cpu.icache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses 735system.cpu.icache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses 736system.cpu.icache.overall_mshr_misses::total 277 # number of overall MSHR misses | 717system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 718system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 719system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 720system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 721system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 722system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 723system.cpu.icache.fast_writes 0 # number of fast writes performed 724system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 729system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits 730system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits 731system.cpu.icache.ReadReq_mshr_misses::cpu.inst 277 # number of ReadReq MSHR misses 732system.cpu.icache.ReadReq_mshr_misses::total 277 # number of ReadReq MSHR misses 733system.cpu.icache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses 734system.cpu.icache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses 735system.cpu.icache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses 736system.cpu.icache.overall_mshr_misses::total 277 # number of overall MSHR misses |
| 737system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22318000 # number of ReadReq MSHR miss cycles 738system.cpu.icache.ReadReq_mshr_miss_latency::total 22318000 # number of ReadReq MSHR miss cycles 739system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22318000 # number of demand (read+write) MSHR miss cycles 740system.cpu.icache.demand_mshr_miss_latency::total 22318000 # number of demand (read+write) MSHR miss cycles 741system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22318000 # number of overall MSHR miss cycles 742system.cpu.icache.overall_mshr_miss_latency::total 22318000 # number of overall MSHR miss cycles | 737system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22319000 # number of ReadReq MSHR miss cycles 738system.cpu.icache.ReadReq_mshr_miss_latency::total 22319000 # number of ReadReq MSHR miss cycles 739system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22319000 # number of demand (read+write) MSHR miss cycles 740system.cpu.icache.demand_mshr_miss_latency::total 22319000 # number of demand (read+write) MSHR miss cycles 741system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22319000 # number of overall MSHR miss cycles 742system.cpu.icache.overall_mshr_miss_latency::total 22319000 # number of overall MSHR miss cycles |
| 743system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for ReadReq accesses 744system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133494 # mshr miss rate for ReadReq accesses 745system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for demand accesses 746system.cpu.icache.demand_mshr_miss_rate::total 0.133494 # mshr miss rate for demand accesses 747system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for overall accesses 748system.cpu.icache.overall_mshr_miss_rate::total 0.133494 # mshr miss rate for overall accesses | 743system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for ReadReq accesses 744system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133494 # mshr miss rate for ReadReq accesses 745system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for demand accesses 746system.cpu.icache.demand_mshr_miss_rate::total 0.133494 # mshr miss rate for demand accesses 747system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for overall accesses 748system.cpu.icache.overall_mshr_miss_rate::total 0.133494 # mshr miss rate for overall accesses |
| 749system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80570.397112 # average ReadReq mshr miss latency 750system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80570.397112 # average ReadReq mshr miss latency 751system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80570.397112 # average overall mshr miss latency 752system.cpu.icache.demand_avg_mshr_miss_latency::total 80570.397112 # average overall mshr miss latency 753system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80570.397112 # average overall mshr miss latency 754system.cpu.icache.overall_avg_mshr_miss_latency::total 80570.397112 # average overall mshr miss latency | 749system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80574.007220 # average ReadReq mshr miss latency 750system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80574.007220 # average ReadReq mshr miss latency 751system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80574.007220 # average overall mshr miss latency 752system.cpu.icache.demand_avg_mshr_miss_latency::total 80574.007220 # average overall mshr miss latency 753system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80574.007220 # average overall mshr miss latency 754system.cpu.icache.overall_avg_mshr_miss_latency::total 80574.007220 # average overall mshr miss latency |
| 755system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 756system.cpu.l2cache.tags.replacements 0 # number of replacements | 755system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 756system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 757system.cpu.l2cache.tags.tagsinuse 162.374270 # Cycle average of tags in use | 757system.cpu.l2cache.tags.tagsinuse 162.380689 # Cycle average of tags in use |
| 758system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 759system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. 760system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. 761system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 758system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 759system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. 760system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. 761system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 762system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.338432 # Average occupied blocks per requestor 763system.cpu.l2cache.tags.occ_blocks::cpu.data 32.035838 # Average occupied blocks per requestor | 762system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.343988 # Average occupied blocks per requestor 763system.cpu.l2cache.tags.occ_blocks::cpu.data 32.036700 # Average occupied blocks per requestor |
| 764system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003978 # Average percentage of cache occupancy 765system.cpu.l2cache.tags.occ_percent::cpu.data 0.000978 # Average percentage of cache occupancy 766system.cpu.l2cache.tags.occ_percent::total 0.004955 # Average percentage of cache occupancy 767system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id 768system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id 769system.cpu.l2cache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id 770system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010315 # Percentage of cache occupancy per task id 771system.cpu.l2cache.tags.tag_accesses 3743 # Number of tag accesses --- 116 unchanged lines hidden (view full) --- 888system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73758.064516 # average ReadSharedReq mshr miss latency 889system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69317.028986 # average overall mshr miss latency 890system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency 891system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency 892system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69317.028986 # average overall mshr miss latency 893system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency 894system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency 895system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 764system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003978 # Average percentage of cache occupancy 765system.cpu.l2cache.tags.occ_percent::cpu.data 0.000978 # Average percentage of cache occupancy 766system.cpu.l2cache.tags.occ_percent::total 0.004955 # Average percentage of cache occupancy 767system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id 768system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id 769system.cpu.l2cache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id 770system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010315 # Percentage of cache occupancy per task id 771system.cpu.l2cache.tags.tag_accesses 3743 # Number of tag accesses --- 116 unchanged lines hidden (view full) --- 888system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73758.064516 # average ReadSharedReq mshr miss latency 889system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69317.028986 # average overall mshr miss latency 890system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency 891system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency 892system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69317.028986 # average overall mshr miss latency 893system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency 894system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency 895system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 896system.cpu.toL2Bus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter. 897system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 898system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 899system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 900system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 901system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 896system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 897system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution 898system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution 899system.cpu.toL2Bus.trans_dist::ReadCleanReq 277 # Transaction distribution 900system.cpu.toL2Bus.trans_dist::ReadSharedReq 62 # Transaction distribution 901system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 554 # Packet count per connected master and slave (bytes) 902system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes) 903system.cpu.toL2Bus.pkt_count::total 832 # Packet count per connected master and slave (bytes) 904system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17728 # Cumulative packet size per connected master and slave (bytes) 905system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8896 # Cumulative packet size per connected master and slave (bytes) 906system.cpu.toL2Bus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) 907system.cpu.toL2Bus.snoops 0 # Total snoops (count) 908system.cpu.toL2Bus.snoop_fanout::samples 416 # Request fanout histogram | 902system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 903system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution 904system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution 905system.cpu.toL2Bus.trans_dist::ReadCleanReq 277 # Transaction distribution 906system.cpu.toL2Bus.trans_dist::ReadSharedReq 62 # Transaction distribution 907system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 554 # Packet count per connected master and slave (bytes) 908system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes) 909system.cpu.toL2Bus.pkt_count::total 832 # Packet count per connected master and slave (bytes) 910system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17728 # Cumulative packet size per connected master and slave (bytes) 911system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8896 # Cumulative packet size per connected master and slave (bytes) 912system.cpu.toL2Bus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) 913system.cpu.toL2Bus.snoops 0 # Total snoops (count) 914system.cpu.toL2Bus.snoop_fanout::samples 416 # Request fanout histogram |
| 909system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 910system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 915system.cpu.toL2Bus.snoop_fanout::mean 0.002404 # Request fanout histogram 916system.cpu.toL2Bus.snoop_fanout::stdev 0.049029 # Request fanout histogram |
| 911system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 917system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 912system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 913system.cpu.toL2Bus.snoop_fanout::1 416 100.00% 100.00% # Request fanout histogram | 918system.cpu.toL2Bus.snoop_fanout::0 415 99.76% 99.76% # Request fanout histogram 919system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram |
| 914system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 915system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 920system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 921system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 916system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 922system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 917system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 918system.cpu.toL2Bus.snoop_fanout::total 416 # Request fanout histogram 919system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks) 920system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 921system.cpu.toL2Bus.respLayer0.occupancy 415500 # Layer occupancy (ticks) 922system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 923system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks) 924system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) --- 27 unchanged lines hidden --- | 923system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 924system.cpu.toL2Bus.snoop_fanout::total 416 # Request fanout histogram 925system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks) 926system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 927system.cpu.toL2Bus.respLayer0.occupancy 415500 # Layer occupancy (ticks) 928system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 929system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks) 930system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) --- 27 unchanged lines hidden --- |