| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated 4sim_ticks 21143500 # Number of ticks simulated 5final_tick 21143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 49814 # Simulator instruction rate (inst/s) 8host_op_rate 90238 # Simulator op (including micro ops) rate (op/s) --- 522 unchanged lines hidden (view full) --- 531system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction 533system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction 534system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction 535system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 536system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 537system.cpu.commit.op_class_0::total 9747 # Class of committed instruction 538system.cpu.commit.bw_lim_events 259 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated 4sim_ticks 21143500 # Number of ticks simulated 5final_tick 21143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 49814 # Simulator instruction rate (inst/s) 8host_op_rate 90238 # Simulator op (including micro ops) rate (op/s) --- 522 unchanged lines hidden (view full) --- 531system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction 533system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction 534system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction 535system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 536system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 537system.cpu.commit.op_class_0::total 9747 # Class of committed instruction 538system.cpu.commit.bw_lim_events 259 # number cycles where commit BW limit reached |
| 539system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 540system.cpu.rob.rob_reads 43058 # The number of ROB reads 541system.cpu.rob.rob_writes 44876 # The number of ROB writes 542system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself 543system.cpu.idleCycles 18450 # Total number of cycles that the CPU has spent unscheduled due to idling 544system.cpu.committedInsts 5380 # Number of Instructions Simulated 545system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated 546system.cpu.cpi 7.860223 # CPI: Cycles Per Instruction 547system.cpu.cpi_total 7.860223 # CPI: Total CPI of All Threads --- 397 unchanged lines hidden --- | 539system.cpu.rob.rob_reads 43058 # The number of ROB reads 540system.cpu.rob.rob_writes 44876 # The number of ROB writes 541system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself 542system.cpu.idleCycles 18450 # Total number of cycles that the CPU has spent unscheduled due to idling 543system.cpu.committedInsts 5380 # Number of Instructions Simulated 544system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated 545system.cpu.cpi 7.860223 # CPI: Cycles Per Instruction 546system.cpu.cpi_total 7.860223 # CPI: Total CPI of All Threads --- 397 unchanged lines hidden --- |