| stats.txt (10628:c9b7e0c69f88) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000020 # Number of seconds simulated 4sim_ticks 19678000 # Number of ticks simulated 5final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000021 # Number of seconds simulated 4sim_ticks 21143500 # Number of ticks simulated 5final_tick 21143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 46918 # Simulator instruction rate (inst/s) 8host_op_rate 84992 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 171550123 # Simulator tick rate (ticks/s) 10host_mem_usage 309548 # Number of bytes of host memory used | 7host_inst_rate 49814 # Simulator instruction rate (inst/s) 8host_op_rate 90238 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 195722405 # Simulator tick rate (ticks/s) 10host_mem_usage 309420 # Number of bytes of host memory used |
| 11host_seconds 0.11 # Real time elapsed on the host 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory | 11host_seconds 0.11 # Real time elapsed on the host 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 894399837 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 458583189 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1352983027 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 894399837 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 894399837 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 894399837 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 458583189 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1352983027 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 832407123 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 426797834 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1259204957 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 832407123 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 832407123 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 832407123 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 426797834 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1259204957 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 417 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 417 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 19629500 # Total gap between requests | 78system.physmem.totGap 21095000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 417 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 417 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 244 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see |
| 96system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 77 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 96system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 77 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 242.285714 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 158.475642 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 257.521253 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 36 36.73% 36.73% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 30 30.61% 67.35% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 13 13.27% 80.61% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 6 6.12% 86.73% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::640-767 6 6.12% 92.86% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::896-1023 4 4.08% 96.94% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1024-1151 3 3.06% 100.00% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation 201system.physmem.totQLat 4347000 # Total ticks spent queuing 202system.physmem.totMemAccLat 12165750 # Total ticks spent from burst creation until serviced by the DRAM | 189system.physmem.bytesPerActivate::samples 100 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 237.440000 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 159.807528 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 245.488436 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 35 35.00% 35.00% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 31 31.00% 66.00% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 16 16.00% 82.00% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 6 6.00% 88.00% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 2 2.00% 90.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 3 3.00% 93.00% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 2 2.00% 95.00% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 1 1.00% 96.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 4 4.00% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 100 # Bytes accessed per row activation 203system.physmem.totQLat 5105750 # Total ticks spent queuing 204system.physmem.totMemAccLat 12924500 # Total ticks spent from burst creation until serviced by the DRAM |
| 203system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers |
| 204system.physmem.avgQLat 10424.46 # Average queueing delay per DRAM burst | 206system.physmem.avgQLat 12244.00 # Average queueing delay per DRAM burst |
| 205system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 206system.physmem.avgMemAccLat 29174.46 # Average memory access latency per DRAM burst 207system.physmem.avgRdBW 1356.24 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 30994.00 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1262.23 # Average DRAM read bandwidth in MiByte/s |
| 208system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 209system.physmem.avgRdBWSys 1356.24 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 1262.23 # Average system read bandwidth in MiByte/s |
| 210system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 211system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 212system.physmem.busUtil 10.60 # Data bus utilization in percentage 213system.physmem.busUtilRead 10.60 # Data bus utilization in percentage for reads | 214system.physmem.busUtil 9.86 # Data bus utilization in percentage 215system.physmem.busUtilRead 9.86 # Data bus utilization in percentage for reads |
| 214system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 215system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing | 217system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing |
| 216system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 217system.physmem.readRowHits 309 # Number of row buffer hits during reads | 219system.physmem.readRowHits 307 # Number of row buffer hits during reads |
| 218system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 219system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 73.62 # Row buffer hit rate for reads |
| 220system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 221system.physmem.avgGap 47073.14 # Average gap between requests 222system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined 223system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) 224system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) 225system.physmem_0.readEnergy 1084200 # Energy for read commands per rank (pJ) | 223system.physmem.avgGap 50587.53 # Average gap between requests 224system.physmem.pageHitRate 73.62 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 936000 # Energy for read commands per rank (pJ) |
| 226system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 227system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) | 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) |
| 228system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) 229system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) 230system.physmem_0.totalEnergy 13267770 # Total energy per rank (pJ) 231system.physmem_0.averagePower 837.810088 # Core power per rank (mW) 232system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states | 230system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 13058475 # Total energy per rank (pJ) 233system.physmem_0.averagePower 824.789199 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states |
| 233system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 234system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 235system.physmem_0.memoryStateTime::ACT 15318250 # Time in different power states | 237system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states |
| 236system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 237system.physmem_1.actEnergy 446040 # Energy for activate commands per rank (pJ) 238system.physmem_1.preEnergy 243375 # Energy for precharge commands per rank (pJ) 239system.physmem_1.readEnergy 1567800 # Energy for read commands per rank (pJ) | 239system.physmem_1.actEnergy 438480 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 239250 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 1513200 # Energy for read commands per rank (pJ) |
| 240system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 241system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) | 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) |
| 242system.physmem_1.actBackEnergy 10701180 # Energy for active background per rank (pJ) 243system.physmem_1.preBackEnergy 112500 # Energy for precharge background per rank (pJ) 244system.physmem_1.totalEnergy 14088015 # Total energy per rank (pJ) 245system.physmem_1.averagePower 889.816201 # Core power per rank (mW) 246system.physmem_1.memoryStateTime::IDLE 882750 # Time in different power states | 244system.physmem_1.actBackEnergy 10696905 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 14021205 # Total energy per rank (pJ) 247system.physmem_1.averagePower 885.596400 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 102500 # Time in different power states |
| 247system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 248system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 249system.physmem_1.memoryStateTime::ACT 15230750 # Time in different power states | 251system.physmem_1.memoryStateTime::ACT 15223750 # Time in different power states |
| 250system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 251system.cpu.branchPred.lookups 3423 # Number of BP lookups 252system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted 253system.cpu.branchPred.condIncorrect 535 # Number of conditional branches incorrect 254system.cpu.branchPred.BTBLookups 2544 # Number of BTB lookups 255system.cpu.branchPred.BTBHits 864 # Number of BTB hits | 253system.cpu.branchPred.lookups 3414 # Number of BP lookups 254system.cpu.branchPred.condPredicted 3414 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 534 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 2533 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 863 # Number of BTB hits |
| 256system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 257system.cpu.branchPred.BTBHitPct 33.962264 # BTB Hit Percentage | 259system.cpu.branchPred.BTBHitPct 34.070272 # BTB Hit Percentage |
| 258system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target. 259system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. 260system.cpu_clk_domain.clock 500 # Clock period in ticks 261system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 262system.cpu.workload.num_syscalls 11 # Number of system calls | 260system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 264system.cpu.workload.num_syscalls 11 # Number of system calls |
| 263system.cpu.numCycles 39357 # number of cpu cycles simulated | 265system.cpu.numCycles 42288 # number of cpu cycles simulated |
| 264system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 265system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 266system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 267system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 266system.cpu.fetch.icacheStallCycles 10915 # Number of cycles fetch is stalled on an Icache miss 267system.cpu.fetch.Insts 15528 # Number of instructions fetch has processed 268system.cpu.fetch.Branches 3423 # Number of branches that fetch encountered 269system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken 270system.cpu.fetch.Cycles 9222 # Number of cycles fetch has run and was not squashing or blocked 271system.cpu.fetch.SquashCycles 1203 # Number of cycles fetch has spent squashing 272system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 273system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps | 268system.cpu.fetch.icacheStallCycles 12291 # Number of cycles fetch is stalled on an Icache miss 269system.cpu.fetch.Insts 15496 # Number of instructions fetch has processed 270system.cpu.fetch.Branches 3414 # Number of branches that fetch encountered 271system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken 272system.cpu.fetch.Cycles 9718 # Number of cycles fetch has run and was not squashing or blocked 273system.cpu.fetch.SquashCycles 1201 # Number of cycles fetch has spent squashing 274system.cpu.fetch.MiscStallCycles 55 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 275system.cpu.fetch.PendingTrapStallCycles 1161 # Number of stall cycles due to pending traps |
| 274system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions | 276system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions |
| 275system.cpu.fetch.CacheLines 2168 # Number of cache lines fetched 276system.cpu.fetch.IcacheSquashes 278 # Number of outstanding Icache misses that were squashed 277system.cpu.fetch.rateDist::samples 21893 # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::mean 1.270406 # Number of instructions fetched each cycle (Total) 279system.cpu.fetch.rateDist::stdev 2.764504 # Number of instructions fetched each cycle (Total) | 277system.cpu.fetch.CacheLines 2164 # Number of cache lines fetched 278system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed 279system.cpu.fetch.rateDist::samples 23838 # Number of instructions fetched each cycle (Total) 280system.cpu.fetch.rateDist::mean 1.164108 # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::stdev 2.669642 # Number of instructions fetched each cycle (Total) |
| 280system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 282system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 281system.cpu.fetch.rateDist::0 17618 80.47% 80.47% # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::1 236 1.08% 81.55% # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::2 174 0.79% 82.35% # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::3 259 1.18% 83.53% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::4 208 0.95% 84.48% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::5 227 1.04% 85.52% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::6 339 1.55% 87.06% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::7 205 0.94% 88.00% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::8 2627 12.00% 100.00% # Number of instructions fetched each cycle (Total) | 283system.cpu.fetch.rateDist::0 19573 82.11% 82.11% # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::1 236 0.99% 83.10% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::2 173 0.73% 83.82% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::3 257 1.08% 84.90% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::4 208 0.87% 85.77% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::5 228 0.96% 86.73% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::6 337 1.41% 88.14% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::7 205 0.86% 89.00% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::8 2621 11.00% 100.00% # Number of instructions fetched each cycle (Total) |
| 290system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 292system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 293system.cpu.fetch.rateDist::total 21893 # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.branchRate 0.086973 # Number of branch fetches per cycle 295system.cpu.fetch.rate 0.394542 # Number of inst fetches per cycle 296system.cpu.decode.IdleCycles 10660 # Number of cycles decode is idle 297system.cpu.decode.BlockedCycles 6840 # Number of cycles decode is blocked 298system.cpu.decode.RunCycles 3336 # Number of cycles decode is running 299system.cpu.decode.UnblockCycles 456 # Number of cycles decode is unblocking 300system.cpu.decode.SquashCycles 601 # Number of cycles decode is squashing 301system.cpu.decode.DecodedInsts 25755 # Number of instructions handled by decode 302system.cpu.rename.SquashCycles 601 # Number of cycles rename is squashing 303system.cpu.rename.IdleCycles 10929 # Number of cycles rename is idle 304system.cpu.rename.BlockCycles 2194 # Number of cycles rename is blocking 305system.cpu.rename.serializeStallCycles 719 # count of cycles rename stalled for serializing inst 306system.cpu.rename.RunCycles 3480 # Number of cycles rename is running 307system.cpu.rename.UnblockCycles 3970 # Number of cycles rename is unblocking 308system.cpu.rename.RenamedInsts 24219 # Number of instructions processed by rename | 295system.cpu.fetch.rateDist::total 23838 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.branchRate 0.080732 # Number of branch fetches per cycle 297system.cpu.fetch.rate 0.366440 # Number of inst fetches per cycle 298system.cpu.decode.IdleCycles 12043 # Number of cycles decode is idle 299system.cpu.decode.BlockedCycles 7408 # Number of cycles decode is blocked 300system.cpu.decode.RunCycles 3332 # Number of cycles decode is running 301system.cpu.decode.UnblockCycles 455 # Number of cycles decode is unblocking 302system.cpu.decode.SquashCycles 600 # Number of cycles decode is squashing 303system.cpu.decode.DecodedInsts 25703 # Number of instructions handled by decode 304system.cpu.rename.SquashCycles 600 # Number of cycles rename is squashing 305system.cpu.rename.IdleCycles 12311 # Number of cycles rename is idle 306system.cpu.rename.BlockCycles 2293 # Number of cycles rename is blocking 307system.cpu.rename.serializeStallCycles 795 # count of cycles rename stalled for serializing inst 308system.cpu.rename.RunCycles 3474 # Number of cycles rename is running 309system.cpu.rename.UnblockCycles 4365 # Number of cycles rename is unblocking 310system.cpu.rename.RenamedInsts 24179 # Number of instructions processed by rename |
| 309system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full 310system.cpu.rename.IQFullEvents 93 # Number of times rename has blocked due to IQ full | 311system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full 312system.cpu.rename.IQFullEvents 93 # Number of times rename has blocked due to IQ full |
| 311system.cpu.rename.SQFullEvents 3820 # Number of times rename has blocked due to SQ full 312system.cpu.rename.RenamedOperands 27591 # Number of destination operands rename has renamed 313system.cpu.rename.RenameLookups 59364 # Number of register rename lookups that rename has made 314system.cpu.rename.int_rename_lookups 33558 # Number of integer rename lookups | 313system.cpu.rename.SQFullEvents 4214 # Number of times rename has blocked due to SQ full 314system.cpu.rename.RenamedOperands 27545 # Number of destination operands rename has renamed 315system.cpu.rename.RenameLookups 59275 # Number of register rename lookups that rename has made 316system.cpu.rename.int_rename_lookups 33508 # Number of integer rename lookups |
| 315system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 316system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed | 317system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 318system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed |
| 317system.cpu.rename.UndoneMaps 16528 # Number of HB maps that are undone due to squashing | 319system.cpu.rename.UndoneMaps 16482 # Number of HB maps that are undone due to squashing |
| 318system.cpu.rename.serializingInsts 29 # count of serializing insts renamed 319system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed | 320system.cpu.rename.serializingInsts 29 # count of serializing insts renamed 321system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed |
| 320system.cpu.rename.skidInsts 1503 # count of insts added to the skid buffer 321system.cpu.memDep0.insertedLoads 2441 # Number of loads inserted to the mem dependence unit. 322system.cpu.memDep0.insertedStores 1612 # Number of stores inserted to the mem dependence unit. | 322system.cpu.rename.skidInsts 1507 # count of insts added to the skid buffer 323system.cpu.memDep0.insertedLoads 2438 # Number of loads inserted to the mem dependence unit. 324system.cpu.memDep0.insertedStores 1611 # Number of stores inserted to the mem dependence unit. |
| 323system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. 324system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. | 325system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. 326system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. |
| 325system.cpu.iq.iqInstsAdded 21443 # Number of instructions added to the IQ (excludes non-spec) | 327system.cpu.iq.iqInstsAdded 21419 # Number of instructions added to the IQ (excludes non-spec) |
| 326system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ | 328system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ |
| 327system.cpu.iq.iqInstsIssued 17897 # Number of instructions issued 328system.cpu.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued 329system.cpu.iq.iqSquashedInstsExamined 11052 # Number of squashed instructions iterated over during squash; mainly for profiling 330system.cpu.iq.iqSquashedOperandsExamined 16525 # Number of squashed operands that are examined and possibly removed from graph | 329system.cpu.iq.iqInstsIssued 17882 # Number of instructions issued 330system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued 331system.cpu.iq.iqSquashedInstsExamined 11007 # Number of squashed instructions iterated over during squash; mainly for profiling 332system.cpu.iq.iqSquashedOperandsExamined 16508 # Number of squashed operands that are examined and possibly removed from graph |
| 331system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed | 333system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed |
| 332system.cpu.iq.issued_per_cycle::samples 21893 # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::mean 0.817476 # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::stdev 1.773238 # Number of insts issued each cycle | 334system.cpu.iq.issued_per_cycle::samples 23838 # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::mean 0.750147 # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::stdev 1.712551 # Number of insts issued each cycle |
| 335system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 337system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 336system.cpu.iq.issued_per_cycle::0 16772 76.61% 76.61% # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::1 1137 5.19% 81.80% # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::2 886 4.05% 85.85% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::3 636 2.91% 88.75% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::4 833 3.80% 92.56% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::5 590 2.69% 95.25% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::6 599 2.74% 97.99% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::7 316 1.44% 99.43% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::8 124 0.57% 100.00% # Number of insts issued each cycle | 338system.cpu.iq.issued_per_cycle::0 18713 78.50% 78.50% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::1 1142 4.79% 83.29% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::2 888 3.73% 87.02% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::3 640 2.68% 89.70% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::4 832 3.49% 93.19% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::5 584 2.45% 95.64% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::6 601 2.52% 98.16% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::7 314 1.32% 99.48% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::8 124 0.52% 100.00% # Number of insts issued each cycle |
| 345system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 347system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 348system.cpu.iq.issued_per_cycle::total 21893 # Number of insts issued each cycle | 350system.cpu.iq.issued_per_cycle::total 23838 # Number of insts issued each cycle |
| 349system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 351system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 350system.cpu.iq.fu_full::IntAlu 174 77.68% 77.68% # attempts to use FU when none available 351system.cpu.iq.fu_full::IntMult 0 0.00% 77.68% # attempts to use FU when none available 352system.cpu.iq.fu_full::IntDiv 0 0.00% 77.68% # attempts to use FU when none available 353system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.68% # attempts to use FU when none available 354system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.68% # attempts to use FU when none available 355system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.68% # attempts to use FU when none available 356system.cpu.iq.fu_full::FloatMult 0 0.00% 77.68% # attempts to use FU when none available 357system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.68% # attempts to use FU when none available 358system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.68% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.68% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.68% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.68% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.68% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.68% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.68% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdMult 0 0.00% 77.68% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.68% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdShift 0 0.00% 77.68% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.68% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.68% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.68% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.68% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.68% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.68% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.68% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.68% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.68% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.68% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.68% # attempts to use FU when none available 379system.cpu.iq.fu_full::MemRead 31 13.84% 91.52% # attempts to use FU when none available 380system.cpu.iq.fu_full::MemWrite 19 8.48% 100.00% # attempts to use FU when none available | 352system.cpu.iq.fu_full::IntAlu 173 77.58% 77.58% # attempts to use FU when none available 353system.cpu.iq.fu_full::IntMult 0 0.00% 77.58% # attempts to use FU when none available 354system.cpu.iq.fu_full::IntDiv 0 0.00% 77.58% # attempts to use FU when none available 355system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.58% # attempts to use FU when none available 356system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.58% # attempts to use FU when none available 357system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.58% # attempts to use FU when none available 358system.cpu.iq.fu_full::FloatMult 0 0.00% 77.58% # attempts to use FU when none available 359system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.58% # attempts to use FU when none available 360system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.58% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.58% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.58% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.58% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.58% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.58% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.58% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdMult 0 0.00% 77.58% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.58% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdShift 0 0.00% 77.58% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.58% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.58% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.58% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.58% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.58% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.58% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.58% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.58% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.58% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.58% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.58% # attempts to use FU when none available 381system.cpu.iq.fu_full::MemRead 31 13.90% 91.48% # attempts to use FU when none available 382system.cpu.iq.fu_full::MemWrite 19 8.52% 100.00% # attempts to use FU when none available |
| 381system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 382system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 383system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued | 383system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 384system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 385system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued |
| 384system.cpu.iq.FU_type_0::IntAlu 14382 80.36% 80.38% # Type of FU issued 385system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.40% # Type of FU issued 386system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.44% # Type of FU issued 387system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.44% # Type of FU issued 388system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.44% # Type of FU issued 389system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.44% # Type of FU issued 390system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.44% # Type of FU issued 391system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.44% # Type of FU issued 392system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.44% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.44% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.44% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.44% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.44% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.44% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.44% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.44% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.44% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.44% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.44% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.44% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.44% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.44% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.44% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.44% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.44% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.44% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.44% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.44% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.44% # Type of FU issued 413system.cpu.iq.FU_type_0::MemRead 2122 11.86% 92.29% # Type of FU issued | 386system.cpu.iq.FU_type_0::IntAlu 14368 80.35% 80.37% # Type of FU issued 387system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.39% # Type of FU issued 388system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.43% # Type of FU issued 389system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.43% # Type of FU issued 390system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.43% # Type of FU issued 391system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.43% # Type of FU issued 392system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.43% # Type of FU issued 393system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.43% # Type of FU issued 394system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.43% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.43% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.43% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.43% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.43% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.43% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.43% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.43% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.43% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.43% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.43% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.43% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.43% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.43% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.43% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.43% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.43% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.43% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.43% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.43% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.43% # Type of FU issued 415system.cpu.iq.FU_type_0::MemRead 2121 11.86% 92.29% # Type of FU issued |
| 414system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Type of FU issued 415system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 416system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 416system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Type of FU issued 417system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 418system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 417system.cpu.iq.FU_type_0::total 17897 # Type of FU issued 418system.cpu.iq.rate 0.454735 # Inst issue rate 419system.cpu.iq.fu_busy_cnt 224 # FU busy when requested 420system.cpu.iq.fu_busy_rate 0.012516 # FU busy rate (busy events/executed inst) 421system.cpu.iq.int_inst_queue_reads 57983 # Number of integer instruction queue reads 422system.cpu.iq.int_inst_queue_writes 32531 # Number of integer instruction queue writes 423system.cpu.iq.int_inst_queue_wakeup_accesses 16370 # Number of integer instruction queue wakeup accesses | 419system.cpu.iq.FU_type_0::total 17882 # Type of FU issued 420system.cpu.iq.rate 0.422862 # Inst issue rate 421system.cpu.iq.fu_busy_cnt 223 # FU busy when requested 422system.cpu.iq.fu_busy_rate 0.012471 # FU busy rate (busy events/executed inst) 423system.cpu.iq.int_inst_queue_reads 59896 # Number of integer instruction queue reads 424system.cpu.iq.int_inst_queue_writes 32462 # Number of integer instruction queue writes 425system.cpu.iq.int_inst_queue_wakeup_accesses 16353 # Number of integer instruction queue wakeup accesses |
| 424system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 425system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 426system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses | 426system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 427system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 428system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses |
| 427system.cpu.iq.int_alu_accesses 18114 # Number of integer alu accesses | 429system.cpu.iq.int_alu_accesses 18098 # Number of integer alu accesses |
| 428system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses | 430system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses |
| 429system.cpu.iew.lsq.thread0.forwLoads 228 # Number of loads that had data forwarded from stores | 431system.cpu.iew.lsq.thread0.forwLoads 235 # Number of loads that had data forwarded from stores |
| 430system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 432system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 431system.cpu.iew.lsq.thread0.squashedLoads 1388 # Number of loads squashed | 433system.cpu.iew.lsq.thread0.squashedLoads 1385 # Number of loads squashed |
| 432system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed 433system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations | 434system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed 435system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations |
| 434system.cpu.iew.lsq.thread0.squashedStores 677 # Number of stores squashed | 436system.cpu.iew.lsq.thread0.squashedStores 676 # Number of stores squashed |
| 435system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 436system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 437system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 438system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked 439system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 437system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 438system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 439system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 440system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked 441system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 440system.cpu.iew.iewSquashCycles 601 # Number of cycles IEW is squashing 441system.cpu.iew.iewBlockCycles 1862 # Number of cycles IEW is blocking 442system.cpu.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking 443system.cpu.iew.iewDispatchedInsts 21468 # Number of instructions dispatched to IQ | 442system.cpu.iew.iewSquashCycles 600 # Number of cycles IEW is squashing 443system.cpu.iew.iewBlockCycles 1925 # Number of cycles IEW is blocking 444system.cpu.iew.iewUnblockCycles 68 # Number of cycles IEW is unblocking 445system.cpu.iew.iewDispatchedInsts 21444 # Number of instructions dispatched to IQ |
| 444system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch | 446system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch |
| 445system.cpu.iew.iewDispLoadInsts 2441 # Number of dispatched load instructions 446system.cpu.iew.iewDispStoreInsts 1612 # Number of dispatched store instructions | 447system.cpu.iew.iewDispLoadInsts 2438 # Number of dispatched load instructions 448system.cpu.iew.iewDispStoreInsts 1611 # Number of dispatched store instructions |
| 447system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions 448system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall | 449system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions 450system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall |
| 449system.cpu.iew.iewLSQFullEvents 46 # Number of times the LSQ has become full, causing a stall | 451system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall |
| 450system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations 451system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly | 452system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations 453system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly |
| 452system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly 453system.cpu.iew.branchMispredicts 695 # Number of branch mispredicts detected at execute 454system.cpu.iew.iewExecutedInsts 16926 # Number of executed instructions 455system.cpu.iew.iewExecLoadInsts 1969 # Number of load instructions executed 456system.cpu.iew.iewExecSquashedInsts 971 # Number of squashed instructions skipped in execute | 454system.cpu.iew.predictedNotTakenIncorrect 569 # Number of branches that were predicted not taken incorrectly 455system.cpu.iew.branchMispredicts 694 # Number of branch mispredicts detected at execute 456system.cpu.iew.iewExecutedInsts 16910 # Number of executed instructions 457system.cpu.iew.iewExecLoadInsts 1967 # Number of load instructions executed 458system.cpu.iew.iewExecSquashedInsts 972 # Number of squashed instructions skipped in execute |
| 457system.cpu.iew.exec_swp 0 # number of swp insts executed 458system.cpu.iew.exec_nop 0 # number of nop insts executed | 459system.cpu.iew.exec_swp 0 # number of swp insts executed 460system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 459system.cpu.iew.exec_refs 3251 # number of memory reference insts executed 460system.cpu.iew.exec_branches 1662 # Number of branches executed | 461system.cpu.iew.exec_refs 3249 # number of memory reference insts executed 462system.cpu.iew.exec_branches 1660 # Number of branches executed |
| 461system.cpu.iew.exec_stores 1282 # Number of stores executed | 463system.cpu.iew.exec_stores 1282 # Number of stores executed |
| 462system.cpu.iew.exec_rate 0.430063 # Inst execution rate 463system.cpu.iew.wb_sent 16636 # cumulative count of insts sent to commit 464system.cpu.iew.wb_count 16374 # cumulative count of insts written-back 465system.cpu.iew.wb_producers 11006 # num instructions producing a value 466system.cpu.iew.wb_consumers 17135 # num instructions consuming a value | 464system.cpu.iew.exec_rate 0.399877 # Inst execution rate 465system.cpu.iew.wb_sent 16617 # cumulative count of insts sent to commit 466system.cpu.iew.wb_count 16357 # cumulative count of insts written-back 467system.cpu.iew.wb_producers 10994 # num instructions producing a value 468system.cpu.iew.wb_consumers 17115 # num instructions consuming a value |
| 467system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 469system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 468system.cpu.iew.wb_rate 0.416038 # insts written-back per cycle 469system.cpu.iew.wb_fanout 0.642311 # average fanout of values written-back | 470system.cpu.iew.wb_rate 0.386800 # insts written-back per cycle 471system.cpu.iew.wb_fanout 0.642361 # average fanout of values written-back |
| 470system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 472system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 471system.cpu.commit.commitSquashedInsts 11720 # The number of squashed insts skipped by commit | 473system.cpu.commit.commitSquashedInsts 11696 # The number of squashed insts skipped by commit |
| 472system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards | 474system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards |
| 473system.cpu.commit.branchMispredicts 588 # The number of times a branch was mispredicted 474system.cpu.commit.committed_per_cycle::samples 19924 # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::mean 0.489209 # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::stdev 1.394281 # Number of insts commited each cycle | 475system.cpu.commit.branchMispredicts 587 # The number of times a branch was mispredicted 476system.cpu.commit.committed_per_cycle::samples 21874 # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::mean 0.445598 # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::stdev 1.336765 # Number of insts commited each cycle |
| 477system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 479system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 478system.cpu.commit.committed_per_cycle::0 16684 83.74% 83.74% # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::1 1003 5.03% 88.77% # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::2 547 2.75% 91.52% # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::3 737 3.70% 95.22% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::4 365 1.83% 97.05% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::5 142 0.71% 97.76% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::6 113 0.57% 98.33% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::7 73 0.37% 98.70% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::8 260 1.30% 100.00% # Number of insts commited each cycle | 480system.cpu.commit.committed_per_cycle::0 18628 85.16% 85.16% # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::1 1010 4.62% 89.78% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::2 544 2.49% 92.26% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::3 738 3.37% 95.64% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::4 369 1.69% 97.33% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::5 141 0.64% 97.97% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::6 113 0.52% 98.49% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::7 72 0.33% 98.82% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::8 259 1.18% 100.00% # Number of insts commited each cycle |
| 487system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 489system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 490system.cpu.commit.committed_per_cycle::total 19924 # Number of insts commited each cycle | 492system.cpu.commit.committed_per_cycle::total 21874 # Number of insts commited each cycle |
| 491system.cpu.commit.committedInsts 5380 # Number of instructions committed 492system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed 493system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 494system.cpu.commit.refs 1988 # Number of memory references committed 495system.cpu.commit.loads 1053 # Number of loads committed 496system.cpu.commit.membars 0 # Number of memory barriers committed 497system.cpu.commit.branches 1208 # Number of branches committed 498system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 528system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction 530system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction 531system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction 532system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction 533system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 534system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 535system.cpu.commit.op_class_0::total 9747 # Class of committed instruction | 493system.cpu.commit.committedInsts 5380 # Number of instructions committed 494system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed 495system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 496system.cpu.commit.refs 1988 # Number of memory references committed 497system.cpu.commit.loads 1053 # Number of loads committed 498system.cpu.commit.membars 0 # Number of memory barriers committed 499system.cpu.commit.branches 1208 # Number of branches committed 500system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 530system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction 531system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction 533system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction 534system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction 535system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 536system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 537system.cpu.commit.op_class_0::total 9747 # Class of committed instruction |
| 536system.cpu.commit.bw_lim_events 260 # number cycles where commit BW limit reached | 538system.cpu.commit.bw_lim_events 259 # number cycles where commit BW limit reached |
| 537system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 539system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 538system.cpu.rob.rob_reads 41131 # The number of ROB reads 539system.cpu.rob.rob_writes 44929 # The number of ROB writes 540system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself 541system.cpu.idleCycles 17464 # Total number of cycles that the CPU has spent unscheduled due to idling | 540system.cpu.rob.rob_reads 43058 # The number of ROB reads 541system.cpu.rob.rob_writes 44876 # The number of ROB writes 542system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself 543system.cpu.idleCycles 18450 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 542system.cpu.committedInsts 5380 # Number of Instructions Simulated 543system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated | 544system.cpu.committedInsts 5380 # Number of Instructions Simulated 545system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated |
| 544system.cpu.cpi 7.315428 # CPI: Cycles Per Instruction 545system.cpu.cpi_total 7.315428 # CPI: Total CPI of All Threads 546system.cpu.ipc 0.136697 # IPC: Instructions Per Cycle 547system.cpu.ipc_total 0.136697 # IPC: Total IPC of All Threads 548system.cpu.int_regfile_reads 21341 # number of integer regfile reads 549system.cpu.int_regfile_writes 13120 # number of integer regfile writes | 546system.cpu.cpi 7.860223 # CPI: Cycles Per Instruction 547system.cpu.cpi_total 7.860223 # CPI: Total CPI of All Threads 548system.cpu.ipc 0.127223 # IPC: Instructions Per Cycle 549system.cpu.ipc_total 0.127223 # IPC: Total IPC of All Threads 550system.cpu.int_regfile_reads 21328 # number of integer regfile reads 551system.cpu.int_regfile_writes 13105 # number of integer regfile writes |
| 550system.cpu.fp_regfile_reads 4 # number of floating regfile reads | 552system.cpu.fp_regfile_reads 4 # number of floating regfile reads |
| 551system.cpu.cc_regfile_reads 8069 # number of cc regfile reads | 553system.cpu.cc_regfile_reads 8064 # number of cc regfile reads |
| 552system.cpu.cc_regfile_writes 5036 # number of cc regfile writes | 554system.cpu.cc_regfile_writes 5036 # number of cc regfile writes |
| 553system.cpu.misc_regfile_reads 7491 # number of misc regfile reads | 555system.cpu.misc_regfile_reads 7485 # number of misc regfile reads |
| 554system.cpu.misc_regfile_writes 1 # number of misc regfile writes 555system.cpu.dcache.tags.replacements 0 # number of replacements | 556system.cpu.misc_regfile_writes 1 # number of misc regfile writes 557system.cpu.dcache.tags.replacements 0 # number of replacements |
| 556system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use 557system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. | 558system.cpu.dcache.tags.tagsinuse 82.313704 # Cycle average of tags in use 559system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks. |
| 558system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. | 560system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. |
| 559system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. | 561system.cpu.dcache.tags.avg_refs 16.971631 # Average number of references to valid blocks. |
| 560system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 562system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 561system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor 562system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy 563system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy | 563system.cpu.dcache.tags.occ_blocks::cpu.data 82.313704 # Average occupied blocks per requestor 564system.cpu.dcache.tags.occ_percent::cpu.data 0.020096 # Average percentage of cache occupancy 565system.cpu.dcache.tags.occ_percent::total 0.020096 # Average percentage of cache occupancy |
| 564system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id | 566system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id |
| 565system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 566system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id | 567system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 568system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id |
| 567system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id | 569system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id |
| 568system.cpu.dcache.tags.tag_accesses 5369 # Number of tag accesses 569system.cpu.dcache.tags.data_accesses 5369 # Number of data accesses 570system.cpu.dcache.ReadReq_hits::cpu.data 1543 # number of ReadReq hits 571system.cpu.dcache.ReadReq_hits::total 1543 # number of ReadReq hits | 570system.cpu.dcache.tags.tag_accesses 5351 # Number of tag accesses 571system.cpu.dcache.tags.data_accesses 5351 # Number of data accesses 572system.cpu.dcache.ReadReq_hits::cpu.data 1536 # number of ReadReq hits 573system.cpu.dcache.ReadReq_hits::total 1536 # number of ReadReq hits |
| 572system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits 573system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits | 574system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits 575system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits |
| 574system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits 575system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits 576system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits 577system.cpu.dcache.overall_hits::total 2400 # number of overall hits 578system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses 579system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses | 576system.cpu.dcache.demand_hits::cpu.data 2393 # number of demand (read+write) hits 577system.cpu.dcache.demand_hits::total 2393 # number of demand (read+write) hits 578system.cpu.dcache.overall_hits::cpu.data 2393 # number of overall hits 579system.cpu.dcache.overall_hits::total 2393 # number of overall hits 580system.cpu.dcache.ReadReq_misses::cpu.data 134 # number of ReadReq misses 581system.cpu.dcache.ReadReq_misses::total 134 # number of ReadReq misses |
| 580system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses 581system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses | 582system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses 583system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses |
| 582system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses 583system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses 584system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses 585system.cpu.dcache.overall_misses::total 214 # number of overall misses 586system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles 587system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles 588system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles 589system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles 590system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles 591system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles 592system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles 593system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles 594system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) 595system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) | 584system.cpu.dcache.demand_misses::cpu.data 212 # number of demand (read+write) misses 585system.cpu.dcache.demand_misses::total 212 # number of demand (read+write) misses 586system.cpu.dcache.overall_misses::cpu.data 212 # number of overall misses 587system.cpu.dcache.overall_misses::total 212 # number of overall misses 588system.cpu.dcache.ReadReq_miss_latency::cpu.data 11119000 # number of ReadReq miss cycles 589system.cpu.dcache.ReadReq_miss_latency::total 11119000 # number of ReadReq miss cycles 590system.cpu.dcache.WriteReq_miss_latency::cpu.data 6761250 # number of WriteReq miss cycles 591system.cpu.dcache.WriteReq_miss_latency::total 6761250 # number of WriteReq miss cycles 592system.cpu.dcache.demand_miss_latency::cpu.data 17880250 # number of demand (read+write) miss cycles 593system.cpu.dcache.demand_miss_latency::total 17880250 # number of demand (read+write) miss cycles 594system.cpu.dcache.overall_miss_latency::cpu.data 17880250 # number of overall miss cycles 595system.cpu.dcache.overall_miss_latency::total 17880250 # number of overall miss cycles 596system.cpu.dcache.ReadReq_accesses::cpu.data 1670 # number of ReadReq accesses(hits+misses) 597system.cpu.dcache.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) |
| 596system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 597system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) | 598system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 599system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) |
| 598system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses 599system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses 600system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses 601system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses 602system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081001 # miss rate for ReadReq accesses 603system.cpu.dcache.ReadReq_miss_rate::total 0.081001 # miss rate for ReadReq accesses | 600system.cpu.dcache.demand_accesses::cpu.data 2605 # number of demand (read+write) accesses 601system.cpu.dcache.demand_accesses::total 2605 # number of demand (read+write) accesses 602system.cpu.dcache.overall_accesses::cpu.data 2605 # number of overall (read+write) accesses 603system.cpu.dcache.overall_accesses::total 2605 # number of overall (read+write) accesses 604system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080240 # miss rate for ReadReq accesses 605system.cpu.dcache.ReadReq_miss_rate::total 0.080240 # miss rate for ReadReq accesses |
| 604system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses 605system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses | 606system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses 607system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses |
| 606system.cpu.dcache.demand_miss_rate::cpu.data 0.081867 # miss rate for demand accesses 607system.cpu.dcache.demand_miss_rate::total 0.081867 # miss rate for demand accesses 608system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 # miss rate for overall accesses 609system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses 610system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency 611system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency 612system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency 613system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency 614system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency 615system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency 616system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency 617system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency 618system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked | 608system.cpu.dcache.demand_miss_rate::cpu.data 0.081382 # miss rate for demand accesses 609system.cpu.dcache.demand_miss_rate::total 0.081382 # miss rate for demand accesses 610system.cpu.dcache.overall_miss_rate::cpu.data 0.081382 # miss rate for overall accesses 611system.cpu.dcache.overall_miss_rate::total 0.081382 # miss rate for overall accesses 612system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 82977.611940 # average ReadReq miss latency 613system.cpu.dcache.ReadReq_avg_miss_latency::total 82977.611940 # average ReadReq miss latency 614system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 86682.692308 # average WriteReq miss latency 615system.cpu.dcache.WriteReq_avg_miss_latency::total 86682.692308 # average WriteReq miss latency 616system.cpu.dcache.demand_avg_miss_latency::cpu.data 84340.801887 # average overall miss latency 617system.cpu.dcache.demand_avg_miss_latency::total 84340.801887 # average overall miss latency 618system.cpu.dcache.overall_avg_miss_latency::cpu.data 84340.801887 # average overall miss latency 619system.cpu.dcache.overall_avg_miss_latency::total 84340.801887 # average overall miss latency 620system.cpu.dcache.blocked_cycles::no_mshrs 236 # number of cycles access was blocked |
| 619system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 620system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 621system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 621system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 622system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 623system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 622system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked | 624system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.200000 # average number of cycles each access was blocked |
| 623system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 624system.cpu.dcache.fast_writes 0 # number of fast writes performed 625system.cpu.dcache.cache_copies 0 # number of cache copies performed | 625system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 626system.cpu.dcache.fast_writes 0 # number of fast writes performed 627system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 626system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits 627system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits 628system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits 629system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits 630system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits 631system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits | 628system.cpu.dcache.ReadReq_mshr_hits::cpu.data 70 # number of ReadReq MSHR hits 629system.cpu.dcache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits 630system.cpu.dcache.demand_mshr_hits::cpu.data 70 # number of demand (read+write) MSHR hits 631system.cpu.dcache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits 632system.cpu.dcache.overall_mshr_hits::cpu.data 70 # number of overall MSHR hits 633system.cpu.dcache.overall_mshr_hits::total 70 # number of overall MSHR hits |
| 632system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 633system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses 634system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses 635system.cpu.dcache.WriteReq_mshr_misses::total 78 # number of WriteReq MSHR misses 636system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 637system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 638system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 639system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses | 634system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 635system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses 636system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses 637system.cpu.dcache.WriteReq_mshr_misses::total 78 # number of WriteReq MSHR misses 638system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 639system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 640system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 641system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses |
| 640system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles 641system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles 642system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles 643system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles 644system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles 645system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles 646system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles 647system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles 648system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses 649system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses | 642system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5695500 # number of ReadReq MSHR miss cycles 643system.cpu.dcache.ReadReq_mshr_miss_latency::total 5695500 # number of ReadReq MSHR miss cycles 644system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6612750 # number of WriteReq MSHR miss cycles 645system.cpu.dcache.WriteReq_mshr_miss_latency::total 6612750 # number of WriteReq MSHR miss cycles 646system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12308250 # number of demand (read+write) MSHR miss cycles 647system.cpu.dcache.demand_mshr_miss_latency::total 12308250 # number of demand (read+write) MSHR miss cycles 648system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12308250 # number of overall MSHR miss cycles 649system.cpu.dcache.overall_mshr_miss_latency::total 12308250 # number of overall MSHR miss cycles 650system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038323 # mshr miss rate for ReadReq accesses 651system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038323 # mshr miss rate for ReadReq accesses |
| 650system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses 651system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses | 652system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses 653system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses |
| 652system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses 653system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses 654system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses 655system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses 656system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency 657system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency 658system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency 659system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency 660system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency 661system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency 662system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency 663system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency | 654system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054511 # mshr miss rate for demand accesses 655system.cpu.dcache.demand_mshr_miss_rate::total 0.054511 # mshr miss rate for demand accesses 656system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054511 # mshr miss rate for overall accesses 657system.cpu.dcache.overall_mshr_miss_rate::total 0.054511 # mshr miss rate for overall accesses 658system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88992.187500 # average ReadReq mshr miss latency 659system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88992.187500 # average ReadReq mshr miss latency 660system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84778.846154 # average WriteReq mshr miss latency 661system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84778.846154 # average WriteReq mshr miss latency 662system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86677.816901 # average overall mshr miss latency 663system.cpu.dcache.demand_avg_mshr_miss_latency::total 86677.816901 # average overall mshr miss latency 664system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86677.816901 # average overall mshr miss latency 665system.cpu.dcache.overall_avg_mshr_miss_latency::total 86677.816901 # average overall mshr miss latency |
| 664system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 665system.cpu.icache.tags.replacements 0 # number of replacements | 666system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 667system.cpu.icache.tags.replacements 0 # number of replacements |
| 666system.cpu.icache.tags.tagsinuse 131.539722 # Cycle average of tags in use 667system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks. | 668system.cpu.icache.tags.tagsinuse 131.513084 # Cycle average of tags in use 669system.cpu.icache.tags.total_refs 1796 # Total number of references to valid blocks. |
| 668system.cpu.icache.tags.sampled_refs 276 # Sample count of references to valid blocks. | 670system.cpu.icache.tags.sampled_refs 276 # Sample count of references to valid blocks. |
| 669system.cpu.icache.tags.avg_refs 6.521739 # Average number of references to valid blocks. | 671system.cpu.icache.tags.avg_refs 6.507246 # Average number of references to valid blocks. |
| 670system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 672system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 671system.cpu.icache.tags.occ_blocks::cpu.inst 131.539722 # Average occupied blocks per requestor 672system.cpu.icache.tags.occ_percent::cpu.inst 0.064228 # Average percentage of cache occupancy 673system.cpu.icache.tags.occ_percent::total 0.064228 # Average percentage of cache occupancy | 673system.cpu.icache.tags.occ_blocks::cpu.inst 131.513084 # Average occupied blocks per requestor 674system.cpu.icache.tags.occ_percent::cpu.inst 0.064215 # Average percentage of cache occupancy 675system.cpu.icache.tags.occ_percent::total 0.064215 # Average percentage of cache occupancy |
| 674system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id | 676system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id |
| 675system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id 676system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id | 677system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id 678system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id |
| 677system.cpu.icache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id | 679system.cpu.icache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id |
| 678system.cpu.icache.tags.tag_accesses 4612 # Number of tag accesses 679system.cpu.icache.tags.data_accesses 4612 # Number of data accesses 680system.cpu.icache.ReadReq_hits::cpu.inst 1800 # number of ReadReq hits 681system.cpu.icache.ReadReq_hits::total 1800 # number of ReadReq hits 682system.cpu.icache.demand_hits::cpu.inst 1800 # number of demand (read+write) hits 683system.cpu.icache.demand_hits::total 1800 # number of demand (read+write) hits 684system.cpu.icache.overall_hits::cpu.inst 1800 # number of overall hits 685system.cpu.icache.overall_hits::total 1800 # number of overall hits | 680system.cpu.icache.tags.tag_accesses 4604 # Number of tag accesses 681system.cpu.icache.tags.data_accesses 4604 # Number of data accesses 682system.cpu.icache.ReadReq_hits::cpu.inst 1796 # number of ReadReq hits 683system.cpu.icache.ReadReq_hits::total 1796 # number of ReadReq hits 684system.cpu.icache.demand_hits::cpu.inst 1796 # number of demand (read+write) hits 685system.cpu.icache.demand_hits::total 1796 # number of demand (read+write) hits 686system.cpu.icache.overall_hits::cpu.inst 1796 # number of overall hits 687system.cpu.icache.overall_hits::total 1796 # number of overall hits |
| 686system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses 687system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses 688system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses 689system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses 690system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses 691system.cpu.icache.overall_misses::total 368 # number of overall misses | 688system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses 689system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses 690system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses 691system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses 692system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses 693system.cpu.icache.overall_misses::total 368 # number of overall misses |
| 692system.cpu.icache.ReadReq_miss_latency::cpu.inst 25557250 # number of ReadReq miss cycles 693system.cpu.icache.ReadReq_miss_latency::total 25557250 # number of ReadReq miss cycles 694system.cpu.icache.demand_miss_latency::cpu.inst 25557250 # number of demand (read+write) miss cycles 695system.cpu.icache.demand_miss_latency::total 25557250 # number of demand (read+write) miss cycles 696system.cpu.icache.overall_miss_latency::cpu.inst 25557250 # number of overall miss cycles 697system.cpu.icache.overall_miss_latency::total 25557250 # number of overall miss cycles 698system.cpu.icache.ReadReq_accesses::cpu.inst 2168 # number of ReadReq accesses(hits+misses) 699system.cpu.icache.ReadReq_accesses::total 2168 # number of ReadReq accesses(hits+misses) 700system.cpu.icache.demand_accesses::cpu.inst 2168 # number of demand (read+write) accesses 701system.cpu.icache.demand_accesses::total 2168 # number of demand (read+write) accesses 702system.cpu.icache.overall_accesses::cpu.inst 2168 # number of overall (read+write) accesses 703system.cpu.icache.overall_accesses::total 2168 # number of overall (read+write) accesses 704system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169742 # miss rate for ReadReq accesses 705system.cpu.icache.ReadReq_miss_rate::total 0.169742 # miss rate for ReadReq accesses 706system.cpu.icache.demand_miss_rate::cpu.inst 0.169742 # miss rate for demand accesses 707system.cpu.icache.demand_miss_rate::total 0.169742 # miss rate for demand accesses 708system.cpu.icache.overall_miss_rate::cpu.inst 0.169742 # miss rate for overall accesses 709system.cpu.icache.overall_miss_rate::total 0.169742 # miss rate for overall accesses 710system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69449.048913 # average ReadReq miss latency 711system.cpu.icache.ReadReq_avg_miss_latency::total 69449.048913 # average ReadReq miss latency 712system.cpu.icache.demand_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency 713system.cpu.icache.demand_avg_miss_latency::total 69449.048913 # average overall miss latency 714system.cpu.icache.overall_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency 715system.cpu.icache.overall_avg_miss_latency::total 69449.048913 # average overall miss latency | 694system.cpu.icache.ReadReq_miss_latency::cpu.inst 28645750 # number of ReadReq miss cycles 695system.cpu.icache.ReadReq_miss_latency::total 28645750 # number of ReadReq miss cycles 696system.cpu.icache.demand_miss_latency::cpu.inst 28645750 # number of demand (read+write) miss cycles 697system.cpu.icache.demand_miss_latency::total 28645750 # number of demand (read+write) miss cycles 698system.cpu.icache.overall_miss_latency::cpu.inst 28645750 # number of overall miss cycles 699system.cpu.icache.overall_miss_latency::total 28645750 # number of overall miss cycles 700system.cpu.icache.ReadReq_accesses::cpu.inst 2164 # number of ReadReq accesses(hits+misses) 701system.cpu.icache.ReadReq_accesses::total 2164 # number of ReadReq accesses(hits+misses) 702system.cpu.icache.demand_accesses::cpu.inst 2164 # number of demand (read+write) accesses 703system.cpu.icache.demand_accesses::total 2164 # number of demand (read+write) accesses 704system.cpu.icache.overall_accesses::cpu.inst 2164 # number of overall (read+write) accesses 705system.cpu.icache.overall_accesses::total 2164 # number of overall (read+write) accesses 706system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.170055 # miss rate for ReadReq accesses 707system.cpu.icache.ReadReq_miss_rate::total 0.170055 # miss rate for ReadReq accesses 708system.cpu.icache.demand_miss_rate::cpu.inst 0.170055 # miss rate for demand accesses 709system.cpu.icache.demand_miss_rate::total 0.170055 # miss rate for demand accesses 710system.cpu.icache.overall_miss_rate::cpu.inst 0.170055 # miss rate for overall accesses 711system.cpu.icache.overall_miss_rate::total 0.170055 # miss rate for overall accesses 712system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77841.711957 # average ReadReq miss latency 713system.cpu.icache.ReadReq_avg_miss_latency::total 77841.711957 # average ReadReq miss latency 714system.cpu.icache.demand_avg_miss_latency::cpu.inst 77841.711957 # average overall miss latency 715system.cpu.icache.demand_avg_miss_latency::total 77841.711957 # average overall miss latency 716system.cpu.icache.overall_avg_miss_latency::cpu.inst 77841.711957 # average overall miss latency 717system.cpu.icache.overall_avg_miss_latency::total 77841.711957 # average overall miss latency |
| 716system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 717system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 718system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 719system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 720system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 721system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 722system.cpu.icache.fast_writes 0 # number of fast writes performed 723system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 728system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits 729system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits 730system.cpu.icache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses 731system.cpu.icache.ReadReq_mshr_misses::total 276 # number of ReadReq MSHR misses 732system.cpu.icache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 733system.cpu.icache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses 734system.cpu.icache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 735system.cpu.icache.overall_mshr_misses::total 276 # number of overall MSHR misses | 718system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 719system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 720system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 721system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 722system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 723system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 724system.cpu.icache.fast_writes 0 # number of fast writes performed 725system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 730system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits 731system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits 732system.cpu.icache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses 733system.cpu.icache.ReadReq_mshr_misses::total 276 # number of ReadReq MSHR misses 734system.cpu.icache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 735system.cpu.icache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses 736system.cpu.icache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 737system.cpu.icache.overall_mshr_misses::total 276 # number of overall MSHR misses |
| 736system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20059000 # number of ReadReq MSHR miss cycles 737system.cpu.icache.ReadReq_mshr_miss_latency::total 20059000 # number of ReadReq MSHR miss cycles 738system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20059000 # number of demand (read+write) MSHR miss cycles 739system.cpu.icache.demand_mshr_miss_latency::total 20059000 # number of demand (read+write) MSHR miss cycles 740system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20059000 # number of overall MSHR miss cycles 741system.cpu.icache.overall_mshr_miss_latency::total 20059000 # number of overall MSHR miss cycles 742system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for ReadReq accesses 743system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127306 # mshr miss rate for ReadReq accesses 744system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for demand accesses 745system.cpu.icache.demand_mshr_miss_rate::total 0.127306 # mshr miss rate for demand accesses 746system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for overall accesses 747system.cpu.icache.overall_mshr_miss_rate::total 0.127306 # mshr miss rate for overall accesses 748system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72677.536232 # average ReadReq mshr miss latency 749system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72677.536232 # average ReadReq mshr miss latency 750system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency 751system.cpu.icache.demand_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency 752system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency 753system.cpu.icache.overall_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency | 738system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21933250 # number of ReadReq MSHR miss cycles 739system.cpu.icache.ReadReq_mshr_miss_latency::total 21933250 # number of ReadReq MSHR miss cycles 740system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21933250 # number of demand (read+write) MSHR miss cycles 741system.cpu.icache.demand_mshr_miss_latency::total 21933250 # number of demand (read+write) MSHR miss cycles 742system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21933250 # number of overall MSHR miss cycles 743system.cpu.icache.overall_mshr_miss_latency::total 21933250 # number of overall MSHR miss cycles 744system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for ReadReq accesses 745system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127542 # mshr miss rate for ReadReq accesses 746system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for demand accesses 747system.cpu.icache.demand_mshr_miss_rate::total 0.127542 # mshr miss rate for demand accesses 748system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for overall accesses 749system.cpu.icache.overall_mshr_miss_rate::total 0.127542 # mshr miss rate for overall accesses 750system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79468.297101 # average ReadReq mshr miss latency 751system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79468.297101 # average ReadReq mshr miss latency 752system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79468.297101 # average overall mshr miss latency 753system.cpu.icache.demand_avg_mshr_miss_latency::total 79468.297101 # average overall mshr miss latency 754system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79468.297101 # average overall mshr miss latency 755system.cpu.icache.overall_avg_mshr_miss_latency::total 79468.297101 # average overall mshr miss latency |
| 754system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 755system.cpu.l2cache.tags.replacements 0 # number of replacements | 756system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 757system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 756system.cpu.l2cache.tags.tagsinuse 163.220102 # Cycle average of tags in use | 758system.cpu.l2cache.tags.tagsinuse 163.168393 # Cycle average of tags in use |
| 757system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 758system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. 759system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. 760system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 759system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 760system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. 761system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. 762system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 761system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.613484 # Average occupied blocks per requestor 762system.cpu.l2cache.tags.occ_blocks::cpu.data 31.606618 # Average occupied blocks per requestor 763system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004017 # Average percentage of cache occupancy 764system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy 765system.cpu.l2cache.tags.occ_percent::total 0.004981 # Average percentage of cache occupancy | 763system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.574096 # Average occupied blocks per requestor 764system.cpu.l2cache.tags.occ_blocks::cpu.data 31.594298 # Average occupied blocks per requestor 765system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004015 # Average percentage of cache occupancy 766system.cpu.l2cache.tags.occ_percent::cpu.data 0.000964 # Average percentage of cache occupancy 767system.cpu.l2cache.tags.occ_percent::total 0.004980 # Average percentage of cache occupancy |
| 766system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id | 768system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id |
| 767system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id 768system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id | 769system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id 770system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id |
| 769system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010315 # Percentage of cache occupancy per task id 770system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses 771system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses 772system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 773system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 774system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 775system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 776system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits --- 4 unchanged lines hidden (view full) --- 781system.cpu.l2cache.ReadExReq_misses::cpu.data 78 # number of ReadExReq misses 782system.cpu.l2cache.ReadExReq_misses::total 78 # number of ReadExReq misses 783system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses 784system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 785system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses 786system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses 787system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 788system.cpu.l2cache.overall_misses::total 417 # number of overall misses | 771system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010315 # Percentage of cache occupancy per task id 772system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses 773system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses 774system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 775system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 776system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 777system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 778system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits --- 4 unchanged lines hidden (view full) --- 783system.cpu.l2cache.ReadExReq_misses::cpu.data 78 # number of ReadExReq misses 784system.cpu.l2cache.ReadExReq_misses::total 78 # number of ReadExReq misses 785system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses 786system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 787system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses 788system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses 789system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 790system.cpu.l2cache.overall_misses::total 417 # number of overall misses |
| 789system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19772500 # number of ReadReq miss cycles 790system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4946500 # number of ReadReq miss cycles 791system.cpu.l2cache.ReadReq_miss_latency::total 24719000 # number of ReadReq miss cycles 792system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5510000 # number of ReadExReq miss cycles 793system.cpu.l2cache.ReadExReq_miss_latency::total 5510000 # number of ReadExReq miss cycles 794system.cpu.l2cache.demand_miss_latency::cpu.inst 19772500 # number of demand (read+write) miss cycles 795system.cpu.l2cache.demand_miss_latency::cpu.data 10456500 # number of demand (read+write) miss cycles 796system.cpu.l2cache.demand_miss_latency::total 30229000 # number of demand (read+write) miss cycles 797system.cpu.l2cache.overall_miss_latency::cpu.inst 19772500 # number of overall miss cycles 798system.cpu.l2cache.overall_miss_latency::cpu.data 10456500 # number of overall miss cycles 799system.cpu.l2cache.overall_miss_latency::total 30229000 # number of overall miss cycles | 791system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21646250 # number of ReadReq miss cycles 792system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5632500 # number of ReadReq miss cycles 793system.cpu.l2cache.ReadReq_miss_latency::total 27278750 # number of ReadReq miss cycles 794system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6534750 # number of ReadExReq miss cycles 795system.cpu.l2cache.ReadExReq_miss_latency::total 6534750 # number of ReadExReq miss cycles 796system.cpu.l2cache.demand_miss_latency::cpu.inst 21646250 # number of demand (read+write) miss cycles 797system.cpu.l2cache.demand_miss_latency::cpu.data 12167250 # number of demand (read+write) miss cycles 798system.cpu.l2cache.demand_miss_latency::total 33813500 # number of demand (read+write) miss cycles 799system.cpu.l2cache.overall_miss_latency::cpu.inst 21646250 # number of overall miss cycles 800system.cpu.l2cache.overall_miss_latency::cpu.data 12167250 # number of overall miss cycles 801system.cpu.l2cache.overall_miss_latency::total 33813500 # number of overall miss cycles |
| 800system.cpu.l2cache.ReadReq_accesses::cpu.inst 276 # number of ReadReq accesses(hits+misses) 801system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) 802system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) 803system.cpu.l2cache.ReadExReq_accesses::cpu.data 78 # number of ReadExReq accesses(hits+misses) 804system.cpu.l2cache.ReadExReq_accesses::total 78 # number of ReadExReq accesses(hits+misses) 805system.cpu.l2cache.demand_accesses::cpu.inst 276 # number of demand (read+write) accesses 806system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 807system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 814system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 815system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 816system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996377 # miss rate for demand accesses 817system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 818system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses 819system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996377 # miss rate for overall accesses 820system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 821system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses | 802system.cpu.l2cache.ReadReq_accesses::cpu.inst 276 # number of ReadReq accesses(hits+misses) 803system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) 804system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) 805system.cpu.l2cache.ReadExReq_accesses::cpu.data 78 # number of ReadExReq accesses(hits+misses) 806system.cpu.l2cache.ReadExReq_accesses::total 78 # number of ReadExReq accesses(hits+misses) 807system.cpu.l2cache.demand_accesses::cpu.inst 276 # number of demand (read+write) accesses 808system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 809system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 816system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 817system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 818system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996377 # miss rate for demand accesses 819system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 820system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses 821system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996377 # miss rate for overall accesses 822system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 823system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses |
| 822system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71900 # average ReadReq miss latency 823system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77289.062500 # average ReadReq miss latency 824system.cpu.l2cache.ReadReq_avg_miss_latency::total 72917.404130 # average ReadReq miss latency 825system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70641.025641 # average ReadExReq miss latency 826system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70641.025641 # average ReadExReq miss latency 827system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71900 # average overall miss latency 828system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency 829system.cpu.l2cache.demand_avg_miss_latency::total 72491.606715 # average overall miss latency 830system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71900 # average overall miss latency 831system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency 832system.cpu.l2cache.overall_avg_miss_latency::total 72491.606715 # average overall miss latency | 824system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78713.636364 # average ReadReq miss latency 825system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88007.812500 # average ReadReq miss latency 826system.cpu.l2cache.ReadReq_avg_miss_latency::total 80468.289086 # average ReadReq miss latency 827system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83778.846154 # average ReadExReq miss latency 828system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83778.846154 # average ReadExReq miss latency 829system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78713.636364 # average overall miss latency 830system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85684.859155 # average overall miss latency 831system.cpu.l2cache.demand_avg_miss_latency::total 81087.529976 # average overall miss latency 832system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78713.636364 # average overall miss latency 833system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85684.859155 # average overall miss latency 834system.cpu.l2cache.overall_avg_miss_latency::total 81087.529976 # average overall miss latency |
| 833system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 834system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 835system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 836system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 837system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 838system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 839system.cpu.l2cache.fast_writes 0 # number of fast writes performed 840system.cpu.l2cache.cache_copies 0 # number of cache copies performed 841system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses 842system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 843system.cpu.l2cache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses 844system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 78 # number of ReadExReq MSHR misses 845system.cpu.l2cache.ReadExReq_mshr_misses::total 78 # number of ReadExReq MSHR misses 846system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses 847system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 848system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses 849system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses 850system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 851system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses | 835system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 836system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 837system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 838system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 839system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 840system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 841system.cpu.l2cache.fast_writes 0 # number of fast writes performed 842system.cpu.l2cache.cache_copies 0 # number of cache copies performed 843system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses 844system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 845system.cpu.l2cache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses 846system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 78 # number of ReadExReq MSHR misses 847system.cpu.l2cache.ReadExReq_mshr_misses::total 78 # number of ReadExReq MSHR misses 848system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses 849system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 850system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses 851system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses 852system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 853system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses |
| 852system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16317000 # number of ReadReq MSHR miss cycles 853system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4156000 # number of ReadReq MSHR miss cycles 854system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20473000 # number of ReadReq MSHR miss cycles 855system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4539500 # number of ReadExReq MSHR miss cycles 856system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539500 # number of ReadExReq MSHR miss cycles 857system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16317000 # number of demand (read+write) MSHR miss cycles 858system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8695500 # number of demand (read+write) MSHR miss cycles 859system.cpu.l2cache.demand_mshr_miss_latency::total 25012500 # number of demand (read+write) MSHR miss cycles 860system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16317000 # number of overall MSHR miss cycles 861system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695500 # number of overall MSHR miss cycles 862system.cpu.l2cache.overall_mshr_miss_latency::total 25012500 # number of overall MSHR miss cycles | 854system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18201750 # number of ReadReq MSHR miss cycles 855system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4837000 # number of ReadReq MSHR miss cycles 856system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23038750 # number of ReadReq MSHR miss cycles 857system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5555250 # number of ReadExReq MSHR miss cycles 858system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5555250 # number of ReadExReq MSHR miss cycles 859system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18201750 # number of demand (read+write) MSHR miss cycles 860system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10392250 # number of demand (read+write) MSHR miss cycles 861system.cpu.l2cache.demand_mshr_miss_latency::total 28594000 # number of demand (read+write) MSHR miss cycles 862system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18201750 # number of overall MSHR miss cycles 863system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10392250 # number of overall MSHR miss cycles 864system.cpu.l2cache.overall_mshr_miss_latency::total 28594000 # number of overall MSHR miss cycles |
| 863system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadReq accesses 864system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 865system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997059 # mshr miss rate for ReadReq accesses 866system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 867system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 868system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for demand accesses 869system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 870system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses 871system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for overall accesses 872system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 873system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses | 865system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadReq accesses 866system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 867system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997059 # mshr miss rate for ReadReq accesses 868system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 869system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 870system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for demand accesses 871system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 872system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses 873system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for overall accesses 874system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 875system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses |
| 874system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59334.545455 # average ReadReq mshr miss latency 875system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64937.500000 # average ReadReq mshr miss latency 876system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60392.330383 # average ReadReq mshr miss latency 877system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58198.717949 # average ReadExReq mshr miss latency 878system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58198.717949 # average ReadExReq mshr miss latency 879system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency 880system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency 881system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency 882system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency 883system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency 884system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency | 876system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66188.181818 # average ReadReq mshr miss latency 877system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75578.125000 # average ReadReq mshr miss latency 878system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67960.914454 # average ReadReq mshr miss latency 879system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71221.153846 # average ReadExReq mshr miss latency 880system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71221.153846 # average ReadExReq mshr miss latency 881system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.181818 # average overall mshr miss latency 882system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73184.859155 # average overall mshr miss latency 883system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68570.743405 # average overall mshr miss latency 884system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.181818 # average overall mshr miss latency 885system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73184.859155 # average overall mshr miss latency 886system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68570.743405 # average overall mshr miss latency |
| 885system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 886system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution 887system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 888system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution 889system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution 890system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) 891system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) 892system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) --- 10 unchanged lines hidden (view full) --- 903system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 904system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram 905system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 906system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 907system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 908system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 909system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram 910system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) | 887system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 888system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution 889system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 890system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution 891system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution 892system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) 893system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) 894system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) --- 10 unchanged lines hidden (view full) --- 905system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 906system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram 907system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 908system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 909system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 910system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 911system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram 912system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) |
| 911system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 912system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks) 913system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 914system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks) 915system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) | 913system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 914system.cpu.toL2Bus.respLayer0.occupancy 471250 # Layer occupancy (ticks) 915system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) 916system.cpu.toL2Bus.respLayer1.occupancy 239250 # Layer occupancy (ticks) 917system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) |
| 916system.membus.trans_dist::ReadReq 339 # Transaction distribution 917system.membus.trans_dist::ReadResp 338 # Transaction distribution 918system.membus.trans_dist::ReadExReq 78 # Transaction distribution 919system.membus.trans_dist::ReadExResp 78 # Transaction distribution 920system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) 921system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) 922system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) 923system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 929system.membus.snoop_fanout::stdev 0 # Request fanout histogram 930system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 931system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram 932system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 933system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 934system.membus.snoop_fanout::min_value 0 # Request fanout histogram 935system.membus.snoop_fanout::max_value 0 # Request fanout histogram 936system.membus.snoop_fanout::total 417 # Request fanout histogram | 918system.membus.trans_dist::ReadReq 339 # Transaction distribution 919system.membus.trans_dist::ReadResp 338 # Transaction distribution 920system.membus.trans_dist::ReadExReq 78 # Transaction distribution 921system.membus.trans_dist::ReadExResp 78 # Transaction distribution 922system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) 923system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) 924system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) 925system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 931system.membus.snoop_fanout::stdev 0 # Request fanout histogram 932system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 933system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram 934system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 935system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 936system.membus.snoop_fanout::min_value 0 # Request fanout histogram 937system.membus.snoop_fanout::max_value 0 # Request fanout histogram 938system.membus.snoop_fanout::total 417 # Request fanout histogram |
| 937system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) 938system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) 939system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) 940system.membus.respLayer1.utilization 19.8 # Layer utilization (%) | 939system.membus.reqLayer0.occupancy 504000 # Layer occupancy (ticks) 940system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) 941system.membus.respLayer1.occupancy 2222500 # Layer occupancy (ticks) 942system.membus.respLayer1.utilization 10.5 # Layer utilization (%) |
| 941 942---------- End Simulation Statistics ---------- | 943 944---------- End Simulation Statistics ---------- |