| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated |
| 4sim_ticks 19744000 # Number of ticks simulated 5final_tick 19744000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 19678000 # Number of ticks simulated 5final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 27433 # Simulator instruction rate (inst/s) 8host_op_rate 49695 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 100653274 # Simulator tick rate (ticks/s) 10host_mem_usage 249652 # Number of bytes of host memory used 11host_seconds 0.20 # Real time elapsed on the host | 7host_inst_rate 48979 # Simulator instruction rate (inst/s) 8host_op_rate 88725 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 179100946 # Simulator tick rate (ticks/s) 10host_mem_usage 305852 # Number of bytes of host memory used 11host_seconds 0.11 # Real time elapsed on the host |
| 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory | 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 891410049 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 457050243 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1348460292 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 891410049 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 891410049 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 891410049 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 457050243 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1348460292 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 894399837 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 458583189 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1352983027 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 894399837 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 894399837 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 894399837 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 458583189 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1352983027 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 417 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 417 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 19695500 # Total gap between requests | 78system.physmem.totGap 19629500 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 417 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 417 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see |
| 96system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 79 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 242.285714 # Bytes accessed per row activation | 96system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 79 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 242.285714 # Bytes accessed per row activation |
| 191system.physmem.bytesPerActivate::gmean 159.132678 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 257.193096 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 35 35.71% 35.71% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 32 32.65% 68.37% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 12 12.24% 80.61% # Bytes accessed per row activation | 191system.physmem.bytesPerActivate::gmean 158.475642 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 257.521253 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 36 36.73% 36.73% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 30 30.61% 67.35% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 13 13.27% 80.61% # Bytes accessed per row activation |
| 196system.physmem.bytesPerActivate::384-511 6 6.12% 86.73% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::640-767 6 6.12% 92.86% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::896-1023 4 4.08% 96.94% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1024-1151 3 3.06% 100.00% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation | 196system.physmem.bytesPerActivate::384-511 6 6.12% 86.73% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::640-767 6 6.12% 92.86% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::896-1023 4 4.08% 96.94% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1024-1151 3 3.06% 100.00% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation |
| 201system.physmem.totQLat 4076000 # Total ticks spent queuing 202system.physmem.totMemAccLat 11894750 # Total ticks spent from burst creation until serviced by the DRAM | 201system.physmem.totQLat 4347000 # Total ticks spent queuing 202system.physmem.totMemAccLat 12165750 # Total ticks spent from burst creation until serviced by the DRAM |
| 203system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers | 203system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers |
| 204system.physmem.avgQLat 9774.58 # Average queueing delay per DRAM burst | 204system.physmem.avgQLat 10424.46 # Average queueing delay per DRAM burst |
| 205system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 205system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 206system.physmem.avgMemAccLat 28524.58 # Average memory access latency per DRAM burst 207system.physmem.avgRdBW 1351.70 # Average DRAM read bandwidth in MiByte/s | 206system.physmem.avgMemAccLat 29174.46 # Average memory access latency per DRAM burst 207system.physmem.avgRdBW 1356.24 # Average DRAM read bandwidth in MiByte/s |
| 208system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 208system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 209system.physmem.avgRdBWSys 1351.70 # Average system read bandwidth in MiByte/s | 209system.physmem.avgRdBWSys 1356.24 # Average system read bandwidth in MiByte/s |
| 210system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 211system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 210system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 211system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 212system.physmem.busUtil 10.56 # Data bus utilization in percentage 213system.physmem.busUtilRead 10.56 # Data bus utilization in percentage for reads | 212system.physmem.busUtil 10.60 # Data bus utilization in percentage 213system.physmem.busUtilRead 10.60 # Data bus utilization in percentage for reads |
| 214system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 214system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 215system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing | 215system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing |
| 216system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 217system.physmem.readRowHits 309 # Number of row buffer hits during reads 218system.physmem.writeRowHits 0 # Number of row buffer hits during writes 219system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads 220system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 216system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 217system.physmem.readRowHits 309 # Number of row buffer hits during reads 218system.physmem.writeRowHits 0 # Number of row buffer hits during writes 219system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads 220system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 221system.physmem.avgGap 47231.41 # Average gap between requests | 221system.physmem.avgGap 47073.14 # Average gap between requests |
| 222system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined 223system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 224system.physmem.memoryStateTime::REF 520000 # Time in different power states 225system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 222system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined 223system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 224system.physmem.memoryStateTime::REF 520000 # Time in different power states 225system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 226system.physmem.memoryStateTime::ACT 15315250 # Time in different power states | 226system.physmem.memoryStateTime::ACT 15318250 # Time in different power states |
| 227system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 227system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 228system.membus.throughput 1348460292 # Throughput (bytes/s) | |
| 229system.membus.trans_dist::ReadReq 339 # Transaction distribution 230system.membus.trans_dist::ReadResp 338 # Transaction distribution 231system.membus.trans_dist::ReadExReq 78 # Transaction distribution 232system.membus.trans_dist::ReadExResp 78 # Transaction distribution 233system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) 234system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) 235system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) | 228system.membus.trans_dist::ReadReq 339 # Transaction distribution 229system.membus.trans_dist::ReadResp 338 # Transaction distribution 230system.membus.trans_dist::ReadExReq 78 # Transaction distribution 231system.membus.trans_dist::ReadExResp 78 # Transaction distribution 232system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) 233system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) 234system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) |
| 236system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) 239system.membus.data_through_bus 26624 # Total data (bytes) 240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 235system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) 236system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) 237system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) 238system.membus.snoops 0 # Total snoops (count) 239system.membus.snoop_fanout::samples 417 # Request fanout histogram 240system.membus.snoop_fanout::mean 0 # Request fanout histogram 241system.membus.snoop_fanout::stdev 0 # Request fanout histogram 242system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 243system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram 244system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 245system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 246system.membus.snoop_fanout::min_value 0 # Request fanout histogram 247system.membus.snoop_fanout::max_value 0 # Request fanout histogram 248system.membus.snoop_fanout::total 417 # Request fanout histogram |
| 241system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) 242system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) 243system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) | 249system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) 250system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) 251system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) |
| 244system.membus.respLayer1.utilization 19.7 # Layer utilization (%) | 252system.membus.respLayer1.utilization 19.8 # Layer utilization (%) |
| 245system.cpu_clk_domain.clock 500 # Clock period in ticks 246system.cpu.branchPred.lookups 3423 # Number of BP lookups 247system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted 248system.cpu.branchPred.condIncorrect 535 # Number of conditional branches incorrect 249system.cpu.branchPred.BTBLookups 2544 # Number of BTB lookups 250system.cpu.branchPred.BTBHits 864 # Number of BTB hits 251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 252system.cpu.branchPred.BTBHitPct 33.962264 # BTB Hit Percentage 253system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target. 254system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. 255system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 256system.cpu.workload.num_syscalls 11 # Number of system calls | 253system.cpu_clk_domain.clock 500 # Clock period in ticks 254system.cpu.branchPred.lookups 3423 # Number of BP lookups 255system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted 256system.cpu.branchPred.condIncorrect 535 # Number of conditional branches incorrect 257system.cpu.branchPred.BTBLookups 2544 # Number of BTB lookups 258system.cpu.branchPred.BTBHits 864 # Number of BTB hits 259system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 260system.cpu.branchPred.BTBHitPct 33.962264 # BTB Hit Percentage 261system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target. 262system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. 263system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 264system.cpu.workload.num_syscalls 11 # Number of system calls |
| 257system.cpu.numCycles 39489 # number of cpu cycles simulated | 265system.cpu.numCycles 39357 # number of cpu cycles simulated |
| 258system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 259system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 260system.cpu.fetch.icacheStallCycles 10915 # Number of cycles fetch is stalled on an Icache miss 261system.cpu.fetch.Insts 15528 # Number of instructions fetch has processed 262system.cpu.fetch.Branches 3423 # Number of branches that fetch encountered 263system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken 264system.cpu.fetch.Cycles 9222 # Number of cycles fetch has run and was not squashing or blocked 265system.cpu.fetch.SquashCycles 1202 # Number of cycles fetch has spent squashing --- 14 unchanged lines hidden (view full) --- 280system.cpu.fetch.rateDist::5 227 1.04% 85.52% # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::6 339 1.55% 87.06% # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::7 205 0.94% 88.00% # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::8 2627 12.00% 100.00% # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::total 21893 # Number of instructions fetched each cycle (Total) | 266system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 267system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 268system.cpu.fetch.icacheStallCycles 10915 # Number of cycles fetch is stalled on an Icache miss 269system.cpu.fetch.Insts 15528 # Number of instructions fetch has processed 270system.cpu.fetch.Branches 3423 # Number of branches that fetch encountered 271system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken 272system.cpu.fetch.Cycles 9222 # Number of cycles fetch has run and was not squashing or blocked 273system.cpu.fetch.SquashCycles 1202 # Number of cycles fetch has spent squashing --- 14 unchanged lines hidden (view full) --- 288system.cpu.fetch.rateDist::5 227 1.04% 85.52% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::6 339 1.55% 87.06% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::7 205 0.94% 88.00% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::8 2627 12.00% 100.00% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::total 21893 # Number of instructions fetched each cycle (Total) |
| 288system.cpu.fetch.branchRate 0.086682 # Number of branch fetches per cycle 289system.cpu.fetch.rate 0.393223 # Number of inst fetches per cycle | 296system.cpu.fetch.branchRate 0.086973 # Number of branch fetches per cycle 297system.cpu.fetch.rate 0.394542 # Number of inst fetches per cycle |
| 290system.cpu.decode.IdleCycles 10660 # Number of cycles decode is idle 291system.cpu.decode.BlockedCycles 6840 # Number of cycles decode is blocked 292system.cpu.decode.RunCycles 3336 # Number of cycles decode is running 293system.cpu.decode.UnblockCycles 456 # Number of cycles decode is unblocking 294system.cpu.decode.SquashCycles 601 # Number of cycles decode is squashing 295system.cpu.decode.DecodedInsts 25755 # Number of instructions handled by decode 296system.cpu.rename.SquashCycles 601 # Number of cycles rename is squashing 297system.cpu.rename.IdleCycles 10929 # Number of cycles rename is idle --- 106 unchanged lines hidden (view full) --- 404system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.44% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.44% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.44% # Type of FU issued 407system.cpu.iq.FU_type_0::MemRead 2122 11.86% 92.29% # Type of FU issued 408system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Type of FU issued 409system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 410system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 411system.cpu.iq.FU_type_0::total 17897 # Type of FU issued | 298system.cpu.decode.IdleCycles 10660 # Number of cycles decode is idle 299system.cpu.decode.BlockedCycles 6840 # Number of cycles decode is blocked 300system.cpu.decode.RunCycles 3336 # Number of cycles decode is running 301system.cpu.decode.UnblockCycles 456 # Number of cycles decode is unblocking 302system.cpu.decode.SquashCycles 601 # Number of cycles decode is squashing 303system.cpu.decode.DecodedInsts 25755 # Number of instructions handled by decode 304system.cpu.rename.SquashCycles 601 # Number of cycles rename is squashing 305system.cpu.rename.IdleCycles 10929 # Number of cycles rename is idle --- 106 unchanged lines hidden (view full) --- 412system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.44% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.44% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.44% # Type of FU issued 415system.cpu.iq.FU_type_0::MemRead 2122 11.86% 92.29% # Type of FU issued 416system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Type of FU issued 417system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 418system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 419system.cpu.iq.FU_type_0::total 17897 # Type of FU issued |
| 412system.cpu.iq.rate 0.453215 # Inst issue rate | 420system.cpu.iq.rate 0.454735 # Inst issue rate |
| 413system.cpu.iq.fu_busy_cnt 224 # FU busy when requested 414system.cpu.iq.fu_busy_rate 0.012516 # FU busy rate (busy events/executed inst) 415system.cpu.iq.int_inst_queue_reads 57983 # Number of integer instruction queue reads 416system.cpu.iq.int_inst_queue_writes 32531 # Number of integer instruction queue writes 417system.cpu.iq.int_inst_queue_wakeup_accesses 16370 # Number of integer instruction queue wakeup accesses 418system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 419system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 420system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses --- 27 unchanged lines hidden (view full) --- 448system.cpu.iew.iewExecutedInsts 16926 # Number of executed instructions 449system.cpu.iew.iewExecLoadInsts 1969 # Number of load instructions executed 450system.cpu.iew.iewExecSquashedInsts 971 # Number of squashed instructions skipped in execute 451system.cpu.iew.exec_swp 0 # number of swp insts executed 452system.cpu.iew.exec_nop 0 # number of nop insts executed 453system.cpu.iew.exec_refs 3251 # number of memory reference insts executed 454system.cpu.iew.exec_branches 1662 # Number of branches executed 455system.cpu.iew.exec_stores 1282 # Number of stores executed | 421system.cpu.iq.fu_busy_cnt 224 # FU busy when requested 422system.cpu.iq.fu_busy_rate 0.012516 # FU busy rate (busy events/executed inst) 423system.cpu.iq.int_inst_queue_reads 57983 # Number of integer instruction queue reads 424system.cpu.iq.int_inst_queue_writes 32531 # Number of integer instruction queue writes 425system.cpu.iq.int_inst_queue_wakeup_accesses 16370 # Number of integer instruction queue wakeup accesses 426system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 427system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 428system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses --- 27 unchanged lines hidden (view full) --- 456system.cpu.iew.iewExecutedInsts 16926 # Number of executed instructions 457system.cpu.iew.iewExecLoadInsts 1969 # Number of load instructions executed 458system.cpu.iew.iewExecSquashedInsts 971 # Number of squashed instructions skipped in execute 459system.cpu.iew.exec_swp 0 # number of swp insts executed 460system.cpu.iew.exec_nop 0 # number of nop insts executed 461system.cpu.iew.exec_refs 3251 # number of memory reference insts executed 462system.cpu.iew.exec_branches 1662 # Number of branches executed 463system.cpu.iew.exec_stores 1282 # Number of stores executed |
| 456system.cpu.iew.exec_rate 0.428626 # Inst execution rate | 464system.cpu.iew.exec_rate 0.430063 # Inst execution rate |
| 457system.cpu.iew.wb_sent 16636 # cumulative count of insts sent to commit 458system.cpu.iew.wb_count 16374 # cumulative count of insts written-back 459system.cpu.iew.wb_producers 11006 # num instructions producing a value 460system.cpu.iew.wb_consumers 17135 # num instructions consuming a value 461system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 465system.cpu.iew.wb_sent 16636 # cumulative count of insts sent to commit 466system.cpu.iew.wb_count 16374 # cumulative count of insts written-back 467system.cpu.iew.wb_producers 11006 # num instructions producing a value 468system.cpu.iew.wb_consumers 17135 # num instructions consuming a value 469system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 462system.cpu.iew.wb_rate 0.414647 # insts written-back per cycle | 470system.cpu.iew.wb_rate 0.416038 # insts written-back per cycle |
| 463system.cpu.iew.wb_fanout 0.642311 # average fanout of values written-back 464system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 465system.cpu.commit.commitSquashedInsts 11720 # The number of squashed insts skipped by commit 466system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards 467system.cpu.commit.branchMispredicts 588 # The number of times a branch was mispredicted 468system.cpu.commit.committed_per_cycle::samples 19925 # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::mean 0.489184 # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::stdev 1.394250 # Number of insts commited each cycle --- 56 unchanged lines hidden (view full) --- 527system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 528system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 529system.cpu.commit.op_class_0::total 9747 # Class of committed instruction 530system.cpu.commit.bw_lim_events 260 # number cycles where commit BW limit reached 531system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 532system.cpu.rob.rob_reads 41132 # The number of ROB reads 533system.cpu.rob.rob_writes 44928 # The number of ROB writes 534system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself | 471system.cpu.iew.wb_fanout 0.642311 # average fanout of values written-back 472system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 473system.cpu.commit.commitSquashedInsts 11720 # The number of squashed insts skipped by commit 474system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards 475system.cpu.commit.branchMispredicts 588 # The number of times a branch was mispredicted 476system.cpu.commit.committed_per_cycle::samples 19925 # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::mean 0.489184 # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::stdev 1.394250 # Number of insts commited each cycle --- 56 unchanged lines hidden (view full) --- 535system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 536system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 537system.cpu.commit.op_class_0::total 9747 # Class of committed instruction 538system.cpu.commit.bw_lim_events 260 # number cycles where commit BW limit reached 539system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 540system.cpu.rob.rob_reads 41132 # The number of ROB reads 541system.cpu.rob.rob_writes 44928 # The number of ROB writes 542system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 535system.cpu.idleCycles 17596 # Total number of cycles that the CPU has spent unscheduled due to idling | 543system.cpu.idleCycles 17464 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 536system.cpu.committedInsts 5380 # Number of Instructions Simulated 537system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated | 544system.cpu.committedInsts 5380 # Number of Instructions Simulated 545system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated |
| 538system.cpu.cpi 7.339963 # CPI: Cycles Per Instruction 539system.cpu.cpi_total 7.339963 # CPI: Total CPI of All Threads 540system.cpu.ipc 0.136240 # IPC: Instructions Per Cycle 541system.cpu.ipc_total 0.136240 # IPC: Total IPC of All Threads | 546system.cpu.cpi 7.315428 # CPI: Cycles Per Instruction 547system.cpu.cpi_total 7.315428 # CPI: Total CPI of All Threads 548system.cpu.ipc 0.136697 # IPC: Instructions Per Cycle 549system.cpu.ipc_total 0.136697 # IPC: Total IPC of All Threads |
| 542system.cpu.int_regfile_reads 21340 # number of integer regfile reads 543system.cpu.int_regfile_writes 13120 # number of integer regfile writes 544system.cpu.fp_regfile_reads 4 # number of floating regfile reads 545system.cpu.cc_regfile_reads 8069 # number of cc regfile reads 546system.cpu.cc_regfile_writes 5036 # number of cc regfile writes 547system.cpu.misc_regfile_reads 7491 # number of misc regfile reads 548system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 550system.cpu.int_regfile_reads 21340 # number of integer regfile reads 551system.cpu.int_regfile_writes 13120 # number of integer regfile writes 552system.cpu.fp_regfile_reads 4 # number of floating regfile reads 553system.cpu.cc_regfile_reads 8069 # number of cc regfile reads 554system.cpu.cc_regfile_writes 5036 # number of cc regfile writes 555system.cpu.misc_regfile_reads 7491 # number of misc regfile reads 556system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 549system.cpu.toL2Bus.throughput 1351701783 # Throughput (bytes/s) | |
| 550system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution 551system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 552system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution 553system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution 554system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) 555system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) 556system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) | 557system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution 558system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 559system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution 560system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution 561system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) 562system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) 563system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) |
| 557system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes) 558system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) 559system.cpu.toL2Bus.tot_pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) 560system.cpu.toL2Bus.data_through_bus 26688 # Total data (bytes) 561system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 564system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes) 565system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) 566system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) 567system.cpu.toL2Bus.snoops 0 # Total snoops (count) 568system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram 569system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 570system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 571system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 572system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 573system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 574system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 575system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram 576system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 577system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 578system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 579system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 580system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram |
| 562system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) 563system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) | 581system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) 582system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) |
| 564system.cpu.toL2Bus.respLayer0.occupancy 462750 # Layer occupancy (ticks) 565system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) 566system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks) | 583system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks) 584system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 585system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks) |
| 567system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 568system.cpu.icache.tags.replacements 0 # number of replacements | 586system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 587system.cpu.icache.tags.replacements 0 # number of replacements |
| 569system.cpu.icache.tags.tagsinuse 131.753616 # Cycle average of tags in use | 588system.cpu.icache.tags.tagsinuse 131.539722 # Cycle average of tags in use |
| 570system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks. 571system.cpu.icache.tags.sampled_refs 276 # Sample count of references to valid blocks. 572system.cpu.icache.tags.avg_refs 6.521739 # Average number of references to valid blocks. 573system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 589system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks. 590system.cpu.icache.tags.sampled_refs 276 # Sample count of references to valid blocks. 591system.cpu.icache.tags.avg_refs 6.521739 # Average number of references to valid blocks. 592system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 574system.cpu.icache.tags.occ_blocks::cpu.inst 131.753616 # Average occupied blocks per requestor 575system.cpu.icache.tags.occ_percent::cpu.inst 0.064333 # Average percentage of cache occupancy 576system.cpu.icache.tags.occ_percent::total 0.064333 # Average percentage of cache occupancy | 593system.cpu.icache.tags.occ_blocks::cpu.inst 131.539722 # Average occupied blocks per requestor 594system.cpu.icache.tags.occ_percent::cpu.inst 0.064228 # Average percentage of cache occupancy 595system.cpu.icache.tags.occ_percent::total 0.064228 # Average percentage of cache occupancy |
| 577system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id 578system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id 579system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id 580system.cpu.icache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id 581system.cpu.icache.tags.tag_accesses 4612 # Number of tag accesses 582system.cpu.icache.tags.data_accesses 4612 # Number of data accesses 583system.cpu.icache.ReadReq_hits::cpu.inst 1800 # number of ReadReq hits 584system.cpu.icache.ReadReq_hits::total 1800 # number of ReadReq hits 585system.cpu.icache.demand_hits::cpu.inst 1800 # number of demand (read+write) hits 586system.cpu.icache.demand_hits::total 1800 # number of demand (read+write) hits 587system.cpu.icache.overall_hits::cpu.inst 1800 # number of overall hits 588system.cpu.icache.overall_hits::total 1800 # number of overall hits 589system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses 590system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses 591system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses 592system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses 593system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses 594system.cpu.icache.overall_misses::total 368 # number of overall misses | 596system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id 597system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id 598system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id 599system.cpu.icache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id 600system.cpu.icache.tags.tag_accesses 4612 # Number of tag accesses 601system.cpu.icache.tags.data_accesses 4612 # Number of data accesses 602system.cpu.icache.ReadReq_hits::cpu.inst 1800 # number of ReadReq hits 603system.cpu.icache.ReadReq_hits::total 1800 # number of ReadReq hits 604system.cpu.icache.demand_hits::cpu.inst 1800 # number of demand (read+write) hits 605system.cpu.icache.demand_hits::total 1800 # number of demand (read+write) hits 606system.cpu.icache.overall_hits::cpu.inst 1800 # number of overall hits 607system.cpu.icache.overall_hits::total 1800 # number of overall hits 608system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses 609system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses 610system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses 611system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses 612system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses 613system.cpu.icache.overall_misses::total 368 # number of overall misses |
| 595system.cpu.icache.ReadReq_miss_latency::cpu.inst 25386000 # number of ReadReq miss cycles 596system.cpu.icache.ReadReq_miss_latency::total 25386000 # number of ReadReq miss cycles 597system.cpu.icache.demand_miss_latency::cpu.inst 25386000 # number of demand (read+write) miss cycles 598system.cpu.icache.demand_miss_latency::total 25386000 # number of demand (read+write) miss cycles 599system.cpu.icache.overall_miss_latency::cpu.inst 25386000 # number of overall miss cycles 600system.cpu.icache.overall_miss_latency::total 25386000 # number of overall miss cycles | 614system.cpu.icache.ReadReq_miss_latency::cpu.inst 25557250 # number of ReadReq miss cycles 615system.cpu.icache.ReadReq_miss_latency::total 25557250 # number of ReadReq miss cycles 616system.cpu.icache.demand_miss_latency::cpu.inst 25557250 # number of demand (read+write) miss cycles 617system.cpu.icache.demand_miss_latency::total 25557250 # number of demand (read+write) miss cycles 618system.cpu.icache.overall_miss_latency::cpu.inst 25557250 # number of overall miss cycles 619system.cpu.icache.overall_miss_latency::total 25557250 # number of overall miss cycles |
| 601system.cpu.icache.ReadReq_accesses::cpu.inst 2168 # number of ReadReq accesses(hits+misses) 602system.cpu.icache.ReadReq_accesses::total 2168 # number of ReadReq accesses(hits+misses) 603system.cpu.icache.demand_accesses::cpu.inst 2168 # number of demand (read+write) accesses 604system.cpu.icache.demand_accesses::total 2168 # number of demand (read+write) accesses 605system.cpu.icache.overall_accesses::cpu.inst 2168 # number of overall (read+write) accesses 606system.cpu.icache.overall_accesses::total 2168 # number of overall (read+write) accesses 607system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169742 # miss rate for ReadReq accesses 608system.cpu.icache.ReadReq_miss_rate::total 0.169742 # miss rate for ReadReq accesses 609system.cpu.icache.demand_miss_rate::cpu.inst 0.169742 # miss rate for demand accesses 610system.cpu.icache.demand_miss_rate::total 0.169742 # miss rate for demand accesses 611system.cpu.icache.overall_miss_rate::cpu.inst 0.169742 # miss rate for overall accesses 612system.cpu.icache.overall_miss_rate::total 0.169742 # miss rate for overall accesses | 620system.cpu.icache.ReadReq_accesses::cpu.inst 2168 # number of ReadReq accesses(hits+misses) 621system.cpu.icache.ReadReq_accesses::total 2168 # number of ReadReq accesses(hits+misses) 622system.cpu.icache.demand_accesses::cpu.inst 2168 # number of demand (read+write) accesses 623system.cpu.icache.demand_accesses::total 2168 # number of demand (read+write) accesses 624system.cpu.icache.overall_accesses::cpu.inst 2168 # number of overall (read+write) accesses 625system.cpu.icache.overall_accesses::total 2168 # number of overall (read+write) accesses 626system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169742 # miss rate for ReadReq accesses 627system.cpu.icache.ReadReq_miss_rate::total 0.169742 # miss rate for ReadReq accesses 628system.cpu.icache.demand_miss_rate::cpu.inst 0.169742 # miss rate for demand accesses 629system.cpu.icache.demand_miss_rate::total 0.169742 # miss rate for demand accesses 630system.cpu.icache.overall_miss_rate::cpu.inst 0.169742 # miss rate for overall accesses 631system.cpu.icache.overall_miss_rate::total 0.169742 # miss rate for overall accesses |
| 613system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68983.695652 # average ReadReq miss latency 614system.cpu.icache.ReadReq_avg_miss_latency::total 68983.695652 # average ReadReq miss latency 615system.cpu.icache.demand_avg_miss_latency::cpu.inst 68983.695652 # average overall miss latency 616system.cpu.icache.demand_avg_miss_latency::total 68983.695652 # average overall miss latency 617system.cpu.icache.overall_avg_miss_latency::cpu.inst 68983.695652 # average overall miss latency 618system.cpu.icache.overall_avg_miss_latency::total 68983.695652 # average overall miss latency | 632system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69449.048913 # average ReadReq miss latency 633system.cpu.icache.ReadReq_avg_miss_latency::total 69449.048913 # average ReadReq miss latency 634system.cpu.icache.demand_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency 635system.cpu.icache.demand_avg_miss_latency::total 69449.048913 # average overall miss latency 636system.cpu.icache.overall_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency 637system.cpu.icache.overall_avg_miss_latency::total 69449.048913 # average overall miss latency |
| 619system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 620system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 621system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 622system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 623system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 624system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 625system.cpu.icache.fast_writes 0 # number of fast writes performed 626system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 631system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits 632system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits 633system.cpu.icache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses 634system.cpu.icache.ReadReq_mshr_misses::total 276 # number of ReadReq MSHR misses 635system.cpu.icache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 636system.cpu.icache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses 637system.cpu.icache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 638system.cpu.icache.overall_mshr_misses::total 276 # number of overall MSHR misses | 638system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 639system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 640system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 641system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 642system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 643system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 644system.cpu.icache.fast_writes 0 # number of fast writes performed 645system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 650system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits 651system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits 652system.cpu.icache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses 653system.cpu.icache.ReadReq_mshr_misses::total 276 # number of ReadReq MSHR misses 654system.cpu.icache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 655system.cpu.icache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses 656system.cpu.icache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 657system.cpu.icache.overall_mshr_misses::total 276 # number of overall MSHR misses |
| 639system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19887250 # number of ReadReq MSHR miss cycles 640system.cpu.icache.ReadReq_mshr_miss_latency::total 19887250 # number of ReadReq MSHR miss cycles 641system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19887250 # number of demand (read+write) MSHR miss cycles 642system.cpu.icache.demand_mshr_miss_latency::total 19887250 # number of demand (read+write) MSHR miss cycles 643system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19887250 # number of overall MSHR miss cycles 644system.cpu.icache.overall_mshr_miss_latency::total 19887250 # number of overall MSHR miss cycles | 658system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20059000 # number of ReadReq MSHR miss cycles 659system.cpu.icache.ReadReq_mshr_miss_latency::total 20059000 # number of ReadReq MSHR miss cycles 660system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20059000 # number of demand (read+write) MSHR miss cycles 661system.cpu.icache.demand_mshr_miss_latency::total 20059000 # number of demand (read+write) MSHR miss cycles 662system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20059000 # number of overall MSHR miss cycles 663system.cpu.icache.overall_mshr_miss_latency::total 20059000 # number of overall MSHR miss cycles |
| 645system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for ReadReq accesses 646system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127306 # mshr miss rate for ReadReq accesses 647system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for demand accesses 648system.cpu.icache.demand_mshr_miss_rate::total 0.127306 # mshr miss rate for demand accesses 649system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for overall accesses 650system.cpu.icache.overall_mshr_miss_rate::total 0.127306 # mshr miss rate for overall accesses | 664system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for ReadReq accesses 665system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127306 # mshr miss rate for ReadReq accesses 666system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for demand accesses 667system.cpu.icache.demand_mshr_miss_rate::total 0.127306 # mshr miss rate for demand accesses 668system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for overall accesses 669system.cpu.icache.overall_mshr_miss_rate::total 0.127306 # mshr miss rate for overall accesses |
| 651system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72055.253623 # average ReadReq mshr miss latency 652system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72055.253623 # average ReadReq mshr miss latency 653system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72055.253623 # average overall mshr miss latency 654system.cpu.icache.demand_avg_mshr_miss_latency::total 72055.253623 # average overall mshr miss latency 655system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72055.253623 # average overall mshr miss latency 656system.cpu.icache.overall_avg_mshr_miss_latency::total 72055.253623 # average overall mshr miss latency | 670system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72677.536232 # average ReadReq mshr miss latency 671system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72677.536232 # average ReadReq mshr miss latency 672system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency 673system.cpu.icache.demand_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency 674system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency 675system.cpu.icache.overall_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency |
| 657system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 658system.cpu.l2cache.tags.replacements 0 # number of replacements | 676system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 677system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 659system.cpu.l2cache.tags.tagsinuse 163.478116 # Cycle average of tags in use | 678system.cpu.l2cache.tags.tagsinuse 163.220102 # Cycle average of tags in use |
| 660system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 661system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. 662system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. 663system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 679system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 680system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. 681system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. 682system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 664system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.827183 # Average occupied blocks per requestor 665system.cpu.l2cache.tags.occ_blocks::cpu.data 31.650934 # Average occupied blocks per requestor 666system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004023 # Average percentage of cache occupancy 667system.cpu.l2cache.tags.occ_percent::cpu.data 0.000966 # Average percentage of cache occupancy 668system.cpu.l2cache.tags.occ_percent::total 0.004989 # Average percentage of cache occupancy | 683system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.613484 # Average occupied blocks per requestor 684system.cpu.l2cache.tags.occ_blocks::cpu.data 31.606618 # Average occupied blocks per requestor 685system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004017 # Average percentage of cache occupancy 686system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy 687system.cpu.l2cache.tags.occ_percent::total 0.004981 # Average percentage of cache occupancy |
| 669system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id 670system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id 671system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 672system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010315 # Percentage of cache occupancy per task id 673system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses 674system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses 675system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 676system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits --- 7 unchanged lines hidden (view full) --- 684system.cpu.l2cache.ReadExReq_misses::cpu.data 78 # number of ReadExReq misses 685system.cpu.l2cache.ReadExReq_misses::total 78 # number of ReadExReq misses 686system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses 687system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 688system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses 689system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses 690system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 691system.cpu.l2cache.overall_misses::total 417 # number of overall misses | 688system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id 689system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id 690system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 691system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010315 # Percentage of cache occupancy per task id 692system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses 693system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses 694system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 695system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits --- 7 unchanged lines hidden (view full) --- 703system.cpu.l2cache.ReadExReq_misses::cpu.data 78 # number of ReadExReq misses 704system.cpu.l2cache.ReadExReq_misses::total 78 # number of ReadExReq misses 705system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses 706system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 707system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses 708system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses 709system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 710system.cpu.l2cache.overall_misses::total 417 # number of overall misses |
| 692system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19600750 # number of ReadReq miss cycles | 711system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19772500 # number of ReadReq miss cycles |
| 693system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4946500 # number of ReadReq miss cycles | 712system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4946500 # number of ReadReq miss cycles |
| 694system.cpu.l2cache.ReadReq_miss_latency::total 24547250 # number of ReadReq miss cycles 695system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5508750 # number of ReadExReq miss cycles 696system.cpu.l2cache.ReadExReq_miss_latency::total 5508750 # number of ReadExReq miss cycles 697system.cpu.l2cache.demand_miss_latency::cpu.inst 19600750 # number of demand (read+write) miss cycles 698system.cpu.l2cache.demand_miss_latency::cpu.data 10455250 # number of demand (read+write) miss cycles 699system.cpu.l2cache.demand_miss_latency::total 30056000 # number of demand (read+write) miss cycles 700system.cpu.l2cache.overall_miss_latency::cpu.inst 19600750 # number of overall miss cycles 701system.cpu.l2cache.overall_miss_latency::cpu.data 10455250 # number of overall miss cycles 702system.cpu.l2cache.overall_miss_latency::total 30056000 # number of overall miss cycles | 713system.cpu.l2cache.ReadReq_miss_latency::total 24719000 # number of ReadReq miss cycles 714system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5510000 # number of ReadExReq miss cycles 715system.cpu.l2cache.ReadExReq_miss_latency::total 5510000 # number of ReadExReq miss cycles 716system.cpu.l2cache.demand_miss_latency::cpu.inst 19772500 # number of demand (read+write) miss cycles 717system.cpu.l2cache.demand_miss_latency::cpu.data 10456500 # number of demand (read+write) miss cycles 718system.cpu.l2cache.demand_miss_latency::total 30229000 # number of demand (read+write) miss cycles 719system.cpu.l2cache.overall_miss_latency::cpu.inst 19772500 # number of overall miss cycles 720system.cpu.l2cache.overall_miss_latency::cpu.data 10456500 # number of overall miss cycles 721system.cpu.l2cache.overall_miss_latency::total 30229000 # number of overall miss cycles |
| 703system.cpu.l2cache.ReadReq_accesses::cpu.inst 276 # number of ReadReq accesses(hits+misses) 704system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) 705system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) 706system.cpu.l2cache.ReadExReq_accesses::cpu.data 78 # number of ReadExReq accesses(hits+misses) 707system.cpu.l2cache.ReadExReq_accesses::total 78 # number of ReadExReq accesses(hits+misses) 708system.cpu.l2cache.demand_accesses::cpu.inst 276 # number of demand (read+write) accesses 709system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 710system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 717system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 718system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 719system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996377 # miss rate for demand accesses 720system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 721system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses 722system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996377 # miss rate for overall accesses 723system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 724system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses | 722system.cpu.l2cache.ReadReq_accesses::cpu.inst 276 # number of ReadReq accesses(hits+misses) 723system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) 724system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) 725system.cpu.l2cache.ReadExReq_accesses::cpu.data 78 # number of ReadExReq accesses(hits+misses) 726system.cpu.l2cache.ReadExReq_accesses::total 78 # number of ReadExReq accesses(hits+misses) 727system.cpu.l2cache.demand_accesses::cpu.inst 276 # number of demand (read+write) accesses 728system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 729system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 736system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 737system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 738system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996377 # miss rate for demand accesses 739system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 740system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses 741system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996377 # miss rate for overall accesses 742system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 743system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses |
| 725system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71275.454545 # average ReadReq miss latency | 744system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71900 # average ReadReq miss latency |
| 726system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77289.062500 # average ReadReq miss latency | 745system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77289.062500 # average ReadReq miss latency |
| 727system.cpu.l2cache.ReadReq_avg_miss_latency::total 72410.766962 # average ReadReq miss latency 728system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70625 # average ReadExReq miss latency 729system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70625 # average ReadExReq miss latency 730system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71275.454545 # average overall miss latency 731system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73628.521127 # average overall miss latency 732system.cpu.l2cache.demand_avg_miss_latency::total 72076.738609 # average overall miss latency 733system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71275.454545 # average overall miss latency 734system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73628.521127 # average overall miss latency 735system.cpu.l2cache.overall_avg_miss_latency::total 72076.738609 # average overall miss latency | 746system.cpu.l2cache.ReadReq_avg_miss_latency::total 72917.404130 # average ReadReq miss latency 747system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70641.025641 # average ReadExReq miss latency 748system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70641.025641 # average ReadExReq miss latency 749system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71900 # average overall miss latency 750system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency 751system.cpu.l2cache.demand_avg_miss_latency::total 72491.606715 # average overall miss latency 752system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71900 # average overall miss latency 753system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency 754system.cpu.l2cache.overall_avg_miss_latency::total 72491.606715 # average overall miss latency |
| 736system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 737system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 738system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 739system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 740system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 741system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 742system.cpu.l2cache.fast_writes 0 # number of fast writes performed 743system.cpu.l2cache.cache_copies 0 # number of cache copies performed 744system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses 745system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 746system.cpu.l2cache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses 747system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 78 # number of ReadExReq MSHR misses 748system.cpu.l2cache.ReadExReq_mshr_misses::total 78 # number of ReadExReq MSHR misses 749system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses 750system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 751system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses 752system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses 753system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 754system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses | 755system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 756system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 757system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 758system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 759system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 760system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 761system.cpu.l2cache.fast_writes 0 # number of fast writes performed 762system.cpu.l2cache.cache_copies 0 # number of cache copies performed 763system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses 764system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 765system.cpu.l2cache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses 766system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 78 # number of ReadExReq MSHR misses 767system.cpu.l2cache.ReadExReq_mshr_misses::total 78 # number of ReadExReq MSHR misses 768system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses 769system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 770system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses 771system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses 772system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 773system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses |
| 755system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16144250 # number of ReadReq MSHR miss cycles | 774system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16317000 # number of ReadReq MSHR miss cycles |
| 756system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4156000 # number of ReadReq MSHR miss cycles | 775system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4156000 # number of ReadReq MSHR miss cycles |
| 757system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20300250 # number of ReadReq MSHR miss cycles 758system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4539250 # number of ReadExReq MSHR miss cycles 759system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539250 # number of ReadExReq MSHR miss cycles 760system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16144250 # number of demand (read+write) MSHR miss cycles 761system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8695250 # number of demand (read+write) MSHR miss cycles 762system.cpu.l2cache.demand_mshr_miss_latency::total 24839500 # number of demand (read+write) MSHR miss cycles 763system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16144250 # number of overall MSHR miss cycles 764system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695250 # number of overall MSHR miss cycles 765system.cpu.l2cache.overall_mshr_miss_latency::total 24839500 # number of overall MSHR miss cycles | 776system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20473000 # number of ReadReq MSHR miss cycles 777system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4539500 # number of ReadExReq MSHR miss cycles 778system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539500 # number of ReadExReq MSHR miss cycles 779system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16317000 # number of demand (read+write) MSHR miss cycles 780system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8695500 # number of demand (read+write) MSHR miss cycles 781system.cpu.l2cache.demand_mshr_miss_latency::total 25012500 # number of demand (read+write) MSHR miss cycles 782system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16317000 # number of overall MSHR miss cycles 783system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695500 # number of overall MSHR miss cycles 784system.cpu.l2cache.overall_mshr_miss_latency::total 25012500 # number of overall MSHR miss cycles |
| 766system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadReq accesses 767system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 768system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997059 # mshr miss rate for ReadReq accesses 769system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 770system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 771system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for demand accesses 772system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 773system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses 774system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for overall accesses 775system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 776system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses | 785system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadReq accesses 786system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 787system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997059 # mshr miss rate for ReadReq accesses 788system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 789system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 790system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for demand accesses 791system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 792system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses 793system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for overall accesses 794system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 795system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses |
| 777system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58706.363636 # average ReadReq mshr miss latency | 796system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59334.545455 # average ReadReq mshr miss latency |
| 778system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64937.500000 # average ReadReq mshr miss latency | 797system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64937.500000 # average ReadReq mshr miss latency |
| 779system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59882.743363 # average ReadReq mshr miss latency 780system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58195.512821 # average ReadExReq mshr miss latency 781system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58195.512821 # average ReadExReq mshr miss latency 782system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58706.363636 # average overall mshr miss latency 783system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61234.154930 # average overall mshr miss latency 784system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59567.146283 # average overall mshr miss latency 785system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58706.363636 # average overall mshr miss latency 786system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61234.154930 # average overall mshr miss latency 787system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59567.146283 # average overall mshr miss latency | 798system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60392.330383 # average ReadReq mshr miss latency 799system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58198.717949 # average ReadExReq mshr miss latency 800system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58198.717949 # average ReadExReq mshr miss latency 801system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency 802system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency 803system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency 804system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency 805system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency 806system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency |
| 788system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 789system.cpu.dcache.tags.replacements 0 # number of replacements | 807system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 808system.cpu.dcache.tags.replacements 0 # number of replacements |
| 790system.cpu.dcache.tags.tagsinuse 82.450988 # Cycle average of tags in use | 809system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use |
| 791system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. 792system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 793system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. 794system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 810system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. 811system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 812system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. 813system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 795system.cpu.dcache.tags.occ_blocks::cpu.data 82.450988 # Average occupied blocks per requestor 796system.cpu.dcache.tags.occ_percent::cpu.data 0.020130 # Average percentage of cache occupancy 797system.cpu.dcache.tags.occ_percent::total 0.020130 # Average percentage of cache occupancy | 814system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor 815system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy 816system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy |
| 798system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 799system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 800system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id 801system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id 802system.cpu.dcache.tags.tag_accesses 5369 # Number of tag accesses 803system.cpu.dcache.tags.data_accesses 5369 # Number of data accesses 804system.cpu.dcache.ReadReq_hits::cpu.data 1543 # number of ReadReq hits 805system.cpu.dcache.ReadReq_hits::total 1543 # number of ReadReq hits --- 8 unchanged lines hidden (view full) --- 814system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses 815system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses 816system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses 817system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses 818system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses 819system.cpu.dcache.overall_misses::total 214 # number of overall misses 820system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles 821system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles | 817system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 818system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 819system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id 820system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id 821system.cpu.dcache.tags.tag_accesses 5369 # Number of tag accesses 822system.cpu.dcache.tags.data_accesses 5369 # Number of data accesses 823system.cpu.dcache.ReadReq_hits::cpu.data 1543 # number of ReadReq hits 824system.cpu.dcache.ReadReq_hits::total 1543 # number of ReadReq hits --- 8 unchanged lines hidden (view full) --- 833system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses 834system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses 835system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses 836system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses 837system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses 838system.cpu.dcache.overall_misses::total 214 # number of overall misses 839system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles 840system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles |
| 822system.cpu.dcache.WriteReq_miss_latency::cpu.data 5769250 # number of WriteReq miss cycles 823system.cpu.dcache.WriteReq_miss_latency::total 5769250 # number of WriteReq miss cycles 824system.cpu.dcache.demand_miss_latency::cpu.data 15584750 # number of demand (read+write) miss cycles 825system.cpu.dcache.demand_miss_latency::total 15584750 # number of demand (read+write) miss cycles 826system.cpu.dcache.overall_miss_latency::cpu.data 15584750 # number of overall miss cycles 827system.cpu.dcache.overall_miss_latency::total 15584750 # number of overall miss cycles | 841system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles 842system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles 843system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles 844system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles 845system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles 846system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles |
| 828system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) 829system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) 830system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 831system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) 832system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses 833system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses 834system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses 835system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses 836system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081001 # miss rate for ReadReq accesses 837system.cpu.dcache.ReadReq_miss_rate::total 0.081001 # miss rate for ReadReq accesses 838system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses 839system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses 840system.cpu.dcache.demand_miss_rate::cpu.data 0.081867 # miss rate for demand accesses 841system.cpu.dcache.demand_miss_rate::total 0.081867 # miss rate for demand accesses 842system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 # miss rate for overall accesses 843system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses 844system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency 845system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency | 847system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) 848system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) 849system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 850system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) 851system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses 852system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses 853system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses 854system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses 855system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081001 # miss rate for ReadReq accesses 856system.cpu.dcache.ReadReq_miss_rate::total 0.081001 # miss rate for ReadReq accesses 857system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses 858system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses 859system.cpu.dcache.demand_miss_rate::cpu.data 0.081867 # miss rate for demand accesses 860system.cpu.dcache.demand_miss_rate::total 0.081867 # miss rate for demand accesses 861system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 # miss rate for overall accesses 862system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses 863system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency 864system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency |
| 846system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73964.743590 # average WriteReq miss latency 847system.cpu.dcache.WriteReq_avg_miss_latency::total 73964.743590 # average WriteReq miss latency 848system.cpu.dcache.demand_avg_miss_latency::cpu.data 72825.934579 # average overall miss latency 849system.cpu.dcache.demand_avg_miss_latency::total 72825.934579 # average overall miss latency 850system.cpu.dcache.overall_avg_miss_latency::cpu.data 72825.934579 # average overall miss latency 851system.cpu.dcache.overall_avg_miss_latency::total 72825.934579 # average overall miss latency | 865system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency 866system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency 867system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency 868system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency 869system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency 870system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency |
| 852system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked 853system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 854system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 855system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 856system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked 857system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 858system.cpu.dcache.fast_writes 0 # number of fast writes performed 859system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 868system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses 869system.cpu.dcache.WriteReq_mshr_misses::total 78 # number of WriteReq MSHR misses 870system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 871system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 872system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 873system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses 874system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles 875system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles | 871system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked 872system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 873system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 874system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 875system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked 876system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 877system.cpu.dcache.fast_writes 0 # number of fast writes performed 878system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 887system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses 888system.cpu.dcache.WriteReq_mshr_misses::total 78 # number of WriteReq MSHR misses 889system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 890system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 891system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 892system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses 893system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles 894system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles |
| 876system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5586750 # number of WriteReq MSHR miss cycles 877system.cpu.dcache.WriteReq_mshr_miss_latency::total 5586750 # number of WriteReq MSHR miss cycles 878system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10596250 # number of demand (read+write) MSHR miss cycles 879system.cpu.dcache.demand_mshr_miss_latency::total 10596250 # number of demand (read+write) MSHR miss cycles 880system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10596250 # number of overall MSHR miss cycles 881system.cpu.dcache.overall_mshr_miss_latency::total 10596250 # number of overall MSHR miss cycles | 895system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles 896system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles 897system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles 898system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles 899system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles 900system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles |
| 882system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses 883system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses 884system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses 885system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses 886system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses 887system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses 888system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses 889system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses 890system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency 891system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency | 901system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses 902system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses 903system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses 904system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses 905system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses 906system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses 907system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses 908system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses 909system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency 910system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency |
| 892system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71625 # average WriteReq mshr miss latency 893system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71625 # average WriteReq mshr miss latency 894system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74621.478873 # average overall mshr miss latency 895system.cpu.dcache.demand_avg_mshr_miss_latency::total 74621.478873 # average overall mshr miss latency 896system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74621.478873 # average overall mshr miss latency 897system.cpu.dcache.overall_avg_mshr_miss_latency::total 74621.478873 # average overall mshr miss latency | 911system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency 912system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency 913system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency 914system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency 915system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency 916system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency |
| 898system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 899 900---------- End Simulation Statistics ---------- | 917system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 918 919---------- End Simulation Statistics ---------- |