| stats.txt (10230:a2bb75a474fd) | stats.txt (10242:cb4e86c17767) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated |
| 4sim_ticks 20011500 # Number of ticks simulated 5final_tick 20011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 19813000 # Number of ticks simulated 5final_tick 19813000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 41048 # Simulator instruction rate (inst/s) 8host_op_rate 74359 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 152650007 # Simulator tick rate (ticks/s) 10host_mem_usage 284392 # Number of bytes of host memory used 11host_seconds 0.13 # Real time elapsed on the host | 7host_inst_rate 35950 # Simulator instruction rate (inst/s) 8host_op_rate 65125 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 132368943 # Simulator tick rate (ticks/s) 10host_mem_usage 240140 # Number of bytes of host memory used 11host_seconds 0.15 # Real time elapsed on the host |
| 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26496 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 414 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 873097969 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 450940709 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1324038678 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 873097969 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 873097969 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 873097969 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 450940709 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1324038678 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 415 # Number of read requests accepted | 16system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17536 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17536 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 274 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 885075456 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 458688740 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1343764195 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 885075456 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 885075456 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 885075456 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 458688740 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1343764195 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 417 # Number of read requests accepted |
| 33system.physmem.writeReqs 0 # Number of write requests accepted | 33system.physmem.writeReqs 0 # Number of write requests accepted |
| 34system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue | 34system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue |
| 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 36system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM | 36system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM |
| 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 39system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side | 39system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side |
| 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 44system.physmem.perBankRdBursts::0 33 # Per bank write bursts | 44system.physmem.perBankRdBursts::0 34 # Per bank write bursts |
| 45system.physmem.perBankRdBursts::1 1 # Per bank write bursts | 45system.physmem.perBankRdBursts::1 1 # Per bank write bursts |
| 46system.physmem.perBankRdBursts::2 5 # Per bank write bursts | 46system.physmem.perBankRdBursts::2 6 # Per bank write bursts |
| 47system.physmem.perBankRdBursts::3 8 # Per bank write bursts 48system.physmem.perBankRdBursts::4 50 # Per bank write bursts 49system.physmem.perBankRdBursts::5 44 # Per bank write bursts | 47system.physmem.perBankRdBursts::3 8 # Per bank write bursts 48system.physmem.perBankRdBursts::4 50 # Per bank write bursts 49system.physmem.perBankRdBursts::5 44 # Per bank write bursts |
| 50system.physmem.perBankRdBursts::6 20 # Per bank write bursts | 50system.physmem.perBankRdBursts::6 21 # Per bank write bursts |
| 51system.physmem.perBankRdBursts::7 36 # Per bank write bursts | 51system.physmem.perBankRdBursts::7 36 # Per bank write bursts |
| 52system.physmem.perBankRdBursts::8 23 # Per bank write bursts | 52system.physmem.perBankRdBursts::8 22 # Per bank write bursts |
| 53system.physmem.perBankRdBursts::9 73 # Per bank write bursts 54system.physmem.perBankRdBursts::10 63 # Per bank write bursts 55system.physmem.perBankRdBursts::11 17 # Per bank write bursts 56system.physmem.perBankRdBursts::12 2 # Per bank write bursts 57system.physmem.perBankRdBursts::13 17 # Per bank write bursts 58system.physmem.perBankRdBursts::14 6 # Per bank write bursts 59system.physmem.perBankRdBursts::15 17 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts --- 9 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 53system.physmem.perBankRdBursts::9 73 # Per bank write bursts 54system.physmem.perBankRdBursts::10 63 # Per bank write bursts 55system.physmem.perBankRdBursts::11 17 # Per bank write bursts 56system.physmem.perBankRdBursts::12 2 # Per bank write bursts 57system.physmem.perBankRdBursts::13 17 # Per bank write bursts 58system.physmem.perBankRdBursts::14 6 # Per bank write bursts 59system.physmem.perBankRdBursts::15 17 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts --- 9 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 19963000 # Total gap between requests | 78system.physmem.totGap 19764000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 85system.physmem.readPktSize::6 415 # Read request sizes (log2) | 85system.physmem.readPktSize::6 417 # Read request sizes (log2) |
| 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 250 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see |
| 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 77 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation | 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 77 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation |
| 190system.physmem.bytesPerActivate::mean 248.742268 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 161.697208 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 270.249471 # Bytes accessed per row activation | 190system.physmem.bytesPerActivate::mean 250.721649 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 163.075563 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 270.532528 # Bytes accessed per row activation |
| 193system.physmem.bytesPerActivate::0-127 33 34.02% 34.02% # Bytes accessed per row activation | 193system.physmem.bytesPerActivate::0-127 33 34.02% 34.02% # Bytes accessed per row activation |
| 194system.physmem.bytesPerActivate::128-255 34 35.05% 69.07% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 13 13.40% 82.47% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 3 3.09% 85.57% # Bytes accessed per row activation | 194system.physmem.bytesPerActivate::128-255 36 37.11% 71.13% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 9 9.28% 80.41% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 5 5.15% 85.57% # Bytes accessed per row activation |
| 197system.physmem.bytesPerActivate::640-767 6 6.19% 91.75% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::896-1023 3 3.09% 94.85% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation | 197system.physmem.bytesPerActivate::640-767 6 6.19% 91.75% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::896-1023 3 3.09% 94.85% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation |
| 201system.physmem.totQLat 4234000 # Total ticks spent queuing 202system.physmem.totMemAccLat 12015250 # Total ticks spent from burst creation until serviced by the DRAM 203system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers 204system.physmem.avgQLat 10202.41 # Average queueing delay per DRAM burst | 201system.physmem.totQLat 3851250 # Total ticks spent queuing 202system.physmem.totMemAccLat 11670000 # Total ticks spent from burst creation until serviced by the DRAM 203system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers 204system.physmem.avgQLat 9235.61 # Average queueing delay per DRAM burst |
| 205system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 205system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 206system.physmem.avgMemAccLat 28952.41 # Average memory access latency per DRAM burst 207system.physmem.avgRdBW 1327.24 # Average DRAM read bandwidth in MiByte/s | 206system.physmem.avgMemAccLat 27985.61 # Average memory access latency per DRAM burst 207system.physmem.avgRdBW 1346.99 # Average DRAM read bandwidth in MiByte/s |
| 208system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 208system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 209system.physmem.avgRdBWSys 1327.24 # Average system read bandwidth in MiByte/s | 209system.physmem.avgRdBWSys 1346.99 # Average system read bandwidth in MiByte/s |
| 210system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 211system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 210system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 211system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 212system.physmem.busUtil 10.37 # Data bus utilization in percentage 213system.physmem.busUtilRead 10.37 # Data bus utilization in percentage for reads | 212system.physmem.busUtil 10.52 # Data bus utilization in percentage 213system.physmem.busUtilRead 10.52 # Data bus utilization in percentage for reads |
| 214system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 215system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing 216system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 214system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 215system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing 216system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 217system.physmem.readRowHits 307 # Number of row buffer hits during reads | 217system.physmem.readRowHits 310 # Number of row buffer hits during reads |
| 218system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 218system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 219system.physmem.readRowHitRate 73.98 # Row buffer hit rate for reads | 219system.physmem.readRowHitRate 74.34 # Row buffer hit rate for reads |
| 220system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 220system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 221system.physmem.avgGap 48103.61 # Average gap between requests 222system.physmem.pageHitRate 73.98 # Row buffer hit rate, read and write combined | 221system.physmem.avgGap 47395.68 # Average gap between requests 222system.physmem.pageHitRate 74.34 # Row buffer hit rate, read and write combined |
| 223system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 224system.physmem.memoryStateTime::REF 520000 # Time in different power states 225system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 223system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 224system.physmem.memoryStateTime::REF 520000 # Time in different power states 225system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 226system.physmem.memoryStateTime::ACT 15333750 # Time in different power states | 226system.physmem.memoryStateTime::ACT 15315750 # Time in different power states |
| 227system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 227system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 228system.membus.throughput 1324038678 # Throughput (bytes/s) 229system.membus.trans_dist::ReadReq 338 # Transaction distribution 230system.membus.trans_dist::ReadResp 337 # Transaction distribution | 228system.membus.throughput 1343764195 # Throughput (bytes/s) 229system.membus.trans_dist::ReadReq 340 # Transaction distribution 230system.membus.trans_dist::ReadResp 339 # Transaction distribution |
| 231system.membus.trans_dist::ReadExReq 77 # Transaction distribution 232system.membus.trans_dist::ReadExResp 77 # Transaction distribution | 231system.membus.trans_dist::ReadExReq 77 # Transaction distribution 232system.membus.trans_dist::ReadExResp 77 # Transaction distribution |
| 233system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 829 # Packet count per connected master and slave (bytes) 234system.membus.pkt_count_system.cpu.l2cache.mem_side::total 829 # Packet count per connected master and slave (bytes) 235system.membus.pkt_count::total 829 # Packet count per connected master and slave (bytes) 236system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26496 # Cumulative packet size per connected master and slave (bytes) 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26496 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size::total 26496 # Cumulative packet size per connected master and slave (bytes) 239system.membus.data_through_bus 26496 # Total data (bytes) | 233system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) 234system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) 235system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) 236system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) 239system.membus.data_through_bus 26624 # Total data (bytes) |
| 240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 241system.membus.reqLayer0.occupancy 501000 # Layer occupancy (ticks) 242system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) 243system.membus.respLayer1.occupancy 3873250 # Layer occupancy (ticks) 244system.membus.respLayer1.utilization 19.4 # Layer utilization (%) | 241system.membus.reqLayer0.occupancy 508000 # Layer occupancy (ticks) 242system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) 243system.membus.respLayer1.occupancy 3892500 # Layer occupancy (ticks) 244system.membus.respLayer1.utilization 19.6 # Layer utilization (%) |
| 245system.cpu_clk_domain.clock 500 # Clock period in ticks | 245system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 246system.cpu.branchPred.lookups 3083 # Number of BP lookups 247system.cpu.branchPred.condPredicted 3083 # Number of conditional branches predicted 248system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect 249system.cpu.branchPred.BTBLookups 2281 # Number of BTB lookups 250system.cpu.branchPred.BTBHits 725 # Number of BTB hits | 246system.cpu.branchPred.lookups 3151 # Number of BP lookups 247system.cpu.branchPred.condPredicted 3151 # Number of conditional branches predicted 248system.cpu.branchPred.condIncorrect 538 # Number of conditional branches incorrect 249system.cpu.branchPred.BTBLookups 2362 # Number of BTB lookups 250system.cpu.branchPred.BTBHits 784 # Number of BTB hits |
| 251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 252system.cpu.branchPred.BTBHitPct 31.784305 # BTB Hit Percentage 253system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. 254system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. | 252system.cpu.branchPred.BTBHitPct 33.192210 # BTB Hit Percentage 253system.cpu.branchPred.usedRAS 213 # Number of times the RAS was used to get a target. 254system.cpu.branchPred.RASInCorrect 80 # Number of incorrect RAS predictions. |
| 255system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 256system.cpu.workload.num_syscalls 11 # Number of system calls | 255system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 256system.cpu.workload.num_syscalls 11 # Number of system calls |
| 257system.cpu.numCycles 40024 # number of cpu cycles simulated | 257system.cpu.numCycles 39627 # number of cpu cycles simulated |
| 258system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 259system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 258system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 259system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 260system.cpu.fetch.icacheStallCycles 10292 # Number of cycles fetch is stalled on an Icache miss 261system.cpu.fetch.Insts 14141 # Number of instructions fetch has processed 262system.cpu.fetch.Branches 3083 # Number of branches that fetch encountered 263system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken 264system.cpu.fetch.Cycles 3942 # Number of cycles fetch has run and was not squashing or blocked 265system.cpu.fetch.SquashCycles 2472 # Number of cycles fetch has spent squashing 266system.cpu.fetch.BlockedCycles 5349 # Number of cycles fetch has spent blocked 267system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 268system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps 269system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR 270system.cpu.fetch.CacheLines 1981 # Number of cache lines fetched 271system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed 272system.cpu.fetch.rateDist::samples 21900 # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.rateDist::mean 1.150913 # Number of instructions fetched each cycle (Total) 274system.cpu.fetch.rateDist::stdev 2.666787 # Number of instructions fetched each cycle (Total) | 260system.cpu.fetch.icacheStallCycles 10249 # Number of cycles fetch is stalled on an Icache miss 261system.cpu.fetch.Insts 14342 # Number of instructions fetch has processed 262system.cpu.fetch.Branches 3151 # Number of branches that fetch encountered 263system.cpu.fetch.predictedBranches 997 # Number of branches that fetch has predicted taken 264system.cpu.fetch.Cycles 4009 # Number of cycles fetch has run and was not squashing or blocked 265system.cpu.fetch.SquashCycles 2516 # Number of cycles fetch has spent squashing 266system.cpu.fetch.BlockedCycles 5030 # Number of cycles fetch has spent blocked 267system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 268system.cpu.fetch.PendingTrapStallCycles 499 # Number of stall cycles due to pending traps 269system.cpu.fetch.CacheLines 2013 # Number of cache lines fetched 270system.cpu.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed 271system.cpu.fetch.rateDist::samples 21739 # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::mean 1.176503 # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.rateDist::stdev 2.686230 # Number of instructions fetched each cycle (Total) |
| 275system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 274system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 276system.cpu.fetch.rateDist::0 18059 82.46% 82.46% # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.rateDist::1 217 0.99% 83.45% # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::2 142 0.65% 84.10% # Number of instructions fetched each cycle (Total) 279system.cpu.fetch.rateDist::3 224 1.02% 85.12% # Number of instructions fetched each cycle (Total) 280system.cpu.fetch.rateDist::4 180 0.82% 85.95% # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::5 201 0.92% 86.86% # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::6 275 1.26% 88.12% # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::7 159 0.73% 88.84% # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::8 2443 11.16% 100.00% # Number of instructions fetched each cycle (Total) | 275system.cpu.fetch.rateDist::0 17828 82.01% 82.01% # Number of instructions fetched each cycle (Total) 276system.cpu.fetch.rateDist::1 213 0.98% 82.99% # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.rateDist::2 156 0.72% 83.71% # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::3 227 1.04% 84.75% # Number of instructions fetched each cycle (Total) 279system.cpu.fetch.rateDist::4 194 0.89% 85.64% # Number of instructions fetched each cycle (Total) 280system.cpu.fetch.rateDist::5 208 0.96% 86.60% # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::6 291 1.34% 87.94% # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::7 168 0.77% 88.71% # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::8 2454 11.29% 100.00% # Number of instructions fetched each cycle (Total) |
| 285system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 284system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 288system.cpu.fetch.rateDist::total 21900 # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.branchRate 0.077029 # Number of branch fetches per cycle 290system.cpu.fetch.rate 0.353313 # Number of inst fetches per cycle 291system.cpu.decode.IdleCycles 11088 # Number of cycles decode is idle 292system.cpu.decode.BlockedCycles 5242 # Number of cycles decode is blocked 293system.cpu.decode.RunCycles 3583 # Number of cycles decode is running 294system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking 295system.cpu.decode.SquashCycles 1856 # Number of cycles decode is squashing 296system.cpu.decode.DecodedInsts 24179 # Number of instructions handled by decode 297system.cpu.rename.SquashCycles 1856 # Number of cycles rename is squashing 298system.cpu.rename.IdleCycles 11454 # Number of cycles rename is idle 299system.cpu.rename.BlockCycles 3886 # Number of cycles rename is blocking 300system.cpu.rename.serializeStallCycles 592 # count of cycles rename stalled for serializing inst 301system.cpu.rename.RunCycles 3330 # Number of cycles rename is running 302system.cpu.rename.UnblockCycles 782 # Number of cycles rename is unblocking 303system.cpu.rename.RenamedInsts 22657 # Number of instructions processed by rename 304system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full 305system.cpu.rename.IQFullEvents 37 # Number of times rename has blocked due to IQ full 306system.cpu.rename.LSQFullEvents 664 # Number of times rename has blocked due to LSQ full 307system.cpu.rename.RenamedOperands 25254 # Number of destination operands rename has renamed 308system.cpu.rename.RenameLookups 55037 # Number of register rename lookups that rename has made 309system.cpu.rename.int_rename_lookups 31380 # Number of integer rename lookups | 287system.cpu.fetch.rateDist::total 21739 # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.branchRate 0.079516 # Number of branch fetches per cycle 289system.cpu.fetch.rate 0.361925 # Number of inst fetches per cycle 290system.cpu.decode.IdleCycles 11168 # Number of cycles decode is idle 291system.cpu.decode.BlockedCycles 4895 # Number of cycles decode is blocked 292system.cpu.decode.RunCycles 3648 # Number of cycles decode is running 293system.cpu.decode.UnblockCycles 137 # Number of cycles decode is unblocking 294system.cpu.decode.SquashCycles 1891 # Number of cycles decode is squashing 295system.cpu.decode.DecodedInsts 24503 # Number of instructions handled by decode 296system.cpu.rename.SquashCycles 1891 # Number of cycles rename is squashing 297system.cpu.rename.IdleCycles 11399 # Number of cycles rename is idle 298system.cpu.rename.BlockCycles 477 # Number of cycles rename is blocking 299system.cpu.rename.serializeStallCycles 595 # count of cycles rename stalled for serializing inst 300system.cpu.rename.RunCycles 3548 # Number of cycles rename is running 301system.cpu.rename.UnblockCycles 3829 # Number of cycles rename is unblocking 302system.cpu.rename.RenamedInsts 23145 # Number of instructions processed by rename 303system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full 304system.cpu.rename.IQFullEvents 51 # Number of times rename has blocked due to IQ full 305system.cpu.rename.SQFullEvents 3750 # Number of times rename has blocked due to SQ full 306system.cpu.rename.RenamedOperands 25950 # Number of destination operands rename has renamed 307system.cpu.rename.RenameLookups 56380 # Number of register rename lookups that rename has made 308system.cpu.rename.int_rename_lookups 31990 # Number of integer rename lookups |
| 310system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 311system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed | 309system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 310system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed |
| 312system.cpu.rename.UndoneMaps 14191 # Number of HB maps that are undone due to squashing 313system.cpu.rename.serializingInsts 30 # count of serializing insts renamed 314system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed 315system.cpu.rename.skidInsts 2053 # count of insts added to the skid buffer 316system.cpu.memDep0.insertedLoads 2285 # Number of loads inserted to the mem dependence unit. 317system.cpu.memDep0.insertedStores 1565 # Number of stores inserted to the mem dependence unit. 318system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. 319system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. 320system.cpu.iq.iqInstsAdded 20246 # Number of instructions added to the IQ (excludes non-spec) 321system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ 322system.cpu.iq.iqInstsIssued 17025 # Number of instructions issued 323system.cpu.iq.iqSquashedInstsIssued 298 # Number of squashed instructions issued 324system.cpu.iq.iqSquashedInstsExamined 9739 # Number of squashed instructions iterated over during squash; mainly for profiling 325system.cpu.iq.iqSquashedOperandsExamined 13977 # Number of squashed operands that are examined and possibly removed from graph 326system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed 327system.cpu.iq.issued_per_cycle::samples 21900 # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::mean 0.777397 # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::stdev 1.653011 # Number of insts issued each cycle | 311system.cpu.rename.UndoneMaps 14887 # Number of HB maps that are undone due to squashing 312system.cpu.rename.serializingInsts 33 # count of serializing insts renamed 313system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed 314system.cpu.rename.skidInsts 1258 # count of insts added to the skid buffer 315system.cpu.memDep0.insertedLoads 2293 # Number of loads inserted to the mem dependence unit. 316system.cpu.memDep0.insertedStores 1619 # Number of stores inserted to the mem dependence unit. 317system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads. 318system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. 319system.cpu.iq.iqInstsAdded 20529 # Number of instructions added to the IQ (excludes non-spec) 320system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ 321system.cpu.iq.iqInstsIssued 17116 # Number of instructions issued 322system.cpu.iq.iqSquashedInstsIssued 311 # Number of squashed instructions issued 323system.cpu.iq.iqSquashedInstsExamined 10025 # Number of squashed instructions iterated over during squash; mainly for profiling 324system.cpu.iq.iqSquashedOperandsExamined 14683 # Number of squashed operands that are examined and possibly removed from graph 325system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed 326system.cpu.iq.issued_per_cycle::samples 21739 # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::mean 0.787341 # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::stdev 1.689074 # Number of insts issued each cycle |
| 330system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 329system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 331system.cpu.iq.issued_per_cycle::0 16414 74.95% 74.95% # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::1 1544 7.05% 82.00% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::2 1087 4.96% 86.96% # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::3 722 3.30% 90.26% # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::4 701 3.20% 93.46% # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::5 573 2.62% 96.08% # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::6 583 2.66% 98.74% # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::7 234 1.07% 99.81% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle | 330system.cpu.iq.issued_per_cycle::0 16539 76.08% 76.08% # Number of insts issued each cycle 331system.cpu.iq.issued_per_cycle::1 1246 5.73% 81.81% # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::2 983 4.52% 86.33% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::3 694 3.19% 89.53% # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::4 782 3.60% 93.12% # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::5 618 2.84% 95.97% # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::6 580 2.67% 98.63% # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::7 252 1.16% 99.79% # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::8 45 0.21% 100.00% # Number of insts issued each cycle |
| 340system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 339system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 343system.cpu.iq.issued_per_cycle::total 21900 # Number of insts issued each cycle | 342system.cpu.iq.issued_per_cycle::total 21739 # Number of insts issued each cycle |
| 344system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 343system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 345system.cpu.iq.fu_full::IntAlu 140 77.35% 77.35% # attempts to use FU when none available 346system.cpu.iq.fu_full::IntMult 0 0.00% 77.35% # attempts to use FU when none available 347system.cpu.iq.fu_full::IntDiv 0 0.00% 77.35% # attempts to use FU when none available 348system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.35% # attempts to use FU when none available 349system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.35% # attempts to use FU when none available 350system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.35% # attempts to use FU when none available 351system.cpu.iq.fu_full::FloatMult 0 0.00% 77.35% # attempts to use FU when none available 352system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.35% # attempts to use FU when none available 353system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.35% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.35% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.35% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.35% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.35% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.35% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.35% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdMult 0 0.00% 77.35% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.35% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdShift 0 0.00% 77.35% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.35% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.35% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.35% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.35% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.35% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.35% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.35% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.35% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.35% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.35% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.35% # attempts to use FU when none available 374system.cpu.iq.fu_full::MemRead 26 14.36% 91.71% # attempts to use FU when none available 375system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available | 344system.cpu.iq.fu_full::IntAlu 136 76.40% 76.40% # attempts to use FU when none available 345system.cpu.iq.fu_full::IntMult 0 0.00% 76.40% # attempts to use FU when none available 346system.cpu.iq.fu_full::IntDiv 0 0.00% 76.40% # attempts to use FU when none available 347system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.40% # attempts to use FU when none available 348system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.40% # attempts to use FU when none available 349system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.40% # attempts to use FU when none available 350system.cpu.iq.fu_full::FloatMult 0 0.00% 76.40% # attempts to use FU when none available 351system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.40% # attempts to use FU when none available 352system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.40% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.40% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.40% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.40% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.40% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.40% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.40% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdMult 0 0.00% 76.40% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.40% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdShift 0 0.00% 76.40% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.40% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.40% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.40% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.40% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.40% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.40% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.40% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.40% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.40% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.40% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.40% # attempts to use FU when none available 373system.cpu.iq.fu_full::MemRead 26 14.61% 91.01% # attempts to use FU when none available 374system.cpu.iq.fu_full::MemWrite 16 8.99% 100.00% # attempts to use FU when none available |
| 376system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 377system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 378system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued | 375system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 376system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 377system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued |
| 379system.cpu.iq.FU_type_0::IntAlu 13665 80.26% 80.28% # Type of FU issued 380system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.31% # Type of FU issued | 378system.cpu.iq.FU_type_0::IntAlu 13738 80.26% 80.28% # Type of FU issued 379system.cpu.iq.FU_type_0::IntMult 5 0.03% 80.31% # Type of FU issued |
| 381system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.35% # Type of FU issued 382system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.35% # Type of FU issued 383system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.35% # Type of FU issued 384system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.35% # Type of FU issued 385system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.35% # Type of FU issued 386system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.35% # Type of FU issued 387system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.35% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.35% # Type of FU issued --- 11 unchanged lines hidden (view full) --- 400system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.35% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.35% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.35% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.35% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.35% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.35% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.35% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.35% # Type of FU issued | 380system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.35% # Type of FU issued 381system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.35% # Type of FU issued 382system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.35% # Type of FU issued 383system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.35% # Type of FU issued 384system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.35% # Type of FU issued 385system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.35% # Type of FU issued 386system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.35% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.35% # Type of FU issued --- 11 unchanged lines hidden (view full) --- 399system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.35% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.35% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.35% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.35% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.35% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.35% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.35% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.35% # Type of FU issued |
| 408system.cpu.iq.FU_type_0::MemRead 1973 11.59% 91.94% # Type of FU issued 409system.cpu.iq.FU_type_0::MemWrite 1373 8.06% 100.00% # Type of FU issued | 407system.cpu.iq.FU_type_0::MemRead 1970 11.51% 91.86% # Type of FU issued 408system.cpu.iq.FU_type_0::MemWrite 1393 8.14% 100.00% # Type of FU issued |
| 410system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 411system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 409system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 410system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 412system.cpu.iq.FU_type_0::total 17025 # Type of FU issued 413system.cpu.iq.rate 0.425370 # Inst issue rate 414system.cpu.iq.fu_busy_cnt 181 # FU busy when requested 415system.cpu.iq.fu_busy_rate 0.010631 # FU busy rate (busy events/executed inst) 416system.cpu.iq.int_inst_queue_reads 56421 # Number of integer instruction queue reads 417system.cpu.iq.int_inst_queue_writes 30018 # Number of integer instruction queue writes 418system.cpu.iq.int_inst_queue_wakeup_accesses 15641 # Number of integer instruction queue wakeup accesses | 411system.cpu.iq.FU_type_0::total 17116 # Type of FU issued 412system.cpu.iq.rate 0.431928 # Inst issue rate 413system.cpu.iq.fu_busy_cnt 178 # FU busy when requested 414system.cpu.iq.fu_busy_rate 0.010400 # FU busy rate (busy events/executed inst) 415system.cpu.iq.int_inst_queue_reads 56452 # Number of integer instruction queue reads 416system.cpu.iq.int_inst_queue_writes 30591 # Number of integer instruction queue writes 417system.cpu.iq.int_inst_queue_wakeup_accesses 15728 # Number of integer instruction queue wakeup accesses |
| 419system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 420system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 421system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses | 418system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 419system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 420system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses |
| 422system.cpu.iq.int_alu_accesses 17199 # Number of integer alu accesses | 421system.cpu.iq.int_alu_accesses 17287 # Number of integer alu accesses |
| 423system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses | 422system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses |
| 424system.cpu.iew.lsq.thread0.forwLoads 168 # Number of loads that had data forwarded from stores | 423system.cpu.iew.lsq.thread0.forwLoads 197 # Number of loads that had data forwarded from stores |
| 425system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 424system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 426system.cpu.iew.lsq.thread0.squashedLoads 1232 # Number of loads squashed | 425system.cpu.iew.lsq.thread0.squashedLoads 1240 # Number of loads squashed |
| 427system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed | 426system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed |
| 428system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations 429system.cpu.iew.lsq.thread0.squashedStores 630 # Number of stores squashed | 427system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations 428system.cpu.iew.lsq.thread0.squashedStores 684 # Number of stores squashed |
| 430system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 431system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 429system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 430system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 432system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled | 431system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled |
| 433system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked 434system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 432system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked 433system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 435system.cpu.iew.iewSquashCycles 1856 # Number of cycles IEW is squashing 436system.cpu.iew.iewBlockCycles 3085 # Number of cycles IEW is blocking 437system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking 438system.cpu.iew.iewDispatchedInsts 20272 # Number of instructions dispatched to IQ 439system.cpu.iew.iewDispSquashedInsts 39 # Number of squashed instructions skipped by dispatch 440system.cpu.iew.iewDispLoadInsts 2285 # Number of dispatched load instructions 441system.cpu.iew.iewDispStoreInsts 1565 # Number of dispatched store instructions 442system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions | 434system.cpu.iew.iewSquashCycles 1891 # Number of cycles IEW is squashing 435system.cpu.iew.iewBlockCycles 262 # Number of cycles IEW is blocking 436system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking 437system.cpu.iew.iewDispatchedInsts 20557 # Number of instructions dispatched to IQ 438system.cpu.iew.iewDispSquashedInsts 31 # Number of squashed instructions skipped by dispatch 439system.cpu.iew.iewDispLoadInsts 2293 # Number of dispatched load instructions 440system.cpu.iew.iewDispStoreInsts 1619 # Number of dispatched store instructions 441system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions |
| 443system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall | 442system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall |
| 444system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 445system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations 446system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly 447system.cpu.iew.predictedNotTakenIncorrect 571 # Number of branches that were predicted not taken incorrectly 448system.cpu.iew.branchMispredicts 687 # Number of branch mispredicts detected at execute 449system.cpu.iew.iewExecutedInsts 16122 # Number of executed instructions 450system.cpu.iew.iewExecLoadInsts 1853 # Number of load instructions executed 451system.cpu.iew.iewExecSquashedInsts 903 # Number of squashed instructions skipped in execute | 443system.cpu.iew.iewLSQFullEvents 22 # Number of times the LSQ has become full, causing a stall 444system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations 445system.cpu.iew.predictedTakenIncorrect 124 # Number of branches that were predicted taken incorrectly 446system.cpu.iew.predictedNotTakenIncorrect 573 # Number of branches that were predicted not taken incorrectly 447system.cpu.iew.branchMispredicts 697 # Number of branch mispredicts detected at execute 448system.cpu.iew.iewExecutedInsts 16214 # Number of executed instructions 449system.cpu.iew.iewExecLoadInsts 1838 # Number of load instructions executed 450system.cpu.iew.iewExecSquashedInsts 902 # Number of squashed instructions skipped in execute |
| 452system.cpu.iew.exec_swp 0 # number of swp insts executed 453system.cpu.iew.exec_nop 0 # number of nop insts executed | 451system.cpu.iew.exec_swp 0 # number of swp insts executed 452system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 454system.cpu.iew.exec_refs 3126 # number of memory reference insts executed 455system.cpu.iew.exec_branches 1623 # Number of branches executed 456system.cpu.iew.exec_stores 1273 # Number of stores executed 457system.cpu.iew.exec_rate 0.402808 # Inst execution rate 458system.cpu.iew.wb_sent 15864 # cumulative count of insts sent to commit 459system.cpu.iew.wb_count 15645 # cumulative count of insts written-back 460system.cpu.iew.wb_producers 10128 # num instructions producing a value 461system.cpu.iew.wb_consumers 15590 # num instructions consuming a value | 453system.cpu.iew.exec_refs 3129 # number of memory reference insts executed 454system.cpu.iew.exec_branches 1636 # Number of branches executed 455system.cpu.iew.exec_stores 1291 # Number of stores executed 456system.cpu.iew.exec_rate 0.409165 # Inst execution rate 457system.cpu.iew.wb_sent 15955 # cumulative count of insts sent to commit 458system.cpu.iew.wb_count 15732 # cumulative count of insts written-back 459system.cpu.iew.wb_producers 10485 # num instructions producing a value 460system.cpu.iew.wb_consumers 16294 # num instructions consuming a value |
| 462system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 461system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 463system.cpu.iew.wb_rate 0.390890 # insts written-back per cycle 464system.cpu.iew.wb_fanout 0.649647 # average fanout of values written-back | 462system.cpu.iew.wb_rate 0.397002 # insts written-back per cycle 463system.cpu.iew.wb_fanout 0.643488 # average fanout of values written-back |
| 465system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 464system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 466system.cpu.commit.commitSquashedInsts 10536 # The number of squashed insts skipped by commit | 465system.cpu.commit.commitSquashedInsts 10809 # The number of squashed insts skipped by commit |
| 467system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards | 466system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards |
| 468system.cpu.commit.branchMispredicts 592 # The number of times a branch was mispredicted 469system.cpu.commit.committed_per_cycle::samples 20044 # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::mean 0.486280 # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::stdev 1.342641 # Number of insts commited each cycle | 467system.cpu.commit.branchMispredicts 599 # The number of times a branch was mispredicted 468system.cpu.commit.committed_per_cycle::samples 19848 # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::mean 0.491082 # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::stdev 1.377621 # Number of insts commited each cycle |
| 472system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 471system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 473system.cpu.commit.committed_per_cycle::0 16476 82.20% 82.20% # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::1 1360 6.79% 88.98% # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::2 589 2.94% 91.92% # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::3 713 3.56% 95.48% # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::4 364 1.82% 97.30% # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::5 136 0.68% 97.97% # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::6 120 0.60% 98.57% # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::7 74 0.37% 98.94% # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Number of insts commited each cycle | 472system.cpu.commit.committed_per_cycle::0 16557 83.42% 83.42% # Number of insts commited each cycle 473system.cpu.commit.committed_per_cycle::1 1016 5.12% 88.54% # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::2 561 2.83% 91.36% # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::3 767 3.86% 95.23% # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::4 387 1.95% 97.18% # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::5 137 0.69% 97.87% # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::6 118 0.59% 98.46% # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::7 73 0.37% 98.83% # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::8 232 1.17% 100.00% # Number of insts commited each cycle |
| 482system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 481system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 485system.cpu.commit.committed_per_cycle::total 20044 # Number of insts commited each cycle | 484system.cpu.commit.committed_per_cycle::total 19848 # Number of insts commited each cycle |
| 486system.cpu.commit.committedInsts 5380 # Number of instructions committed 487system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed 488system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 489system.cpu.commit.refs 1988 # Number of memory references committed 490system.cpu.commit.loads 1053 # Number of loads committed 491system.cpu.commit.membars 0 # Number of memory barriers committed 492system.cpu.commit.branches 1208 # Number of branches committed 493system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 523system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction 524system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction 525system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction 526system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction 527system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction 528system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 529system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 530system.cpu.commit.op_class_0::total 9747 # Class of committed instruction | 485system.cpu.commit.committedInsts 5380 # Number of instructions committed 486system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed 487system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 488system.cpu.commit.refs 1988 # Number of memory references committed 489system.cpu.commit.loads 1053 # Number of loads committed 490system.cpu.commit.membars 0 # Number of memory barriers committed 491system.cpu.commit.branches 1208 # Number of branches committed 492system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 522system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction 523system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction 524system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction 525system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction 526system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction 527system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 528system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 529system.cpu.commit.op_class_0::total 9747 # Class of committed instruction |
| 531system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached | 530system.cpu.commit.bw_lim_events 232 # number cycles where commit BW limit reached |
| 532system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 531system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 533system.cpu.rob.rob_reads 40115 # The number of ROB reads 534system.cpu.rob.rob_writes 42444 # The number of ROB writes 535system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself 536system.cpu.idleCycles 18124 # Total number of cycles that the CPU has spent unscheduled due to idling | 532system.cpu.rob.rob_reads 40172 # The number of ROB reads 533system.cpu.rob.rob_writes 43025 # The number of ROB writes 534system.cpu.timesIdled 166 # Number of times that the entire CPU went into an idle state and unscheduled itself 535system.cpu.idleCycles 17888 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 537system.cpu.committedInsts 5380 # Number of Instructions Simulated 538system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated | 536system.cpu.committedInsts 5380 # Number of Instructions Simulated 537system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated |
| 539system.cpu.cpi 7.439405 # CPI: Cycles Per Instruction 540system.cpu.cpi_total 7.439405 # CPI: Total CPI of All Threads 541system.cpu.ipc 0.134419 # IPC: Instructions Per Cycle 542system.cpu.ipc_total 0.134419 # IPC: Total IPC of All Threads 543system.cpu.int_regfile_reads 20731 # number of integer regfile reads 544system.cpu.int_regfile_writes 12356 # number of integer regfile writes | 538system.cpu.cpi 7.365613 # CPI: Cycles Per Instruction 539system.cpu.cpi_total 7.365613 # CPI: Total CPI of All Threads 540system.cpu.ipc 0.135766 # IPC: Instructions Per Cycle 541system.cpu.ipc_total 0.135766 # IPC: Total IPC of All Threads 542system.cpu.int_regfile_reads 20766 # number of integer regfile reads 543system.cpu.int_regfile_writes 12432 # number of integer regfile writes |
| 545system.cpu.fp_regfile_reads 4 # number of floating regfile reads | 544system.cpu.fp_regfile_reads 4 # number of floating regfile reads |
| 546system.cpu.cc_regfile_reads 8007 # number of cc regfile reads 547system.cpu.cc_regfile_writes 4854 # number of cc regfile writes 548system.cpu.misc_regfile_reads 7133 # number of misc regfile reads | 545system.cpu.cc_regfile_reads 8051 # number of cc regfile reads 546system.cpu.cc_regfile_writes 4869 # number of cc regfile writes 547system.cpu.misc_regfile_reads 7177 # number of misc regfile reads |
| 549system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 548system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 550system.cpu.toL2Bus.throughput 1330435000 # Throughput (bytes/s) 551system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution 552system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution | 549system.cpu.toL2Bus.throughput 1346994398 # Throughput (bytes/s) 550system.cpu.toL2Bus.trans_dist::ReadReq 341 # Transaction distribution 551system.cpu.toL2Bus.trans_dist::ReadResp 340 # Transaction distribution |
| 553system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution 554system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution | 552system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution 553system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution |
| 555system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 548 # Packet count per connected master and slave (bytes) | 554system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550 # Packet count per connected master and slave (bytes) |
| 556system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) | 555system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) |
| 557system.cpu.toL2Bus.pkt_count::total 833 # Packet count per connected master and slave (bytes) 558system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17536 # Cumulative packet size per connected master and slave (bytes) | 556system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) 557system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) |
| 559system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) | 558system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) |
| 560system.cpu.toL2Bus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) 561system.cpu.toL2Bus.data_through_bus 26624 # Total data (bytes) | 559system.cpu.toL2Bus.tot_pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) 560system.cpu.toL2Bus.data_through_bus 26688 # Total data (bytes) |
| 562system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 561system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 563system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) 564system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 565system.cpu.toL2Bus.respLayer0.occupancy 459500 # Layer occupancy (ticks) | 562system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) 563system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 564system.cpu.toL2Bus.respLayer0.occupancy 461000 # Layer occupancy (ticks) |
| 566system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) | 565system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) |
| 567system.cpu.toL2Bus.respLayer1.occupancy 236250 # Layer occupancy (ticks) | 566system.cpu.toL2Bus.respLayer1.occupancy 236000 # Layer occupancy (ticks) |
| 568system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 569system.cpu.icache.tags.replacements 0 # number of replacements | 567system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 568system.cpu.icache.tags.replacements 0 # number of replacements |
| 570system.cpu.icache.tags.tagsinuse 130.942440 # Cycle average of tags in use 571system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks. 572system.cpu.icache.tags.sampled_refs 274 # Sample count of references to valid blocks. 573system.cpu.icache.tags.avg_refs 5.875912 # Average number of references to valid blocks. | 569system.cpu.icache.tags.tagsinuse 131.410773 # Cycle average of tags in use 570system.cpu.icache.tags.total_refs 1641 # Total number of references to valid blocks. 571system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks. 572system.cpu.icache.tags.avg_refs 5.967273 # Average number of references to valid blocks. |
| 574system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 573system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 575system.cpu.icache.tags.occ_blocks::cpu.inst 130.942440 # Average occupied blocks per requestor 576system.cpu.icache.tags.occ_percent::cpu.inst 0.063937 # Average percentage of cache occupancy 577system.cpu.icache.tags.occ_percent::total 0.063937 # Average percentage of cache occupancy 578system.cpu.icache.tags.occ_task_id_blocks::1024 274 # Occupied blocks per task id 579system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id 580system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id 581system.cpu.icache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id 582system.cpu.icache.tags.tag_accesses 4236 # Number of tag accesses 583system.cpu.icache.tags.data_accesses 4236 # Number of data accesses 584system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits 585system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits 586system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits 587system.cpu.icache.demand_hits::total 1610 # number of demand (read+write) hits 588system.cpu.icache.overall_hits::cpu.inst 1610 # number of overall hits 589system.cpu.icache.overall_hits::total 1610 # number of overall hits 590system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses 591system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses 592system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses 593system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses 594system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses 595system.cpu.icache.overall_misses::total 371 # number of overall misses 596system.cpu.icache.ReadReq_miss_latency::cpu.inst 25106250 # number of ReadReq miss cycles 597system.cpu.icache.ReadReq_miss_latency::total 25106250 # number of ReadReq miss cycles 598system.cpu.icache.demand_miss_latency::cpu.inst 25106250 # number of demand (read+write) miss cycles 599system.cpu.icache.demand_miss_latency::total 25106250 # number of demand (read+write) miss cycles 600system.cpu.icache.overall_miss_latency::cpu.inst 25106250 # number of overall miss cycles 601system.cpu.icache.overall_miss_latency::total 25106250 # number of overall miss cycles 602system.cpu.icache.ReadReq_accesses::cpu.inst 1981 # number of ReadReq accesses(hits+misses) 603system.cpu.icache.ReadReq_accesses::total 1981 # number of ReadReq accesses(hits+misses) 604system.cpu.icache.demand_accesses::cpu.inst 1981 # number of demand (read+write) accesses 605system.cpu.icache.demand_accesses::total 1981 # number of demand (read+write) accesses 606system.cpu.icache.overall_accesses::cpu.inst 1981 # number of overall (read+write) accesses 607system.cpu.icache.overall_accesses::total 1981 # number of overall (read+write) accesses 608system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187279 # miss rate for ReadReq accesses 609system.cpu.icache.ReadReq_miss_rate::total 0.187279 # miss rate for ReadReq accesses 610system.cpu.icache.demand_miss_rate::cpu.inst 0.187279 # miss rate for demand accesses 611system.cpu.icache.demand_miss_rate::total 0.187279 # miss rate for demand accesses 612system.cpu.icache.overall_miss_rate::cpu.inst 0.187279 # miss rate for overall accesses 613system.cpu.icache.overall_miss_rate::total 0.187279 # miss rate for overall accesses 614system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67671.832884 # average ReadReq miss latency 615system.cpu.icache.ReadReq_avg_miss_latency::total 67671.832884 # average ReadReq miss latency 616system.cpu.icache.demand_avg_miss_latency::cpu.inst 67671.832884 # average overall miss latency 617system.cpu.icache.demand_avg_miss_latency::total 67671.832884 # average overall miss latency 618system.cpu.icache.overall_avg_miss_latency::cpu.inst 67671.832884 # average overall miss latency 619system.cpu.icache.overall_avg_miss_latency::total 67671.832884 # average overall miss latency 620system.cpu.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked | 574system.cpu.icache.tags.occ_blocks::cpu.inst 131.410773 # Average occupied blocks per requestor 575system.cpu.icache.tags.occ_percent::cpu.inst 0.064165 # Average percentage of cache occupancy 576system.cpu.icache.tags.occ_percent::total 0.064165 # Average percentage of cache occupancy 577system.cpu.icache.tags.occ_task_id_blocks::1024 275 # Occupied blocks per task id 578system.cpu.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id 579system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 580system.cpu.icache.tags.occ_task_id_percent::1024 0.134277 # Percentage of cache occupancy per task id 581system.cpu.icache.tags.tag_accesses 4301 # Number of tag accesses 582system.cpu.icache.tags.data_accesses 4301 # Number of data accesses 583system.cpu.icache.ReadReq_hits::cpu.inst 1641 # number of ReadReq hits 584system.cpu.icache.ReadReq_hits::total 1641 # number of ReadReq hits 585system.cpu.icache.demand_hits::cpu.inst 1641 # number of demand (read+write) hits 586system.cpu.icache.demand_hits::total 1641 # number of demand (read+write) hits 587system.cpu.icache.overall_hits::cpu.inst 1641 # number of overall hits 588system.cpu.icache.overall_hits::total 1641 # number of overall hits 589system.cpu.icache.ReadReq_misses::cpu.inst 372 # number of ReadReq misses 590system.cpu.icache.ReadReq_misses::total 372 # number of ReadReq misses 591system.cpu.icache.demand_misses::cpu.inst 372 # number of demand (read+write) misses 592system.cpu.icache.demand_misses::total 372 # number of demand (read+write) misses 593system.cpu.icache.overall_misses::cpu.inst 372 # number of overall misses 594system.cpu.icache.overall_misses::total 372 # number of overall misses 595system.cpu.icache.ReadReq_miss_latency::cpu.inst 25012250 # number of ReadReq miss cycles 596system.cpu.icache.ReadReq_miss_latency::total 25012250 # number of ReadReq miss cycles 597system.cpu.icache.demand_miss_latency::cpu.inst 25012250 # number of demand (read+write) miss cycles 598system.cpu.icache.demand_miss_latency::total 25012250 # number of demand (read+write) miss cycles 599system.cpu.icache.overall_miss_latency::cpu.inst 25012250 # number of overall miss cycles 600system.cpu.icache.overall_miss_latency::total 25012250 # number of overall miss cycles 601system.cpu.icache.ReadReq_accesses::cpu.inst 2013 # number of ReadReq accesses(hits+misses) 602system.cpu.icache.ReadReq_accesses::total 2013 # number of ReadReq accesses(hits+misses) 603system.cpu.icache.demand_accesses::cpu.inst 2013 # number of demand (read+write) accesses 604system.cpu.icache.demand_accesses::total 2013 # number of demand (read+write) accesses 605system.cpu.icache.overall_accesses::cpu.inst 2013 # number of overall (read+write) accesses 606system.cpu.icache.overall_accesses::total 2013 # number of overall (read+write) accesses 607system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184799 # miss rate for ReadReq accesses 608system.cpu.icache.ReadReq_miss_rate::total 0.184799 # miss rate for ReadReq accesses 609system.cpu.icache.demand_miss_rate::cpu.inst 0.184799 # miss rate for demand accesses 610system.cpu.icache.demand_miss_rate::total 0.184799 # miss rate for demand accesses 611system.cpu.icache.overall_miss_rate::cpu.inst 0.184799 # miss rate for overall accesses 612system.cpu.icache.overall_miss_rate::total 0.184799 # miss rate for overall accesses 613system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67237.231183 # average ReadReq miss latency 614system.cpu.icache.ReadReq_avg_miss_latency::total 67237.231183 # average ReadReq miss latency 615system.cpu.icache.demand_avg_miss_latency::cpu.inst 67237.231183 # average overall miss latency 616system.cpu.icache.demand_avg_miss_latency::total 67237.231183 # average overall miss latency 617system.cpu.icache.overall_avg_miss_latency::cpu.inst 67237.231183 # average overall miss latency 618system.cpu.icache.overall_avg_miss_latency::total 67237.231183 # average overall miss latency 619system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 621system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 620system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 622system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked | 621system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 623system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 622system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 624system.cpu.icache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked | 623system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 625system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 626system.cpu.icache.fast_writes 0 # number of fast writes performed 627system.cpu.icache.cache_copies 0 # number of cache copies performed 628system.cpu.icache.ReadReq_mshr_hits::cpu.inst 97 # number of ReadReq MSHR hits 629system.cpu.icache.ReadReq_mshr_hits::total 97 # number of ReadReq MSHR hits 630system.cpu.icache.demand_mshr_hits::cpu.inst 97 # number of demand (read+write) MSHR hits 631system.cpu.icache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits 632system.cpu.icache.overall_mshr_hits::cpu.inst 97 # number of overall MSHR hits 633system.cpu.icache.overall_mshr_hits::total 97 # number of overall MSHR hits | 624system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 625system.cpu.icache.fast_writes 0 # number of fast writes performed 626system.cpu.icache.cache_copies 0 # number of cache copies performed 627system.cpu.icache.ReadReq_mshr_hits::cpu.inst 97 # number of ReadReq MSHR hits 628system.cpu.icache.ReadReq_mshr_hits::total 97 # number of ReadReq MSHR hits 629system.cpu.icache.demand_mshr_hits::cpu.inst 97 # number of demand (read+write) MSHR hits 630system.cpu.icache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits 631system.cpu.icache.overall_mshr_hits::cpu.inst 97 # number of overall MSHR hits 632system.cpu.icache.overall_mshr_hits::total 97 # number of overall MSHR hits |
| 634system.cpu.icache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses 635system.cpu.icache.ReadReq_mshr_misses::total 274 # number of ReadReq MSHR misses 636system.cpu.icache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses 637system.cpu.icache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses 638system.cpu.icache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses 639system.cpu.icache.overall_mshr_misses::total 274 # number of overall MSHR misses 640system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19660000 # number of ReadReq MSHR miss cycles 641system.cpu.icache.ReadReq_mshr_miss_latency::total 19660000 # number of ReadReq MSHR miss cycles 642system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19660000 # number of demand (read+write) MSHR miss cycles 643system.cpu.icache.demand_mshr_miss_latency::total 19660000 # number of demand (read+write) MSHR miss cycles 644system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19660000 # number of overall MSHR miss cycles 645system.cpu.icache.overall_mshr_miss_latency::total 19660000 # number of overall MSHR miss cycles 646system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for ReadReq accesses 647system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138314 # mshr miss rate for ReadReq accesses 648system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for demand accesses 649system.cpu.icache.demand_mshr_miss_rate::total 0.138314 # mshr miss rate for demand accesses 650system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for overall accesses 651system.cpu.icache.overall_mshr_miss_rate::total 0.138314 # mshr miss rate for overall accesses 652system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71751.824818 # average ReadReq mshr miss latency 653system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71751.824818 # average ReadReq mshr miss latency 654system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71751.824818 # average overall mshr miss latency 655system.cpu.icache.demand_avg_mshr_miss_latency::total 71751.824818 # average overall mshr miss latency 656system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71751.824818 # average overall mshr miss latency 657system.cpu.icache.overall_avg_mshr_miss_latency::total 71751.824818 # average overall mshr miss latency | 633system.cpu.icache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses 634system.cpu.icache.ReadReq_mshr_misses::total 275 # number of ReadReq MSHR misses 635system.cpu.icache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses 636system.cpu.icache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses 637system.cpu.icache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses 638system.cpu.icache.overall_mshr_misses::total 275 # number of overall MSHR misses 639system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19562000 # number of ReadReq MSHR miss cycles 640system.cpu.icache.ReadReq_mshr_miss_latency::total 19562000 # number of ReadReq MSHR miss cycles 641system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19562000 # number of demand (read+write) MSHR miss cycles 642system.cpu.icache.demand_mshr_miss_latency::total 19562000 # number of demand (read+write) MSHR miss cycles 643system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19562000 # number of overall MSHR miss cycles 644system.cpu.icache.overall_mshr_miss_latency::total 19562000 # number of overall MSHR miss cycles 645system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136612 # mshr miss rate for ReadReq accesses 646system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136612 # mshr miss rate for ReadReq accesses 647system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136612 # mshr miss rate for demand accesses 648system.cpu.icache.demand_mshr_miss_rate::total 0.136612 # mshr miss rate for demand accesses 649system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136612 # mshr miss rate for overall accesses 650system.cpu.icache.overall_mshr_miss_rate::total 0.136612 # mshr miss rate for overall accesses 651system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71134.545455 # average ReadReq mshr miss latency 652system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71134.545455 # average ReadReq mshr miss latency 653system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71134.545455 # average overall mshr miss latency 654system.cpu.icache.demand_avg_mshr_miss_latency::total 71134.545455 # average overall mshr miss latency 655system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71134.545455 # average overall mshr miss latency 656system.cpu.icache.overall_avg_mshr_miss_latency::total 71134.545455 # average overall mshr miss latency |
| 658system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 659system.cpu.l2cache.tags.replacements 0 # number of replacements | 657system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 658system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 660system.cpu.l2cache.tags.tagsinuse 163.759335 # Cycle average of tags in use 661system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 662system.cpu.l2cache.tags.sampled_refs 337 # Sample count of references to valid blocks. 663system.cpu.l2cache.tags.avg_refs 0.005935 # Average number of references to valid blocks. | 659system.cpu.l2cache.tags.tagsinuse 164.472388 # Cycle average of tags in use 660system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 661system.cpu.l2cache.tags.sampled_refs 339 # Sample count of references to valid blocks. 662system.cpu.l2cache.tags.avg_refs 0.002950 # Average number of references to valid blocks. |
| 664system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 663system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 665system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.011600 # Average occupied blocks per requestor 666system.cpu.l2cache.tags.occ_blocks::cpu.data 32.747734 # Average occupied blocks per requestor 667system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003998 # Average percentage of cache occupancy 668system.cpu.l2cache.tags.occ_percent::cpu.data 0.000999 # Average percentage of cache occupancy 669system.cpu.l2cache.tags.occ_percent::total 0.004998 # Average percentage of cache occupancy 670system.cpu.l2cache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id 671system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 672system.cpu.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id 673system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010284 # Percentage of cache occupancy per task id 674system.cpu.l2cache.tags.tag_accesses 3750 # Number of tag accesses 675system.cpu.l2cache.tags.data_accesses 3750 # Number of data accesses | 664system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.481156 # Average occupied blocks per requestor 665system.cpu.l2cache.tags.occ_blocks::cpu.data 32.991232 # Average occupied blocks per requestor 666system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004012 # Average percentage of cache occupancy 667system.cpu.l2cache.tags.occ_percent::cpu.data 0.001007 # Average percentage of cache occupancy 668system.cpu.l2cache.tags.occ_percent::total 0.005019 # Average percentage of cache occupancy 669system.cpu.l2cache.tags.occ_task_id_blocks::1024 339 # Occupied blocks per task id 670system.cpu.l2cache.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id 671system.cpu.l2cache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id 672system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010345 # Percentage of cache occupancy per task id 673system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses 674system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses |
| 676system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits | 675system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits |
| 677system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 678system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits | 676system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits |
| 679system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits | 677system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits |
| 680system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 681system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits | 678system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits |
| 682system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits | 679system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits |
| 683system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 684system.cpu.l2cache.overall_hits::total 2 # number of overall hits 685system.cpu.l2cache.ReadReq_misses::cpu.inst 273 # number of ReadReq misses 686system.cpu.l2cache.ReadReq_misses::cpu.data 65 # number of ReadReq misses 687system.cpu.l2cache.ReadReq_misses::total 338 # number of ReadReq misses | 680system.cpu.l2cache.overall_hits::total 1 # number of overall hits 681system.cpu.l2cache.ReadReq_misses::cpu.inst 274 # number of ReadReq misses 682system.cpu.l2cache.ReadReq_misses::cpu.data 66 # number of ReadReq misses 683system.cpu.l2cache.ReadReq_misses::total 340 # number of ReadReq misses |
| 688system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses 689system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses | 684system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses 685system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses |
| 690system.cpu.l2cache.demand_misses::cpu.inst 273 # number of demand (read+write) misses 691system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 692system.cpu.l2cache.demand_misses::total 415 # number of demand (read+write) misses 693system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses 694system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 695system.cpu.l2cache.overall_misses::total 415 # number of overall misses 696system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19374500 # number of ReadReq miss cycles 697system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5212250 # number of ReadReq miss cycles 698system.cpu.l2cache.ReadReq_miss_latency::total 24586750 # number of ReadReq miss cycles 699system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5445500 # number of ReadExReq miss cycles 700system.cpu.l2cache.ReadExReq_miss_latency::total 5445500 # number of ReadExReq miss cycles 701system.cpu.l2cache.demand_miss_latency::cpu.inst 19374500 # number of demand (read+write) miss cycles 702system.cpu.l2cache.demand_miss_latency::cpu.data 10657750 # number of demand (read+write) miss cycles 703system.cpu.l2cache.demand_miss_latency::total 30032250 # number of demand (read+write) miss cycles 704system.cpu.l2cache.overall_miss_latency::cpu.inst 19374500 # number of overall miss cycles 705system.cpu.l2cache.overall_miss_latency::cpu.data 10657750 # number of overall miss cycles 706system.cpu.l2cache.overall_miss_latency::total 30032250 # number of overall miss cycles 707system.cpu.l2cache.ReadReq_accesses::cpu.inst 274 # number of ReadReq accesses(hits+misses) | 686system.cpu.l2cache.demand_misses::cpu.inst 274 # number of demand (read+write) misses 687system.cpu.l2cache.demand_misses::cpu.data 143 # number of demand (read+write) misses 688system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses 689system.cpu.l2cache.overall_misses::cpu.inst 274 # number of overall misses 690system.cpu.l2cache.overall_misses::cpu.data 143 # number of overall misses 691system.cpu.l2cache.overall_misses::total 417 # number of overall misses 692system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19276500 # number of ReadReq miss cycles 693system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5050250 # number of ReadReq miss cycles 694system.cpu.l2cache.ReadReq_miss_latency::total 24326750 # number of ReadReq miss cycles 695system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5454250 # number of ReadExReq miss cycles 696system.cpu.l2cache.ReadExReq_miss_latency::total 5454250 # number of ReadExReq miss cycles 697system.cpu.l2cache.demand_miss_latency::cpu.inst 19276500 # number of demand (read+write) miss cycles 698system.cpu.l2cache.demand_miss_latency::cpu.data 10504500 # number of demand (read+write) miss cycles 699system.cpu.l2cache.demand_miss_latency::total 29781000 # number of demand (read+write) miss cycles 700system.cpu.l2cache.overall_miss_latency::cpu.inst 19276500 # number of overall miss cycles 701system.cpu.l2cache.overall_miss_latency::cpu.data 10504500 # number of overall miss cycles 702system.cpu.l2cache.overall_miss_latency::total 29781000 # number of overall miss cycles 703system.cpu.l2cache.ReadReq_accesses::cpu.inst 275 # number of ReadReq accesses(hits+misses) |
| 708system.cpu.l2cache.ReadReq_accesses::cpu.data 66 # number of ReadReq accesses(hits+misses) | 704system.cpu.l2cache.ReadReq_accesses::cpu.data 66 # number of ReadReq accesses(hits+misses) |
| 709system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) | 705system.cpu.l2cache.ReadReq_accesses::total 341 # number of ReadReq accesses(hits+misses) |
| 710system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses) 711system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses) | 706system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses) 707system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses) |
| 712system.cpu.l2cache.demand_accesses::cpu.inst 274 # number of demand (read+write) accesses | 708system.cpu.l2cache.demand_accesses::cpu.inst 275 # number of demand (read+write) accesses |
| 713system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses | 709system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses |
| 714system.cpu.l2cache.demand_accesses::total 417 # number of demand (read+write) accesses 715system.cpu.l2cache.overall_accesses::cpu.inst 274 # number of overall (read+write) accesses | 710system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses 711system.cpu.l2cache.overall_accesses::cpu.inst 275 # number of overall (read+write) accesses |
| 716system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses | 712system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses |
| 717system.cpu.l2cache.overall_accesses::total 417 # number of overall (read+write) accesses 718system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996350 # miss rate for ReadReq accesses 719system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.984848 # miss rate for ReadReq accesses 720system.cpu.l2cache.ReadReq_miss_rate::total 0.994118 # miss rate for ReadReq accesses | 713system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses 714system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996364 # miss rate for ReadReq accesses 715system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 716system.cpu.l2cache.ReadReq_miss_rate::total 0.997067 # miss rate for ReadReq accesses |
| 721system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 722system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 717system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 718system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 723system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996350 # miss rate for demand accesses 724system.cpu.l2cache.demand_miss_rate::cpu.data 0.993007 # miss rate for demand accesses 725system.cpu.l2cache.demand_miss_rate::total 0.995204 # miss rate for demand accesses 726system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996350 # miss rate for overall accesses 727system.cpu.l2cache.overall_miss_rate::cpu.data 0.993007 # miss rate for overall accesses 728system.cpu.l2cache.overall_miss_rate::total 0.995204 # miss rate for overall accesses 729system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70968.864469 # average ReadReq miss latency 730system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80188.461538 # average ReadReq miss latency 731system.cpu.l2cache.ReadReq_avg_miss_latency::total 72741.863905 # average ReadReq miss latency 732system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70720.779221 # average ReadExReq miss latency 733system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70720.779221 # average ReadExReq miss latency 734system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70968.864469 # average overall miss latency 735system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75054.577465 # average overall miss latency 736system.cpu.l2cache.demand_avg_miss_latency::total 72366.867470 # average overall miss latency 737system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70968.864469 # average overall miss latency 738system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75054.577465 # average overall miss latency 739system.cpu.l2cache.overall_avg_miss_latency::total 72366.867470 # average overall miss latency | 719system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996364 # miss rate for demand accesses 720system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 721system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses 722system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996364 # miss rate for overall accesses 723system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 724system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses 725system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70352.189781 # average ReadReq miss latency 726system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76518.939394 # average ReadReq miss latency 727system.cpu.l2cache.ReadReq_avg_miss_latency::total 71549.264706 # average ReadReq miss latency 728system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70834.415584 # average ReadExReq miss latency 729system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70834.415584 # average ReadExReq miss latency 730system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70352.189781 # average overall miss latency 731system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73458.041958 # average overall miss latency 732system.cpu.l2cache.demand_avg_miss_latency::total 71417.266187 # average overall miss latency 733system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70352.189781 # average overall miss latency 734system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73458.041958 # average overall miss latency 735system.cpu.l2cache.overall_avg_miss_latency::total 71417.266187 # average overall miss latency |
| 740system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 741system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 742system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 743system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 744system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 745system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 746system.cpu.l2cache.fast_writes 0 # number of fast writes performed 747system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 736system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 737system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 738system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 739system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 740system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 741system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 742system.cpu.l2cache.fast_writes 0 # number of fast writes performed 743system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 748system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses 749system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 750system.cpu.l2cache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses | 744system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses 745system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses 746system.cpu.l2cache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses |
| 751system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses 752system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses | 747system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses 748system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses |
| 753system.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses 754system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 755system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses 756system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses 757system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 758system.cpu.l2cache.overall_mshr_misses::total 415 # number of overall MSHR misses 759system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15946000 # number of ReadReq MSHR miss cycles 760system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4413250 # number of ReadReq MSHR miss cycles 761system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20359250 # number of ReadReq MSHR miss cycles 762system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4486000 # number of ReadExReq MSHR miss cycles 763system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4486000 # number of ReadExReq MSHR miss cycles 764system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15946000 # number of demand (read+write) MSHR miss cycles 765system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8899250 # number of demand (read+write) MSHR miss cycles 766system.cpu.l2cache.demand_mshr_miss_latency::total 24845250 # number of demand (read+write) MSHR miss cycles 767system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15946000 # number of overall MSHR miss cycles 768system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8899250 # number of overall MSHR miss cycles 769system.cpu.l2cache.overall_mshr_miss_latency::total 24845250 # number of overall MSHR miss cycles 770system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for ReadReq accesses 771system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.984848 # mshr miss rate for ReadReq accesses 772system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994118 # mshr miss rate for ReadReq accesses | 749system.cpu.l2cache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses 750system.cpu.l2cache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses 751system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses 752system.cpu.l2cache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses 753system.cpu.l2cache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses 754system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses 755system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15837000 # number of ReadReq MSHR miss cycles 756system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4238250 # number of ReadReq MSHR miss cycles 757system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20075250 # number of ReadReq MSHR miss cycles 758system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4493750 # number of ReadExReq MSHR miss cycles 759system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4493750 # number of ReadExReq MSHR miss cycles 760system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15837000 # number of demand (read+write) MSHR miss cycles 761system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8732000 # number of demand (read+write) MSHR miss cycles 762system.cpu.l2cache.demand_mshr_miss_latency::total 24569000 # number of demand (read+write) MSHR miss cycles 763system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15837000 # number of overall MSHR miss cycles 764system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8732000 # number of overall MSHR miss cycles 765system.cpu.l2cache.overall_mshr_miss_latency::total 24569000 # number of overall MSHR miss cycles 766system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for ReadReq accesses 767system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 768system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997067 # mshr miss rate for ReadReq accesses |
| 773system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 774system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 769system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 770system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 775system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for demand accesses 776system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for demand accesses 777system.cpu.l2cache.demand_mshr_miss_rate::total 0.995204 # mshr miss rate for demand accesses 778system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses 779system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for overall accesses 780system.cpu.l2cache.overall_mshr_miss_rate::total 0.995204 # mshr miss rate for overall accesses 781system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58410.256410 # average ReadReq mshr miss latency 782system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67896.153846 # average ReadReq mshr miss latency 783system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60234.467456 # average ReadReq mshr miss latency 784system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58259.740260 # average ReadExReq mshr miss latency 785system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58259.740260 # average ReadExReq mshr miss latency 786system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58410.256410 # average overall mshr miss latency 787system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62670.774648 # average overall mshr miss latency 788system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59868.072289 # average overall mshr miss latency 789system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58410.256410 # average overall mshr miss latency 790system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62670.774648 # average overall mshr miss latency 791system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59868.072289 # average overall mshr miss latency | 771system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for demand accesses 772system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 773system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses 774system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for overall accesses 775system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 776system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses 777system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57799.270073 # average ReadReq mshr miss latency 778system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64215.909091 # average ReadReq mshr miss latency 779system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59044.852941 # average ReadReq mshr miss latency 780system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58360.389610 # average ReadExReq mshr miss latency 781system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58360.389610 # average ReadExReq mshr miss latency 782system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57799.270073 # average overall mshr miss latency 783system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61062.937063 # average overall mshr miss latency 784system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58918.465228 # average overall mshr miss latency 785system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57799.270073 # average overall mshr miss latency 786system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61062.937063 # average overall mshr miss latency 787system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58918.465228 # average overall mshr miss latency |
| 792system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 793system.cpu.dcache.tags.replacements 0 # number of replacements | 788system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 789system.cpu.dcache.tags.replacements 0 # number of replacements |
| 794system.cpu.dcache.tags.tagsinuse 83.261165 # Cycle average of tags in use 795system.cpu.dcache.tags.total_refs 2335 # Total number of references to valid blocks. | 790system.cpu.dcache.tags.tagsinuse 83.263820 # Cycle average of tags in use 791system.cpu.dcache.tags.total_refs 2308 # Total number of references to valid blocks. |
| 796system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. | 792system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. |
| 797system.cpu.dcache.tags.avg_refs 16.443662 # Average number of references to valid blocks. | 793system.cpu.dcache.tags.avg_refs 16.253521 # Average number of references to valid blocks. |
| 798system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 794system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 799system.cpu.dcache.tags.occ_blocks::cpu.data 83.261165 # Average occupied blocks per requestor 800system.cpu.dcache.tags.occ_percent::cpu.data 0.020327 # Average percentage of cache occupancy 801system.cpu.dcache.tags.occ_percent::total 0.020327 # Average percentage of cache occupancy | 795system.cpu.dcache.tags.occ_blocks::cpu.data 83.263820 # Average occupied blocks per requestor 796system.cpu.dcache.tags.occ_percent::cpu.data 0.020328 # Average percentage of cache occupancy 797system.cpu.dcache.tags.occ_percent::total 0.020328 # Average percentage of cache occupancy |
| 802system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id | 798system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id |
| 803system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 804system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id | 799system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 800system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id |
| 805system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id | 801system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id |
| 806system.cpu.dcache.tags.tag_accesses 5232 # Number of tag accesses 807system.cpu.dcache.tags.data_accesses 5232 # Number of data accesses 808system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits 809system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits | 802system.cpu.dcache.tags.tag_accesses 5178 # Number of tag accesses 803system.cpu.dcache.tags.data_accesses 5178 # Number of data accesses 804system.cpu.dcache.ReadReq_hits::cpu.data 1450 # number of ReadReq hits 805system.cpu.dcache.ReadReq_hits::total 1450 # number of ReadReq hits |
| 810system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits 811system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits | 806system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits 807system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits |
| 812system.cpu.dcache.demand_hits::cpu.data 2335 # number of demand (read+write) hits 813system.cpu.dcache.demand_hits::total 2335 # number of demand (read+write) hits 814system.cpu.dcache.overall_hits::cpu.data 2335 # number of overall hits 815system.cpu.dcache.overall_hits::total 2335 # number of overall hits | 808system.cpu.dcache.demand_hits::cpu.data 2308 # number of demand (read+write) hits 809system.cpu.dcache.demand_hits::total 2308 # number of demand (read+write) hits 810system.cpu.dcache.overall_hits::cpu.data 2308 # number of overall hits 811system.cpu.dcache.overall_hits::total 2308 # number of overall hits |
| 816system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses 817system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses 818system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses 819system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses 820system.cpu.dcache.demand_misses::cpu.data 210 # number of demand (read+write) misses 821system.cpu.dcache.demand_misses::total 210 # number of demand (read+write) misses 822system.cpu.dcache.overall_misses::cpu.data 210 # number of overall misses 823system.cpu.dcache.overall_misses::total 210 # number of overall misses | 812system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses 813system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses 814system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses 815system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses 816system.cpu.dcache.demand_misses::cpu.data 210 # number of demand (read+write) misses 817system.cpu.dcache.demand_misses::total 210 # number of demand (read+write) misses 818system.cpu.dcache.overall_misses::cpu.data 210 # number of overall misses 819system.cpu.dcache.overall_misses::total 210 # number of overall misses |
| 824system.cpu.dcache.ReadReq_miss_latency::cpu.data 9645750 # number of ReadReq miss cycles 825system.cpu.dcache.ReadReq_miss_latency::total 9645750 # number of ReadReq miss cycles 826system.cpu.dcache.WriteReq_miss_latency::cpu.data 5703500 # number of WriteReq miss cycles 827system.cpu.dcache.WriteReq_miss_latency::total 5703500 # number of WriteReq miss cycles 828system.cpu.dcache.demand_miss_latency::cpu.data 15349250 # number of demand (read+write) miss cycles 829system.cpu.dcache.demand_miss_latency::total 15349250 # number of demand (read+write) miss cycles 830system.cpu.dcache.overall_miss_latency::cpu.data 15349250 # number of overall miss cycles 831system.cpu.dcache.overall_miss_latency::total 15349250 # number of overall miss cycles 832system.cpu.dcache.ReadReq_accesses::cpu.data 1610 # number of ReadReq accesses(hits+misses) 833system.cpu.dcache.ReadReq_accesses::total 1610 # number of ReadReq accesses(hits+misses) | 820system.cpu.dcache.ReadReq_miss_latency::cpu.data 9474500 # number of ReadReq miss cycles 821system.cpu.dcache.ReadReq_miss_latency::total 9474500 # number of ReadReq miss cycles 822system.cpu.dcache.WriteReq_miss_latency::cpu.data 5711750 # number of WriteReq miss cycles 823system.cpu.dcache.WriteReq_miss_latency::total 5711750 # number of WriteReq miss cycles 824system.cpu.dcache.demand_miss_latency::cpu.data 15186250 # number of demand (read+write) miss cycles 825system.cpu.dcache.demand_miss_latency::total 15186250 # number of demand (read+write) miss cycles 826system.cpu.dcache.overall_miss_latency::cpu.data 15186250 # number of overall miss cycles 827system.cpu.dcache.overall_miss_latency::total 15186250 # number of overall miss cycles 828system.cpu.dcache.ReadReq_accesses::cpu.data 1583 # number of ReadReq accesses(hits+misses) 829system.cpu.dcache.ReadReq_accesses::total 1583 # number of ReadReq accesses(hits+misses) |
| 834system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 835system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) | 830system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 831system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) |
| 836system.cpu.dcache.demand_accesses::cpu.data 2545 # number of demand (read+write) accesses 837system.cpu.dcache.demand_accesses::total 2545 # number of demand (read+write) accesses 838system.cpu.dcache.overall_accesses::cpu.data 2545 # number of overall (read+write) accesses 839system.cpu.dcache.overall_accesses::total 2545 # number of overall (read+write) accesses 840system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082609 # miss rate for ReadReq accesses 841system.cpu.dcache.ReadReq_miss_rate::total 0.082609 # miss rate for ReadReq accesses | 832system.cpu.dcache.demand_accesses::cpu.data 2518 # number of demand (read+write) accesses 833system.cpu.dcache.demand_accesses::total 2518 # number of demand (read+write) accesses 834system.cpu.dcache.overall_accesses::cpu.data 2518 # number of overall (read+write) accesses 835system.cpu.dcache.overall_accesses::total 2518 # number of overall (read+write) accesses 836system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084018 # miss rate for ReadReq accesses 837system.cpu.dcache.ReadReq_miss_rate::total 0.084018 # miss rate for ReadReq accesses |
| 842system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses 843system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses | 838system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses 839system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses |
| 844system.cpu.dcache.demand_miss_rate::cpu.data 0.082515 # miss rate for demand accesses 845system.cpu.dcache.demand_miss_rate::total 0.082515 # miss rate for demand accesses 846system.cpu.dcache.overall_miss_rate::cpu.data 0.082515 # miss rate for overall accesses 847system.cpu.dcache.overall_miss_rate::total 0.082515 # miss rate for overall accesses 848system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72524.436090 # average ReadReq miss latency 849system.cpu.dcache.ReadReq_avg_miss_latency::total 72524.436090 # average ReadReq miss latency 850system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74071.428571 # average WriteReq miss latency 851system.cpu.dcache.WriteReq_avg_miss_latency::total 74071.428571 # average WriteReq miss latency 852system.cpu.dcache.demand_avg_miss_latency::cpu.data 73091.666667 # average overall miss latency 853system.cpu.dcache.demand_avg_miss_latency::total 73091.666667 # average overall miss latency 854system.cpu.dcache.overall_avg_miss_latency::cpu.data 73091.666667 # average overall miss latency 855system.cpu.dcache.overall_avg_miss_latency::total 73091.666667 # average overall miss latency | 840system.cpu.dcache.demand_miss_rate::cpu.data 0.083400 # miss rate for demand accesses 841system.cpu.dcache.demand_miss_rate::total 0.083400 # miss rate for demand accesses 842system.cpu.dcache.overall_miss_rate::cpu.data 0.083400 # miss rate for overall accesses 843system.cpu.dcache.overall_miss_rate::total 0.083400 # miss rate for overall accesses 844system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71236.842105 # average ReadReq miss latency 845system.cpu.dcache.ReadReq_avg_miss_latency::total 71236.842105 # average ReadReq miss latency 846system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74178.571429 # average WriteReq miss latency 847system.cpu.dcache.WriteReq_avg_miss_latency::total 74178.571429 # average WriteReq miss latency 848system.cpu.dcache.demand_avg_miss_latency::cpu.data 72315.476190 # average overall miss latency 849system.cpu.dcache.demand_avg_miss_latency::total 72315.476190 # average overall miss latency 850system.cpu.dcache.overall_avg_miss_latency::cpu.data 72315.476190 # average overall miss latency 851system.cpu.dcache.overall_avg_miss_latency::total 72315.476190 # average overall miss latency |
| 856system.cpu.dcache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked 857system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 858system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 859system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 860system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.750000 # average number of cycles each access was blocked 861system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 862system.cpu.dcache.fast_writes 0 # number of fast writes performed 863system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 870system.cpu.dcache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses 871system.cpu.dcache.ReadReq_mshr_misses::total 66 # number of ReadReq MSHR misses 872system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses 873system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses 874system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses 875system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses 876system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses 877system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses | 852system.cpu.dcache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked 853system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 854system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 855system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 856system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.750000 # average number of cycles each access was blocked 857system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 858system.cpu.dcache.fast_writes 0 # number of fast writes performed 859system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 866system.cpu.dcache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses 867system.cpu.dcache.ReadReq_mshr_misses::total 66 # number of ReadReq MSHR misses 868system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses 869system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses 870system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses 871system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses 872system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses 873system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses |
| 878system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287250 # number of ReadReq MSHR miss cycles 879system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287250 # number of ReadReq MSHR miss cycles 880system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5522500 # number of WriteReq MSHR miss cycles 881system.cpu.dcache.WriteReq_mshr_miss_latency::total 5522500 # number of WriteReq MSHR miss cycles 882system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10809750 # number of demand (read+write) MSHR miss cycles 883system.cpu.dcache.demand_mshr_miss_latency::total 10809750 # number of demand (read+write) MSHR miss cycles 884system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10809750 # number of overall MSHR miss cycles 885system.cpu.dcache.overall_mshr_miss_latency::total 10809750 # number of overall MSHR miss cycles 886system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040994 # mshr miss rate for ReadReq accesses 887system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040994 # mshr miss rate for ReadReq accesses | 874system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5115250 # number of ReadReq MSHR miss cycles 875system.cpu.dcache.ReadReq_mshr_miss_latency::total 5115250 # number of ReadReq MSHR miss cycles 876system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5531250 # number of WriteReq MSHR miss cycles 877system.cpu.dcache.WriteReq_mshr_miss_latency::total 5531250 # number of WriteReq MSHR miss cycles 878system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10646500 # number of demand (read+write) MSHR miss cycles 879system.cpu.dcache.demand_mshr_miss_latency::total 10646500 # number of demand (read+write) MSHR miss cycles 880system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10646500 # number of overall MSHR miss cycles 881system.cpu.dcache.overall_mshr_miss_latency::total 10646500 # number of overall MSHR miss cycles 882system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041693 # mshr miss rate for ReadReq accesses 883system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041693 # mshr miss rate for ReadReq accesses |
| 888system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses 889system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses | 884system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses 885system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses |
| 890system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056189 # mshr miss rate for demand accesses 891system.cpu.dcache.demand_mshr_miss_rate::total 0.056189 # mshr miss rate for demand accesses 892system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056189 # mshr miss rate for overall accesses 893system.cpu.dcache.overall_mshr_miss_rate::total 0.056189 # mshr miss rate for overall accesses 894system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80109.848485 # average ReadReq mshr miss latency 895system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80109.848485 # average ReadReq mshr miss latency 896system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71720.779221 # average WriteReq mshr miss latency 897system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71720.779221 # average WriteReq mshr miss latency 898system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75592.657343 # average overall mshr miss latency 899system.cpu.dcache.demand_avg_mshr_miss_latency::total 75592.657343 # average overall mshr miss latency 900system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75592.657343 # average overall mshr miss latency 901system.cpu.dcache.overall_avg_mshr_miss_latency::total 75592.657343 # average overall mshr miss latency | 886system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056791 # mshr miss rate for demand accesses 887system.cpu.dcache.demand_mshr_miss_rate::total 0.056791 # mshr miss rate for demand accesses 888system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056791 # mshr miss rate for overall accesses 889system.cpu.dcache.overall_mshr_miss_rate::total 0.056791 # mshr miss rate for overall accesses 890system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77503.787879 # average ReadReq mshr miss latency 891system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77503.787879 # average ReadReq mshr miss latency 892system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71834.415584 # average WriteReq mshr miss latency 893system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71834.415584 # average WriteReq mshr miss latency 894system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74451.048951 # average overall mshr miss latency 895system.cpu.dcache.demand_avg_mshr_miss_latency::total 74451.048951 # average overall mshr miss latency 896system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74451.048951 # average overall mshr miss latency 897system.cpu.dcache.overall_avg_mshr_miss_latency::total 74451.048951 # average overall mshr miss latency |
| 902system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 903 904---------- End Simulation Statistics ---------- | 898system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 899 900---------- End Simulation Statistics ---------- |