| stats.txt (10148:4574d5882066) | stats.txt (10220:9eab5efc02e8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated |
| 4sim_ticks 20069500 # Number of ticks simulated 5final_tick 20069500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 20011500 # Number of ticks simulated 5final_tick 20011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 42536 # Simulator instruction rate (inst/s) 8host_op_rate 77054 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 158640887 # Simulator tick rate (ticks/s) 10host_mem_usage 283320 # Number of bytes of host memory used | 7host_inst_rate 41048 # Simulator instruction rate (inst/s) 8host_op_rate 74359 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 152650007 # Simulator tick rate (ticks/s) 10host_mem_usage 284392 # Number of bytes of host memory used |
| 11host_seconds 0.13 # Real time elapsed on the host 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26496 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 414 # Number of read requests responded to by this memory | 11host_seconds 0.13 # Real time elapsed on the host 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26496 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 414 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 870574753 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 449637510 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1320212262 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 870574753 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 870574753 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 870574753 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 449637510 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1320212262 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 873097969 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 450940709 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1324038678 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 873097969 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 873097969 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 873097969 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 450940709 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1324038678 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 415 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 415 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 20021000 # Total gap between requests | 78system.physmem.totGap 19963000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 415 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 415 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 71 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 240.676056 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 152.837127 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 281.987222 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 26 36.62% 36.62% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 26 36.62% 73.24% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 8 11.27% 84.51% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 2 2.82% 87.32% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::640-767 2 2.82% 90.14% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::896-1023 2 2.82% 92.96% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1024-1151 5 7.04% 100.00% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::total 71 # Bytes accessed per row activation 201system.physmem.totQLat 2360500 # Total ticks spent queuing 202system.physmem.totMemAccLat 12135500 # Total ticks spent from burst creation until serviced by the DRAM | 189system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 248.742268 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 161.697208 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 270.249471 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 33 34.02% 34.02% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 34 35.05% 69.07% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 13 13.40% 82.47% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 3 3.09% 85.57% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::640-767 6 6.19% 91.75% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::896-1023 3 3.09% 94.85% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation 201system.physmem.totQLat 4234000 # Total ticks spent queuing 202system.physmem.totMemAccLat 12015250 # Total ticks spent from burst creation until serviced by the DRAM |
| 203system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers | 203system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers |
| 204system.physmem.totBankLat 7700000 # Total ticks spent accessing banks 205system.physmem.avgQLat 5687.95 # Average queueing delay per DRAM burst 206system.physmem.avgBankLat 18554.22 # Average bank access latency per DRAM burst | 204system.physmem.avgQLat 10202.41 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 205system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 29242.17 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1323.40 # Average DRAM read bandwidth in MiByte/s | 206system.physmem.avgMemAccLat 28952.41 # Average memory access latency per DRAM burst 207system.physmem.avgRdBW 1327.24 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 208system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 1323.40 # Average system read bandwidth in MiByte/s | 209system.physmem.avgRdBWSys 1327.24 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 210system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 211system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 214system.physmem.busUtil 10.34 # Data bus utilization in percentage 215system.physmem.busUtilRead 10.34 # Data bus utilization in percentage for reads | 212system.physmem.busUtil 10.37 # Data bus utilization in percentage 213system.physmem.busUtilRead 10.37 # Data bus utilization in percentage for reads |
| 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 307 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 73.98 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 214system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 215system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing 216system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 217system.physmem.readRowHits 307 # Number of row buffer hits during reads 218system.physmem.writeRowHits 0 # Number of row buffer hits during writes 219system.physmem.readRowHitRate 73.98 # Row buffer hit rate for reads 220system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 48243.37 # Average gap between requests | 221system.physmem.avgGap 48103.61 # Average gap between requests |
| 224system.physmem.pageHitRate 73.98 # Row buffer hit rate, read and write combined | 222system.physmem.pageHitRate 73.98 # Row buffer hit rate, read and write combined |
| 225system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state 226system.membus.throughput 1320212262 # Throughput (bytes/s) | 223system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 224system.physmem.memoryStateTime::REF 520000 # Time in different power states 225system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 226system.physmem.memoryStateTime::ACT 15333750 # Time in different power states 227system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 228system.membus.throughput 1324038678 # Throughput (bytes/s) |
| 227system.membus.trans_dist::ReadReq 338 # Transaction distribution 228system.membus.trans_dist::ReadResp 337 # Transaction distribution 229system.membus.trans_dist::ReadExReq 77 # Transaction distribution 230system.membus.trans_dist::ReadExResp 77 # Transaction distribution 231system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 829 # Packet count per connected master and slave (bytes) 232system.membus.pkt_count_system.cpu.l2cache.mem_side::total 829 # Packet count per connected master and slave (bytes) 233system.membus.pkt_count::total 829 # Packet count per connected master and slave (bytes) 234system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26496 # Cumulative packet size per connected master and slave (bytes) 235system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26496 # Cumulative packet size per connected master and slave (bytes) 236system.membus.tot_pkt_size::total 26496 # Cumulative packet size per connected master and slave (bytes) 237system.membus.data_through_bus 26496 # Total data (bytes) 238system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 229system.membus.trans_dist::ReadReq 338 # Transaction distribution 230system.membus.trans_dist::ReadResp 337 # Transaction distribution 231system.membus.trans_dist::ReadExReq 77 # Transaction distribution 232system.membus.trans_dist::ReadExResp 77 # Transaction distribution 233system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 829 # Packet count per connected master and slave (bytes) 234system.membus.pkt_count_system.cpu.l2cache.mem_side::total 829 # Packet count per connected master and slave (bytes) 235system.membus.pkt_count::total 829 # Packet count per connected master and slave (bytes) 236system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26496 # Cumulative packet size per connected master and slave (bytes) 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26496 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size::total 26496 # Cumulative packet size per connected master and slave (bytes) 239system.membus.data_through_bus 26496 # Total data (bytes) 240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 239system.membus.reqLayer0.occupancy 500500 # Layer occupancy (ticks) | 241system.membus.reqLayer0.occupancy 501000 # Layer occupancy (ticks) |
| 240system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) | 242system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) |
| 241system.membus.respLayer1.occupancy 3871750 # Layer occupancy (ticks) 242system.membus.respLayer1.utilization 19.3 # Layer utilization (%) | 243system.membus.respLayer1.occupancy 3873250 # Layer occupancy (ticks) 244system.membus.respLayer1.utilization 19.4 # Layer utilization (%) |
| 243system.cpu_clk_domain.clock 500 # Clock period in ticks | 245system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 244system.cpu.branchPred.lookups 3084 # Number of BP lookups 245system.cpu.branchPred.condPredicted 3084 # Number of conditional branches predicted 246system.cpu.branchPred.condIncorrect 542 # Number of conditional branches incorrect 247system.cpu.branchPred.BTBLookups 2283 # Number of BTB lookups 248system.cpu.branchPred.BTBHits 726 # Number of BTB hits | 246system.cpu.branchPred.lookups 3083 # Number of BP lookups 247system.cpu.branchPred.condPredicted 3083 # Number of conditional branches predicted 248system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect 249system.cpu.branchPred.BTBLookups 2281 # Number of BTB lookups 250system.cpu.branchPred.BTBHits 725 # Number of BTB hits |
| 249system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 250system.cpu.branchPred.BTBHitPct 31.800263 # BTB Hit Percentage | 252system.cpu.branchPred.BTBHitPct 31.784305 # BTB Hit Percentage |
| 251system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. 252system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. 253system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 254system.cpu.workload.num_syscalls 11 # Number of system calls | 253system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. 254system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. 255system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 256system.cpu.workload.num_syscalls 11 # Number of system calls |
| 255system.cpu.numCycles 40140 # number of cpu cycles simulated | 257system.cpu.numCycles 40024 # number of cpu cycles simulated |
| 256system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 257system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 258system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 259system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 258system.cpu.fetch.icacheStallCycles 10289 # Number of cycles fetch is stalled on an Icache miss 259system.cpu.fetch.Insts 14134 # Number of instructions fetch has processed 260system.cpu.fetch.Branches 3084 # Number of branches that fetch encountered 261system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken 262system.cpu.fetch.Cycles 3940 # Number of cycles fetch has run and was not squashing or blocked 263system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing 264system.cpu.fetch.BlockedCycles 5352 # Number of cycles fetch has spent blocked | 260system.cpu.fetch.icacheStallCycles 10292 # Number of cycles fetch is stalled on an Icache miss 261system.cpu.fetch.Insts 14141 # Number of instructions fetch has processed 262system.cpu.fetch.Branches 3083 # Number of branches that fetch encountered 263system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken 264system.cpu.fetch.Cycles 3942 # Number of cycles fetch has run and was not squashing or blocked 265system.cpu.fetch.SquashCycles 2472 # Number of cycles fetch has spent squashing 266system.cpu.fetch.BlockedCycles 5349 # Number of cycles fetch has spent blocked |
| 265system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 266system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps 267system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR | 267system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 268system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps 269system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR |
| 268system.cpu.fetch.CacheLines 1980 # Number of cache lines fetched 269system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed 270system.cpu.fetch.rateDist::samples 21899 # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.rateDist::mean 1.150509 # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::stdev 2.666400 # Number of instructions fetched each cycle (Total) | 270system.cpu.fetch.CacheLines 1981 # Number of cache lines fetched 271system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed 272system.cpu.fetch.rateDist::samples 21900 # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.rateDist::mean 1.150913 # Number of instructions fetched each cycle (Total) 274system.cpu.fetch.rateDist::stdev 2.666787 # Number of instructions fetched each cycle (Total) |
| 273system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 275system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 274system.cpu.fetch.rateDist::0 18060 82.47% 82.47% # Number of instructions fetched each cycle (Total) 275system.cpu.fetch.rateDist::1 216 0.99% 83.46% # Number of instructions fetched each cycle (Total) | 276system.cpu.fetch.rateDist::0 18059 82.46% 82.46% # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.rateDist::1 217 0.99% 83.45% # Number of instructions fetched each cycle (Total) |
| 276system.cpu.fetch.rateDist::2 142 0.65% 84.10% # Number of instructions fetched each cycle (Total) | 278system.cpu.fetch.rateDist::2 142 0.65% 84.10% # Number of instructions fetched each cycle (Total) |
| 277system.cpu.fetch.rateDist::3 224 1.02% 85.13% # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::4 181 0.83% 85.95% # Number of instructions fetched each cycle (Total) 279system.cpu.fetch.rateDist::5 200 0.91% 86.87% # Number of instructions fetched each cycle (Total) | 279system.cpu.fetch.rateDist::3 224 1.02% 85.12% # Number of instructions fetched each cycle (Total) 280system.cpu.fetch.rateDist::4 180 0.82% 85.95% # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::5 201 0.92% 86.86% # Number of instructions fetched each cycle (Total) |
| 280system.cpu.fetch.rateDist::6 275 1.26% 88.12% # Number of instructions fetched each cycle (Total) | 282system.cpu.fetch.rateDist::6 275 1.26% 88.12% # Number of instructions fetched each cycle (Total) |
| 281system.cpu.fetch.rateDist::7 159 0.73% 88.85% # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::8 2442 11.15% 100.00% # Number of instructions fetched each cycle (Total) | 283system.cpu.fetch.rateDist::7 159 0.73% 88.84% # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::8 2443 11.16% 100.00% # Number of instructions fetched each cycle (Total) |
| 283system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 285system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 286system.cpu.fetch.rateDist::total 21899 # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.branchRate 0.076831 # Number of branch fetches per cycle 288system.cpu.fetch.rate 0.352118 # Number of inst fetches per cycle 289system.cpu.decode.IdleCycles 11081 # Number of cycles decode is idle 290system.cpu.decode.BlockedCycles 5247 # Number of cycles decode is blocked | 288system.cpu.fetch.rateDist::total 21900 # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.branchRate 0.077029 # Number of branch fetches per cycle 290system.cpu.fetch.rate 0.353313 # Number of inst fetches per cycle 291system.cpu.decode.IdleCycles 11088 # Number of cycles decode is idle 292system.cpu.decode.BlockedCycles 5242 # Number of cycles decode is blocked |
| 291system.cpu.decode.RunCycles 3583 # Number of cycles decode is running 292system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking | 293system.cpu.decode.RunCycles 3583 # Number of cycles decode is running 294system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking |
| 293system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing 294system.cpu.decode.DecodedInsts 24173 # Number of instructions handled by decode 295system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing 296system.cpu.rename.IdleCycles 11446 # Number of cycles rename is idle | 295system.cpu.decode.SquashCycles 1856 # Number of cycles decode is squashing 296system.cpu.decode.DecodedInsts 24179 # Number of instructions handled by decode 297system.cpu.rename.SquashCycles 1856 # Number of cycles rename is squashing 298system.cpu.rename.IdleCycles 11454 # Number of cycles rename is idle |
| 297system.cpu.rename.BlockCycles 3886 # Number of cycles rename is blocking | 299system.cpu.rename.BlockCycles 3886 # Number of cycles rename is blocking |
| 298system.cpu.rename.serializeStallCycles 603 # count of cycles rename stalled for serializing inst 299system.cpu.rename.RunCycles 3331 # Number of cycles rename is running 300system.cpu.rename.UnblockCycles 776 # Number of cycles rename is unblocking 301system.cpu.rename.RenamedInsts 22661 # Number of instructions processed by rename | 300system.cpu.rename.serializeStallCycles 592 # count of cycles rename stalled for serializing inst 301system.cpu.rename.RunCycles 3330 # Number of cycles rename is running 302system.cpu.rename.UnblockCycles 782 # Number of cycles rename is unblocking 303system.cpu.rename.RenamedInsts 22657 # Number of instructions processed by rename |
| 302system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full | 304system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full |
| 303system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full 304system.cpu.rename.LSQFullEvents 663 # Number of times rename has blocked due to LSQ full 305system.cpu.rename.RenamedOperands 25256 # Number of destination operands rename has renamed 306system.cpu.rename.RenameLookups 55040 # Number of register rename lookups that rename has made | 305system.cpu.rename.IQFullEvents 37 # Number of times rename has blocked due to IQ full 306system.cpu.rename.LSQFullEvents 664 # Number of times rename has blocked due to LSQ full 307system.cpu.rename.RenamedOperands 25254 # Number of destination operands rename has renamed 308system.cpu.rename.RenameLookups 55037 # Number of register rename lookups that rename has made |
| 307system.cpu.rename.int_rename_lookups 31380 # Number of integer rename lookups 308system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 309system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed | 309system.cpu.rename.int_rename_lookups 31380 # Number of integer rename lookups 310system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 311system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed |
| 310system.cpu.rename.UndoneMaps 14193 # Number of HB maps that are undone due to squashing | 312system.cpu.rename.UndoneMaps 14191 # Number of HB maps that are undone due to squashing |
| 311system.cpu.rename.serializingInsts 30 # count of serializing insts renamed 312system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed | 313system.cpu.rename.serializingInsts 30 # count of serializing insts renamed 314system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed |
| 313system.cpu.rename.skidInsts 2047 # count of insts added to the skid buffer | 315system.cpu.rename.skidInsts 2053 # count of insts added to the skid buffer |
| 314system.cpu.memDep0.insertedLoads 2285 # Number of loads inserted to the mem dependence unit. 315system.cpu.memDep0.insertedStores 1565 # Number of stores inserted to the mem dependence unit. 316system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. 317system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. | 316system.cpu.memDep0.insertedLoads 2285 # Number of loads inserted to the mem dependence unit. 317system.cpu.memDep0.insertedStores 1565 # Number of stores inserted to the mem dependence unit. 318system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. 319system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. |
| 318system.cpu.iq.iqInstsAdded 20236 # Number of instructions added to the IQ (excludes non-spec) | 320system.cpu.iq.iqInstsAdded 20246 # Number of instructions added to the IQ (excludes non-spec) |
| 319system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ | 321system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ |
| 320system.cpu.iq.iqInstsIssued 17027 # Number of instructions issued 321system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued 322system.cpu.iq.iqSquashedInstsExamined 9729 # Number of squashed instructions iterated over during squash; mainly for profiling 323system.cpu.iq.iqSquashedOperandsExamined 13960 # Number of squashed operands that are examined and possibly removed from graph | 322system.cpu.iq.iqInstsIssued 17025 # Number of instructions issued 323system.cpu.iq.iqSquashedInstsIssued 298 # Number of squashed instructions issued 324system.cpu.iq.iqSquashedInstsExamined 9739 # Number of squashed instructions iterated over during squash; mainly for profiling 325system.cpu.iq.iqSquashedOperandsExamined 13977 # Number of squashed operands that are examined and possibly removed from graph |
| 324system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed | 326system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed |
| 325system.cpu.iq.issued_per_cycle::samples 21899 # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::mean 0.777524 # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::stdev 1.652832 # Number of insts issued each cycle | 327system.cpu.iq.issued_per_cycle::samples 21900 # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::mean 0.777397 # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::stdev 1.653011 # Number of insts issued each cycle |
| 328system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 330system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 329system.cpu.iq.issued_per_cycle::0 16413 74.95% 74.95% # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::1 1539 7.03% 81.98% # Number of insts issued each cycle 331system.cpu.iq.issued_per_cycle::2 1092 4.99% 86.96% # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::3 724 3.31% 90.27% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::4 698 3.19% 93.46% # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::5 576 2.63% 96.09% # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::6 581 2.65% 98.74% # Number of insts issued each cycle | 331system.cpu.iq.issued_per_cycle::0 16414 74.95% 74.95% # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::1 1544 7.05% 82.00% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::2 1087 4.96% 86.96% # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::3 722 3.30% 90.26% # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::4 701 3.20% 93.46% # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::5 573 2.62% 96.08% # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::6 583 2.66% 98.74% # Number of insts issued each cycle |
| 336system.cpu.iq.issued_per_cycle::7 234 1.07% 99.81% # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 338system.cpu.iq.issued_per_cycle::7 234 1.07% 99.81% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 341system.cpu.iq.issued_per_cycle::total 21899 # Number of insts issued each cycle | 343system.cpu.iq.issued_per_cycle::total 21900 # Number of insts issued each cycle |
| 342system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 343system.cpu.iq.fu_full::IntAlu 140 77.35% 77.35% # attempts to use FU when none available 344system.cpu.iq.fu_full::IntMult 0 0.00% 77.35% # attempts to use FU when none available 345system.cpu.iq.fu_full::IntDiv 0 0.00% 77.35% # attempts to use FU when none available 346system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.35% # attempts to use FU when none available 347system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.35% # attempts to use FU when none available 348system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.35% # attempts to use FU when none available 349system.cpu.iq.fu_full::FloatMult 0 0.00% 77.35% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 369system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.35% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.35% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.35% # attempts to use FU when none available 372system.cpu.iq.fu_full::MemRead 26 14.36% 91.71% # attempts to use FU when none available 373system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available 374system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 375system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 376system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued | 344system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 345system.cpu.iq.fu_full::IntAlu 140 77.35% 77.35% # attempts to use FU when none available 346system.cpu.iq.fu_full::IntMult 0 0.00% 77.35% # attempts to use FU when none available 347system.cpu.iq.fu_full::IntDiv 0 0.00% 77.35% # attempts to use FU when none available 348system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.35% # attempts to use FU when none available 349system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.35% # attempts to use FU when none available 350system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.35% # attempts to use FU when none available 351system.cpu.iq.fu_full::FloatMult 0 0.00% 77.35% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 371system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.35% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.35% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.35% # attempts to use FU when none available 374system.cpu.iq.fu_full::MemRead 26 14.36% 91.71% # attempts to use FU when none available 375system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available 376system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 377system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 378system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued |
| 377system.cpu.iq.FU_type_0::IntAlu 13667 80.27% 80.28% # Type of FU issued | 379system.cpu.iq.FU_type_0::IntAlu 13665 80.26% 80.28% # Type of FU issued |
| 378system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.31% # Type of FU issued 379system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.35% # Type of FU issued 380system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.35% # Type of FU issued 381system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.35% # Type of FU issued 382system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.35% # Type of FU issued 383system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.35% # Type of FU issued 384system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.35% # Type of FU issued 385system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.35% # Type of FU issued --- 16 unchanged lines hidden (view full) --- 402system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.35% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.35% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.35% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.35% # Type of FU issued 406system.cpu.iq.FU_type_0::MemRead 1973 11.59% 91.94% # Type of FU issued 407system.cpu.iq.FU_type_0::MemWrite 1373 8.06% 100.00% # Type of FU issued 408system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 409system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 380system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.31% # Type of FU issued 381system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.35% # Type of FU issued 382system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.35% # Type of FU issued 383system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.35% # Type of FU issued 384system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.35% # Type of FU issued 385system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.35% # Type of FU issued 386system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.35% # Type of FU issued 387system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.35% # Type of FU issued --- 16 unchanged lines hidden (view full) --- 404system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.35% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.35% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.35% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.35% # Type of FU issued 408system.cpu.iq.FU_type_0::MemRead 1973 11.59% 91.94% # Type of FU issued 409system.cpu.iq.FU_type_0::MemWrite 1373 8.06% 100.00% # Type of FU issued 410system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 411system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 410system.cpu.iq.FU_type_0::total 17027 # Type of FU issued 411system.cpu.iq.rate 0.424190 # Inst issue rate | 412system.cpu.iq.FU_type_0::total 17025 # Type of FU issued 413system.cpu.iq.rate 0.425370 # Inst issue rate |
| 412system.cpu.iq.fu_busy_cnt 181 # FU busy when requested | 414system.cpu.iq.fu_busy_cnt 181 # FU busy when requested |
| 413system.cpu.iq.fu_busy_rate 0.010630 # FU busy rate (busy events/executed inst) 414system.cpu.iq.int_inst_queue_reads 56416 # Number of integer instruction queue reads 415system.cpu.iq.int_inst_queue_writes 29998 # Number of integer instruction queue writes 416system.cpu.iq.int_inst_queue_wakeup_accesses 15642 # Number of integer instruction queue wakeup accesses | 415system.cpu.iq.fu_busy_rate 0.010631 # FU busy rate (busy events/executed inst) 416system.cpu.iq.int_inst_queue_reads 56421 # Number of integer instruction queue reads 417system.cpu.iq.int_inst_queue_writes 30018 # Number of integer instruction queue writes 418system.cpu.iq.int_inst_queue_wakeup_accesses 15641 # Number of integer instruction queue wakeup accesses |
| 417system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 418system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 419system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses | 419system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 420system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 421system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses |
| 420system.cpu.iq.int_alu_accesses 17201 # Number of integer alu accesses | 422system.cpu.iq.int_alu_accesses 17199 # Number of integer alu accesses |
| 421system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses 422system.cpu.iew.lsq.thread0.forwLoads 168 # Number of loads that had data forwarded from stores 423system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 424system.cpu.iew.lsq.thread0.squashedLoads 1232 # Number of loads squashed 425system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed 426system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations 427system.cpu.iew.lsq.thread0.squashedStores 630 # Number of stores squashed 428system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 429system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 430system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 431system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked 432system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 423system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses 424system.cpu.iew.lsq.thread0.forwLoads 168 # Number of loads that had data forwarded from stores 425system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 426system.cpu.iew.lsq.thread0.squashedLoads 1232 # Number of loads squashed 427system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed 428system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations 429system.cpu.iew.lsq.thread0.squashedStores 630 # Number of stores squashed 430system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 431system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 432system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 433system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked 434system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 433system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing 434system.cpu.iew.iewBlockCycles 3086 # Number of cycles IEW is blocking | 435system.cpu.iew.iewSquashCycles 1856 # Number of cycles IEW is squashing 436system.cpu.iew.iewBlockCycles 3085 # Number of cycles IEW is blocking |
| 435system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking | 437system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking |
| 436system.cpu.iew.iewDispatchedInsts 20262 # Number of instructions dispatched to IQ | 438system.cpu.iew.iewDispatchedInsts 20272 # Number of instructions dispatched to IQ |
| 437system.cpu.iew.iewDispSquashedInsts 39 # Number of squashed instructions skipped by dispatch 438system.cpu.iew.iewDispLoadInsts 2285 # Number of dispatched load instructions 439system.cpu.iew.iewDispStoreInsts 1565 # Number of dispatched store instructions 440system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions 441system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall 442system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 443system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations 444system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly | 439system.cpu.iew.iewDispSquashedInsts 39 # Number of squashed instructions skipped by dispatch 440system.cpu.iew.iewDispLoadInsts 2285 # Number of dispatched load instructions 441system.cpu.iew.iewDispStoreInsts 1565 # Number of dispatched store instructions 442system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions 443system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall 444system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 445system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations 446system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly |
| 445system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly 446system.cpu.iew.branchMispredicts 686 # Number of branch mispredicts detected at execute 447system.cpu.iew.iewExecutedInsts 16124 # Number of executed instructions 448system.cpu.iew.iewExecLoadInsts 1854 # Number of load instructions executed | 447system.cpu.iew.predictedNotTakenIncorrect 571 # Number of branches that were predicted not taken incorrectly 448system.cpu.iew.branchMispredicts 687 # Number of branch mispredicts detected at execute 449system.cpu.iew.iewExecutedInsts 16122 # Number of executed instructions 450system.cpu.iew.iewExecLoadInsts 1853 # Number of load instructions executed |
| 449system.cpu.iew.iewExecSquashedInsts 903 # Number of squashed instructions skipped in execute 450system.cpu.iew.exec_swp 0 # number of swp insts executed 451system.cpu.iew.exec_nop 0 # number of nop insts executed | 451system.cpu.iew.iewExecSquashedInsts 903 # Number of squashed instructions skipped in execute 452system.cpu.iew.exec_swp 0 # number of swp insts executed 453system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 452system.cpu.iew.exec_refs 3127 # number of memory reference insts executed | 454system.cpu.iew.exec_refs 3126 # number of memory reference insts executed |
| 453system.cpu.iew.exec_branches 1623 # Number of branches executed 454system.cpu.iew.exec_stores 1273 # Number of stores executed | 455system.cpu.iew.exec_branches 1623 # Number of branches executed 456system.cpu.iew.exec_stores 1273 # Number of stores executed |
| 455system.cpu.iew.exec_rate 0.401694 # Inst execution rate 456system.cpu.iew.wb_sent 15865 # cumulative count of insts sent to commit 457system.cpu.iew.wb_count 15646 # cumulative count of insts written-back | 457system.cpu.iew.exec_rate 0.402808 # Inst execution rate 458system.cpu.iew.wb_sent 15864 # cumulative count of insts sent to commit 459system.cpu.iew.wb_count 15645 # cumulative count of insts written-back |
| 458system.cpu.iew.wb_producers 10128 # num instructions producing a value | 460system.cpu.iew.wb_producers 10128 # num instructions producing a value |
| 459system.cpu.iew.wb_consumers 15579 # num instructions consuming a value | 461system.cpu.iew.wb_consumers 15590 # num instructions consuming a value |
| 460system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 462system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 461system.cpu.iew.wb_rate 0.389786 # insts written-back per cycle 462system.cpu.iew.wb_fanout 0.650106 # average fanout of values written-back | 463system.cpu.iew.wb_rate 0.390890 # insts written-back per cycle 464system.cpu.iew.wb_fanout 0.649647 # average fanout of values written-back |
| 463system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 465system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 464system.cpu.commit.commitSquashedInsts 10526 # The number of squashed insts skipped by commit | 466system.cpu.commit.commitSquashedInsts 10536 # The number of squashed insts skipped by commit |
| 465system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards | 467system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards |
| 466system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted 467system.cpu.commit.committed_per_cycle::samples 20042 # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::mean 0.486329 # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::stdev 1.342699 # Number of insts commited each cycle | 468system.cpu.commit.branchMispredicts 592 # The number of times a branch was mispredicted 469system.cpu.commit.committed_per_cycle::samples 20044 # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::mean 0.486280 # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::stdev 1.342641 # Number of insts commited each cycle |
| 470system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 472system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 471system.cpu.commit.committed_per_cycle::0 16474 82.20% 82.20% # Number of insts commited each cycle | 473system.cpu.commit.committed_per_cycle::0 16476 82.20% 82.20% # Number of insts commited each cycle |
| 472system.cpu.commit.committed_per_cycle::1 1360 6.79% 88.98% # Number of insts commited each cycle 473system.cpu.commit.committed_per_cycle::2 589 2.94% 91.92% # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::3 713 3.56% 95.48% # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::4 364 1.82% 97.30% # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::5 136 0.68% 97.97% # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::6 120 0.60% 98.57% # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::7 74 0.37% 98.94% # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 474system.cpu.commit.committed_per_cycle::1 1360 6.79% 88.98% # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::2 589 2.94% 91.92% # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::3 713 3.56% 95.48% # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::4 364 1.82% 97.30% # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::5 136 0.68% 97.97% # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::6 120 0.60% 98.57% # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::7 74 0.37% 98.94% # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 483system.cpu.commit.committed_per_cycle::total 20042 # Number of insts commited each cycle | 485system.cpu.commit.committed_per_cycle::total 20044 # Number of insts commited each cycle |
| 484system.cpu.commit.committedInsts 5380 # Number of instructions committed 485system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed 486system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 487system.cpu.commit.refs 1988 # Number of memory references committed 488system.cpu.commit.loads 1053 # Number of loads committed 489system.cpu.commit.membars 0 # Number of memory barriers committed 490system.cpu.commit.branches 1208 # Number of branches committed 491system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 492system.cpu.commit.int_insts 9653 # Number of committed integer instructions. 493system.cpu.commit.function_calls 106 # Number of function calls committed. | 486system.cpu.commit.committedInsts 5380 # Number of instructions committed 487system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed 488system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 489system.cpu.commit.refs 1988 # Number of memory references committed 490system.cpu.commit.loads 1053 # Number of loads committed 491system.cpu.commit.membars 0 # Number of memory barriers committed 492system.cpu.commit.branches 1208 # Number of branches committed 493system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 494system.cpu.commit.int_insts 9653 # Number of committed integer instructions. 495system.cpu.commit.function_calls 106 # Number of function calls committed. |
| 496system.cpu.commit.op_class_0::No_OpClass 1 0.01% 0.01% # Class of committed instruction 497system.cpu.commit.op_class_0::IntAlu 7748 79.49% 79.50% # Class of committed instruction 498system.cpu.commit.op_class_0::IntMult 3 0.03% 79.53% # Class of committed instruction 499system.cpu.commit.op_class_0::IntDiv 7 0.07% 79.60% # Class of committed instruction 500system.cpu.commit.op_class_0::FloatAdd 0 0.00% 79.60% # Class of committed instruction 501system.cpu.commit.op_class_0::FloatCmp 0 0.00% 79.60% # Class of committed instruction 502system.cpu.commit.op_class_0::FloatCvt 0 0.00% 79.60% # Class of committed instruction 503system.cpu.commit.op_class_0::FloatMult 0 0.00% 79.60% # Class of committed instruction 504system.cpu.commit.op_class_0::FloatDiv 0 0.00% 79.60% # Class of committed instruction 505system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 79.60% # Class of committed instruction 506system.cpu.commit.op_class_0::SimdAdd 0 0.00% 79.60% # Class of committed instruction 507system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 79.60% # Class of committed instruction 508system.cpu.commit.op_class_0::SimdAlu 0 0.00% 79.60% # Class of committed instruction 509system.cpu.commit.op_class_0::SimdCmp 0 0.00% 79.60% # Class of committed instruction 510system.cpu.commit.op_class_0::SimdCvt 0 0.00% 79.60% # Class of committed instruction 511system.cpu.commit.op_class_0::SimdMisc 0 0.00% 79.60% # Class of committed instruction 512system.cpu.commit.op_class_0::SimdMult 0 0.00% 79.60% # Class of committed instruction 513system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 79.60% # Class of committed instruction 514system.cpu.commit.op_class_0::SimdShift 0 0.00% 79.60% # Class of committed instruction 515system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 79.60% # Class of committed instruction 516system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 79.60% # Class of committed instruction 517system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 79.60% # Class of committed instruction 518system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 79.60% # Class of committed instruction 519system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 79.60% # Class of committed instruction 520system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 79.60% # Class of committed instruction 521system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 79.60% # Class of committed instruction 522system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 79.60% # Class of committed instruction 523system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction 524system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction 525system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction 526system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction 527system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction 528system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 529system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 530system.cpu.commit.op_class_0::total 9747 # Class of committed instruction |
|
| 494system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached 495system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 531system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached 532system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 496system.cpu.rob.rob_reads 40103 # The number of ROB reads 497system.cpu.rob.rob_writes 42426 # The number of ROB writes 498system.cpu.timesIdled 166 # Number of times that the entire CPU went into an idle state and unscheduled itself 499system.cpu.idleCycles 18241 # Total number of cycles that the CPU has spent unscheduled due to idling | 533system.cpu.rob.rob_reads 40115 # The number of ROB reads 534system.cpu.rob.rob_writes 42444 # The number of ROB writes 535system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself 536system.cpu.idleCycles 18124 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 500system.cpu.committedInsts 5380 # Number of Instructions Simulated 501system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated 502system.cpu.committedInsts_total 5380 # Number of Instructions Simulated | 537system.cpu.committedInsts 5380 # Number of Instructions Simulated 538system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated 539system.cpu.committedInsts_total 5380 # Number of Instructions Simulated |
| 503system.cpu.cpi 7.460967 # CPI: Cycles Per Instruction 504system.cpu.cpi_total 7.460967 # CPI: Total CPI of All Threads 505system.cpu.ipc 0.134031 # IPC: Instructions Per Cycle 506system.cpu.ipc_total 0.134031 # IPC: Total IPC of All Threads 507system.cpu.int_regfile_reads 20727 # number of integer regfile reads 508system.cpu.int_regfile_writes 12358 # number of integer regfile writes | 540system.cpu.cpi 7.439405 # CPI: Cycles Per Instruction 541system.cpu.cpi_total 7.439405 # CPI: Total CPI of All Threads 542system.cpu.ipc 0.134419 # IPC: Instructions Per Cycle 543system.cpu.ipc_total 0.134419 # IPC: Total IPC of All Threads 544system.cpu.int_regfile_reads 20731 # number of integer regfile reads 545system.cpu.int_regfile_writes 12356 # number of integer regfile writes |
| 509system.cpu.fp_regfile_reads 4 # number of floating regfile reads | 546system.cpu.fp_regfile_reads 4 # number of floating regfile reads |
| 510system.cpu.cc_regfile_reads 8004 # number of cc regfile reads 511system.cpu.cc_regfile_writes 4850 # number of cc regfile writes 512system.cpu.misc_regfile_reads 7135 # number of misc regfile reads | 547system.cpu.cc_regfile_reads 8007 # number of cc regfile reads 548system.cpu.cc_regfile_writes 4854 # number of cc regfile writes 549system.cpu.misc_regfile_reads 7133 # number of misc regfile reads |
| 513system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 550system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 514system.cpu.toL2Bus.throughput 1326590099 # Throughput (bytes/s) | 551system.cpu.toL2Bus.throughput 1330435000 # Throughput (bytes/s) |
| 515system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution 516system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 517system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution 518system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution 519system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 548 # Packet count per connected master and slave (bytes) 520system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) 521system.cpu.toL2Bus.pkt_count::total 833 # Packet count per connected master and slave (bytes) 522system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17536 # Cumulative packet size per connected master and slave (bytes) 523system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 524system.cpu.toL2Bus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) 525system.cpu.toL2Bus.data_through_bus 26624 # Total data (bytes) 526system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 527system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) 528system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) | 552system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution 553system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 554system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution 555system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution 556system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 548 # Packet count per connected master and slave (bytes) 557system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) 558system.cpu.toL2Bus.pkt_count::total 833 # Packet count per connected master and slave (bytes) 559system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17536 # Cumulative packet size per connected master and slave (bytes) 560system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 561system.cpu.toL2Bus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) 562system.cpu.toL2Bus.data_through_bus 26624 # Total data (bytes) 563system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 564system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) 565system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) |
| 529system.cpu.toL2Bus.respLayer0.occupancy 458250 # Layer occupancy (ticks) | 566system.cpu.toL2Bus.respLayer0.occupancy 459500 # Layer occupancy (ticks) |
| 530system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) | 567system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) |
| 531system.cpu.toL2Bus.respLayer1.occupancy 235500 # Layer occupancy (ticks) | 568system.cpu.toL2Bus.respLayer1.occupancy 236250 # Layer occupancy (ticks) |
| 532system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 533system.cpu.icache.tags.replacements 0 # number of replacements | 569system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 570system.cpu.icache.tags.replacements 0 # number of replacements |
| 534system.cpu.icache.tags.tagsinuse 130.897576 # Cycle average of tags in use 535system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks. | 571system.cpu.icache.tags.tagsinuse 130.942440 # Cycle average of tags in use 572system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks. |
| 536system.cpu.icache.tags.sampled_refs 274 # Sample count of references to valid blocks. | 573system.cpu.icache.tags.sampled_refs 274 # Sample count of references to valid blocks. |
| 537system.cpu.icache.tags.avg_refs 5.872263 # Average number of references to valid blocks. | 574system.cpu.icache.tags.avg_refs 5.875912 # Average number of references to valid blocks. |
| 538system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 575system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 539system.cpu.icache.tags.occ_blocks::cpu.inst 130.897576 # Average occupied blocks per requestor 540system.cpu.icache.tags.occ_percent::cpu.inst 0.063915 # Average percentage of cache occupancy 541system.cpu.icache.tags.occ_percent::total 0.063915 # Average percentage of cache occupancy | 576system.cpu.icache.tags.occ_blocks::cpu.inst 130.942440 # Average occupied blocks per requestor 577system.cpu.icache.tags.occ_percent::cpu.inst 0.063937 # Average percentage of cache occupancy 578system.cpu.icache.tags.occ_percent::total 0.063937 # Average percentage of cache occupancy |
| 542system.cpu.icache.tags.occ_task_id_blocks::1024 274 # Occupied blocks per task id 543system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id 544system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id 545system.cpu.icache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id | 579system.cpu.icache.tags.occ_task_id_blocks::1024 274 # Occupied blocks per task id 580system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id 581system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id 582system.cpu.icache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id |
| 546system.cpu.icache.tags.tag_accesses 4234 # Number of tag accesses 547system.cpu.icache.tags.data_accesses 4234 # Number of data accesses 548system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits 549system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits 550system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits 551system.cpu.icache.demand_hits::total 1609 # number of demand (read+write) hits 552system.cpu.icache.overall_hits::cpu.inst 1609 # number of overall hits 553system.cpu.icache.overall_hits::total 1609 # number of overall hits | 583system.cpu.icache.tags.tag_accesses 4236 # Number of tag accesses 584system.cpu.icache.tags.data_accesses 4236 # Number of data accesses 585system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits 586system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits 587system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits 588system.cpu.icache.demand_hits::total 1610 # number of demand (read+write) hits 589system.cpu.icache.overall_hits::cpu.inst 1610 # number of overall hits 590system.cpu.icache.overall_hits::total 1610 # number of overall hits |
| 554system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses 555system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses 556system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses 557system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses 558system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses 559system.cpu.icache.overall_misses::total 371 # number of overall misses | 591system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses 592system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses 593system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses 594system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses 595system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses 596system.cpu.icache.overall_misses::total 371 # number of overall misses |
| 560system.cpu.icache.ReadReq_miss_latency::cpu.inst 25180750 # number of ReadReq miss cycles 561system.cpu.icache.ReadReq_miss_latency::total 25180750 # number of ReadReq miss cycles 562system.cpu.icache.demand_miss_latency::cpu.inst 25180750 # number of demand (read+write) miss cycles 563system.cpu.icache.demand_miss_latency::total 25180750 # number of demand (read+write) miss cycles 564system.cpu.icache.overall_miss_latency::cpu.inst 25180750 # number of overall miss cycles 565system.cpu.icache.overall_miss_latency::total 25180750 # number of overall miss cycles 566system.cpu.icache.ReadReq_accesses::cpu.inst 1980 # number of ReadReq accesses(hits+misses) 567system.cpu.icache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) 568system.cpu.icache.demand_accesses::cpu.inst 1980 # number of demand (read+write) accesses 569system.cpu.icache.demand_accesses::total 1980 # number of demand (read+write) accesses 570system.cpu.icache.overall_accesses::cpu.inst 1980 # number of overall (read+write) accesses 571system.cpu.icache.overall_accesses::total 1980 # number of overall (read+write) accesses 572system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187374 # miss rate for ReadReq accesses 573system.cpu.icache.ReadReq_miss_rate::total 0.187374 # miss rate for ReadReq accesses 574system.cpu.icache.demand_miss_rate::cpu.inst 0.187374 # miss rate for demand accesses 575system.cpu.icache.demand_miss_rate::total 0.187374 # miss rate for demand accesses 576system.cpu.icache.overall_miss_rate::cpu.inst 0.187374 # miss rate for overall accesses 577system.cpu.icache.overall_miss_rate::total 0.187374 # miss rate for overall accesses 578system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67872.641509 # average ReadReq miss latency 579system.cpu.icache.ReadReq_avg_miss_latency::total 67872.641509 # average ReadReq miss latency 580system.cpu.icache.demand_avg_miss_latency::cpu.inst 67872.641509 # average overall miss latency 581system.cpu.icache.demand_avg_miss_latency::total 67872.641509 # average overall miss latency 582system.cpu.icache.overall_avg_miss_latency::cpu.inst 67872.641509 # average overall miss latency 583system.cpu.icache.overall_avg_miss_latency::total 67872.641509 # average overall miss latency | 597system.cpu.icache.ReadReq_miss_latency::cpu.inst 25106250 # number of ReadReq miss cycles 598system.cpu.icache.ReadReq_miss_latency::total 25106250 # number of ReadReq miss cycles 599system.cpu.icache.demand_miss_latency::cpu.inst 25106250 # number of demand (read+write) miss cycles 600system.cpu.icache.demand_miss_latency::total 25106250 # number of demand (read+write) miss cycles 601system.cpu.icache.overall_miss_latency::cpu.inst 25106250 # number of overall miss cycles 602system.cpu.icache.overall_miss_latency::total 25106250 # number of overall miss cycles 603system.cpu.icache.ReadReq_accesses::cpu.inst 1981 # number of ReadReq accesses(hits+misses) 604system.cpu.icache.ReadReq_accesses::total 1981 # number of ReadReq accesses(hits+misses) 605system.cpu.icache.demand_accesses::cpu.inst 1981 # number of demand (read+write) accesses 606system.cpu.icache.demand_accesses::total 1981 # number of demand (read+write) accesses 607system.cpu.icache.overall_accesses::cpu.inst 1981 # number of overall (read+write) accesses 608system.cpu.icache.overall_accesses::total 1981 # number of overall (read+write) accesses 609system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187279 # miss rate for ReadReq accesses 610system.cpu.icache.ReadReq_miss_rate::total 0.187279 # miss rate for ReadReq accesses 611system.cpu.icache.demand_miss_rate::cpu.inst 0.187279 # miss rate for demand accesses 612system.cpu.icache.demand_miss_rate::total 0.187279 # miss rate for demand accesses 613system.cpu.icache.overall_miss_rate::cpu.inst 0.187279 # miss rate for overall accesses 614system.cpu.icache.overall_miss_rate::total 0.187279 # miss rate for overall accesses 615system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67671.832884 # average ReadReq miss latency 616system.cpu.icache.ReadReq_avg_miss_latency::total 67671.832884 # average ReadReq miss latency 617system.cpu.icache.demand_avg_miss_latency::cpu.inst 67671.832884 # average overall miss latency 618system.cpu.icache.demand_avg_miss_latency::total 67671.832884 # average overall miss latency 619system.cpu.icache.overall_avg_miss_latency::cpu.inst 67671.832884 # average overall miss latency 620system.cpu.icache.overall_avg_miss_latency::total 67671.832884 # average overall miss latency |
| 584system.cpu.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked 585system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 586system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 587system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 588system.cpu.icache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked 589system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 590system.cpu.icache.fast_writes 0 # number of fast writes performed 591system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 596system.cpu.icache.overall_mshr_hits::cpu.inst 97 # number of overall MSHR hits 597system.cpu.icache.overall_mshr_hits::total 97 # number of overall MSHR hits 598system.cpu.icache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses 599system.cpu.icache.ReadReq_mshr_misses::total 274 # number of ReadReq MSHR misses 600system.cpu.icache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses 601system.cpu.icache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses 602system.cpu.icache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses 603system.cpu.icache.overall_mshr_misses::total 274 # number of overall MSHR misses | 621system.cpu.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked 622system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 623system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 624system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 625system.cpu.icache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked 626system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 627system.cpu.icache.fast_writes 0 # number of fast writes performed 628system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 633system.cpu.icache.overall_mshr_hits::cpu.inst 97 # number of overall MSHR hits 634system.cpu.icache.overall_mshr_hits::total 97 # number of overall MSHR hits 635system.cpu.icache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses 636system.cpu.icache.ReadReq_mshr_misses::total 274 # number of ReadReq MSHR misses 637system.cpu.icache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses 638system.cpu.icache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses 639system.cpu.icache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses 640system.cpu.icache.overall_mshr_misses::total 274 # number of overall MSHR misses |
| 604system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19745750 # number of ReadReq MSHR miss cycles 605system.cpu.icache.ReadReq_mshr_miss_latency::total 19745750 # number of ReadReq MSHR miss cycles 606system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19745750 # number of demand (read+write) MSHR miss cycles 607system.cpu.icache.demand_mshr_miss_latency::total 19745750 # number of demand (read+write) MSHR miss cycles 608system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19745750 # number of overall MSHR miss cycles 609system.cpu.icache.overall_mshr_miss_latency::total 19745750 # number of overall MSHR miss cycles 610system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for ReadReq accesses 611system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138384 # mshr miss rate for ReadReq accesses 612system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for demand accesses 613system.cpu.icache.demand_mshr_miss_rate::total 0.138384 # mshr miss rate for demand accesses 614system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for overall accesses 615system.cpu.icache.overall_mshr_miss_rate::total 0.138384 # mshr miss rate for overall accesses 616system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72064.781022 # average ReadReq mshr miss latency 617system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72064.781022 # average ReadReq mshr miss latency 618system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72064.781022 # average overall mshr miss latency 619system.cpu.icache.demand_avg_mshr_miss_latency::total 72064.781022 # average overall mshr miss latency 620system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72064.781022 # average overall mshr miss latency 621system.cpu.icache.overall_avg_mshr_miss_latency::total 72064.781022 # average overall mshr miss latency | 641system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19660000 # number of ReadReq MSHR miss cycles 642system.cpu.icache.ReadReq_mshr_miss_latency::total 19660000 # number of ReadReq MSHR miss cycles 643system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19660000 # number of demand (read+write) MSHR miss cycles 644system.cpu.icache.demand_mshr_miss_latency::total 19660000 # number of demand (read+write) MSHR miss cycles 645system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19660000 # number of overall MSHR miss cycles 646system.cpu.icache.overall_mshr_miss_latency::total 19660000 # number of overall MSHR miss cycles 647system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for ReadReq accesses 648system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138314 # mshr miss rate for ReadReq accesses 649system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for demand accesses 650system.cpu.icache.demand_mshr_miss_rate::total 0.138314 # mshr miss rate for demand accesses 651system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for overall accesses 652system.cpu.icache.overall_mshr_miss_rate::total 0.138314 # mshr miss rate for overall accesses 653system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71751.824818 # average ReadReq mshr miss latency 654system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71751.824818 # average ReadReq mshr miss latency 655system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71751.824818 # average overall mshr miss latency 656system.cpu.icache.demand_avg_mshr_miss_latency::total 71751.824818 # average overall mshr miss latency 657system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71751.824818 # average overall mshr miss latency 658system.cpu.icache.overall_avg_mshr_miss_latency::total 71751.824818 # average overall mshr miss latency |
| 622system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 623system.cpu.l2cache.tags.replacements 0 # number of replacements | 659system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 660system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 624system.cpu.l2cache.tags.tagsinuse 163.708534 # Cycle average of tags in use | 661system.cpu.l2cache.tags.tagsinuse 163.759335 # Cycle average of tags in use |
| 625system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 626system.cpu.l2cache.tags.sampled_refs 337 # Sample count of references to valid blocks. 627system.cpu.l2cache.tags.avg_refs 0.005935 # Average number of references to valid blocks. 628system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 662system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 663system.cpu.l2cache.tags.sampled_refs 337 # Sample count of references to valid blocks. 664system.cpu.l2cache.tags.avg_refs 0.005935 # Average number of references to valid blocks. 665system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 629system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.966386 # Average occupied blocks per requestor 630system.cpu.l2cache.tags.occ_blocks::cpu.data 32.742148 # Average occupied blocks per requestor 631system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003997 # Average percentage of cache occupancy | 666system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.011600 # Average occupied blocks per requestor 667system.cpu.l2cache.tags.occ_blocks::cpu.data 32.747734 # Average occupied blocks per requestor 668system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003998 # Average percentage of cache occupancy |
| 632system.cpu.l2cache.tags.occ_percent::cpu.data 0.000999 # Average percentage of cache occupancy | 669system.cpu.l2cache.tags.occ_percent::cpu.data 0.000999 # Average percentage of cache occupancy |
| 633system.cpu.l2cache.tags.occ_percent::total 0.004996 # Average percentage of cache occupancy | 670system.cpu.l2cache.tags.occ_percent::total 0.004998 # Average percentage of cache occupancy |
| 634system.cpu.l2cache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id | 671system.cpu.l2cache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id |
| 635system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id 636system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id | 672system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 673system.cpu.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id |
| 637system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010284 # Percentage of cache occupancy per task id 638system.cpu.l2cache.tags.tag_accesses 3750 # Number of tag accesses 639system.cpu.l2cache.tags.data_accesses 3750 # Number of data accesses 640system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 641system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 642system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 643system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 644system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits --- 7 unchanged lines hidden (view full) --- 652system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses 653system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses 654system.cpu.l2cache.demand_misses::cpu.inst 273 # number of demand (read+write) misses 655system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 656system.cpu.l2cache.demand_misses::total 415 # number of demand (read+write) misses 657system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses 658system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 659system.cpu.l2cache.overall_misses::total 415 # number of overall misses | 674system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010284 # Percentage of cache occupancy per task id 675system.cpu.l2cache.tags.tag_accesses 3750 # Number of tag accesses 676system.cpu.l2cache.tags.data_accesses 3750 # Number of data accesses 677system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 678system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 679system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 680system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 681system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits --- 7 unchanged lines hidden (view full) --- 689system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses 690system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses 691system.cpu.l2cache.demand_misses::cpu.inst 273 # number of demand (read+write) misses 692system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 693system.cpu.l2cache.demand_misses::total 415 # number of demand (read+write) misses 694system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses 695system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 696system.cpu.l2cache.overall_misses::total 415 # number of overall misses |
| 660system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19460250 # number of ReadReq miss cycles 661system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5265000 # number of ReadReq miss cycles 662system.cpu.l2cache.ReadReq_miss_latency::total 24725250 # number of ReadReq miss cycles 663system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5444500 # number of ReadExReq miss cycles 664system.cpu.l2cache.ReadExReq_miss_latency::total 5444500 # number of ReadExReq miss cycles 665system.cpu.l2cache.demand_miss_latency::cpu.inst 19460250 # number of demand (read+write) miss cycles 666system.cpu.l2cache.demand_miss_latency::cpu.data 10709500 # number of demand (read+write) miss cycles 667system.cpu.l2cache.demand_miss_latency::total 30169750 # number of demand (read+write) miss cycles 668system.cpu.l2cache.overall_miss_latency::cpu.inst 19460250 # number of overall miss cycles 669system.cpu.l2cache.overall_miss_latency::cpu.data 10709500 # number of overall miss cycles 670system.cpu.l2cache.overall_miss_latency::total 30169750 # number of overall miss cycles | 697system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19374500 # number of ReadReq miss cycles 698system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5212250 # number of ReadReq miss cycles 699system.cpu.l2cache.ReadReq_miss_latency::total 24586750 # number of ReadReq miss cycles 700system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5445500 # number of ReadExReq miss cycles 701system.cpu.l2cache.ReadExReq_miss_latency::total 5445500 # number of ReadExReq miss cycles 702system.cpu.l2cache.demand_miss_latency::cpu.inst 19374500 # number of demand (read+write) miss cycles 703system.cpu.l2cache.demand_miss_latency::cpu.data 10657750 # number of demand (read+write) miss cycles 704system.cpu.l2cache.demand_miss_latency::total 30032250 # number of demand (read+write) miss cycles 705system.cpu.l2cache.overall_miss_latency::cpu.inst 19374500 # number of overall miss cycles 706system.cpu.l2cache.overall_miss_latency::cpu.data 10657750 # number of overall miss cycles 707system.cpu.l2cache.overall_miss_latency::total 30032250 # number of overall miss cycles |
| 671system.cpu.l2cache.ReadReq_accesses::cpu.inst 274 # number of ReadReq accesses(hits+misses) 672system.cpu.l2cache.ReadReq_accesses::cpu.data 66 # number of ReadReq accesses(hits+misses) 673system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) 674system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses) 675system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses) 676system.cpu.l2cache.demand_accesses::cpu.inst 274 # number of demand (read+write) accesses 677system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses 678system.cpu.l2cache.demand_accesses::total 417 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 685system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 686system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 687system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996350 # miss rate for demand accesses 688system.cpu.l2cache.demand_miss_rate::cpu.data 0.993007 # miss rate for demand accesses 689system.cpu.l2cache.demand_miss_rate::total 0.995204 # miss rate for demand accesses 690system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996350 # miss rate for overall accesses 691system.cpu.l2cache.overall_miss_rate::cpu.data 0.993007 # miss rate for overall accesses 692system.cpu.l2cache.overall_miss_rate::total 0.995204 # miss rate for overall accesses | 708system.cpu.l2cache.ReadReq_accesses::cpu.inst 274 # number of ReadReq accesses(hits+misses) 709system.cpu.l2cache.ReadReq_accesses::cpu.data 66 # number of ReadReq accesses(hits+misses) 710system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) 711system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses) 712system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses) 713system.cpu.l2cache.demand_accesses::cpu.inst 274 # number of demand (read+write) accesses 714system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses 715system.cpu.l2cache.demand_accesses::total 417 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 722system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 723system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 724system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996350 # miss rate for demand accesses 725system.cpu.l2cache.demand_miss_rate::cpu.data 0.993007 # miss rate for demand accesses 726system.cpu.l2cache.demand_miss_rate::total 0.995204 # miss rate for demand accesses 727system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996350 # miss rate for overall accesses 728system.cpu.l2cache.overall_miss_rate::cpu.data 0.993007 # miss rate for overall accesses 729system.cpu.l2cache.overall_miss_rate::total 0.995204 # miss rate for overall accesses |
| 693system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71282.967033 # average ReadReq miss latency 694system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81000 # average ReadReq miss latency 695system.cpu.l2cache.ReadReq_avg_miss_latency::total 73151.627219 # average ReadReq miss latency 696system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70707.792208 # average ReadExReq miss latency 697system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70707.792208 # average ReadExReq miss latency 698system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71282.967033 # average overall miss latency 699system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75419.014085 # average overall miss latency 700system.cpu.l2cache.demand_avg_miss_latency::total 72698.192771 # average overall miss latency 701system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71282.967033 # average overall miss latency 702system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75419.014085 # average overall miss latency 703system.cpu.l2cache.overall_avg_miss_latency::total 72698.192771 # average overall miss latency | 730system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70968.864469 # average ReadReq miss latency 731system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80188.461538 # average ReadReq miss latency 732system.cpu.l2cache.ReadReq_avg_miss_latency::total 72741.863905 # average ReadReq miss latency 733system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70720.779221 # average ReadExReq miss latency 734system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70720.779221 # average ReadExReq miss latency 735system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70968.864469 # average overall miss latency 736system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75054.577465 # average overall miss latency 737system.cpu.l2cache.demand_avg_miss_latency::total 72366.867470 # average overall miss latency 738system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70968.864469 # average overall miss latency 739system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75054.577465 # average overall miss latency 740system.cpu.l2cache.overall_avg_miss_latency::total 72366.867470 # average overall miss latency |
| 704system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 705system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 706system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 707system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 708system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 709system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 710system.cpu.l2cache.fast_writes 0 # number of fast writes performed 711system.cpu.l2cache.cache_copies 0 # number of cache copies performed 712system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses 713system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 714system.cpu.l2cache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses 715system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses 716system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses 717system.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses 718system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 719system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses 720system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses 721system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 722system.cpu.l2cache.overall_mshr_misses::total 415 # number of overall MSHR misses | 741system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 742system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 743system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 744system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 745system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 746system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 747system.cpu.l2cache.fast_writes 0 # number of fast writes performed 748system.cpu.l2cache.cache_copies 0 # number of cache copies performed 749system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses 750system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 751system.cpu.l2cache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses 752system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses 753system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses 754system.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses 755system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 756system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses 757system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses 758system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 759system.cpu.l2cache.overall_mshr_misses::total 415 # number of overall MSHR misses |
| 723system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16034750 # number of ReadReq MSHR miss cycles 724system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4466500 # number of ReadReq MSHR miss cycles 725system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20501250 # number of ReadReq MSHR miss cycles 726system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4485000 # number of ReadExReq MSHR miss cycles 727system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4485000 # number of ReadExReq MSHR miss cycles 728system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16034750 # number of demand (read+write) MSHR miss cycles 729system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8951500 # number of demand (read+write) MSHR miss cycles 730system.cpu.l2cache.demand_mshr_miss_latency::total 24986250 # number of demand (read+write) MSHR miss cycles 731system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16034750 # number of overall MSHR miss cycles 732system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8951500 # number of overall MSHR miss cycles 733system.cpu.l2cache.overall_mshr_miss_latency::total 24986250 # number of overall MSHR miss cycles | 760system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15946000 # number of ReadReq MSHR miss cycles 761system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4413250 # number of ReadReq MSHR miss cycles 762system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20359250 # number of ReadReq MSHR miss cycles 763system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4486000 # number of ReadExReq MSHR miss cycles 764system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4486000 # number of ReadExReq MSHR miss cycles 765system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15946000 # number of demand (read+write) MSHR miss cycles 766system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8899250 # number of demand (read+write) MSHR miss cycles 767system.cpu.l2cache.demand_mshr_miss_latency::total 24845250 # number of demand (read+write) MSHR miss cycles 768system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15946000 # number of overall MSHR miss cycles 769system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8899250 # number of overall MSHR miss cycles 770system.cpu.l2cache.overall_mshr_miss_latency::total 24845250 # number of overall MSHR miss cycles |
| 734system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for ReadReq accesses 735system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.984848 # mshr miss rate for ReadReq accesses 736system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994118 # mshr miss rate for ReadReq accesses 737system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 738system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 739system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for demand accesses 740system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for demand accesses 741system.cpu.l2cache.demand_mshr_miss_rate::total 0.995204 # mshr miss rate for demand accesses 742system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses 743system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for overall accesses 744system.cpu.l2cache.overall_mshr_miss_rate::total 0.995204 # mshr miss rate for overall accesses | 771system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for ReadReq accesses 772system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.984848 # mshr miss rate for ReadReq accesses 773system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994118 # mshr miss rate for ReadReq accesses 774system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 775system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 776system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for demand accesses 777system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for demand accesses 778system.cpu.l2cache.demand_mshr_miss_rate::total 0.995204 # mshr miss rate for demand accesses 779system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses 780system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for overall accesses 781system.cpu.l2cache.overall_mshr_miss_rate::total 0.995204 # mshr miss rate for overall accesses |
| 745system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58735.347985 # average ReadReq mshr miss latency 746system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68715.384615 # average ReadReq mshr miss latency 747system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60654.585799 # average ReadReq mshr miss latency 748system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58246.753247 # average ReadExReq mshr miss latency 749system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58246.753247 # average ReadExReq mshr miss latency 750system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58735.347985 # average overall mshr miss latency 751system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63038.732394 # average overall mshr miss latency 752system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60207.831325 # average overall mshr miss latency 753system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58735.347985 # average overall mshr miss latency 754system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63038.732394 # average overall mshr miss latency 755system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60207.831325 # average overall mshr miss latency | 782system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58410.256410 # average ReadReq mshr miss latency 783system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67896.153846 # average ReadReq mshr miss latency 784system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60234.467456 # average ReadReq mshr miss latency 785system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58259.740260 # average ReadExReq mshr miss latency 786system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58259.740260 # average ReadExReq mshr miss latency 787system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58410.256410 # average overall mshr miss latency 788system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62670.774648 # average overall mshr miss latency 789system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59868.072289 # average overall mshr miss latency 790system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58410.256410 # average overall mshr miss latency 791system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62670.774648 # average overall mshr miss latency 792system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59868.072289 # average overall mshr miss latency |
| 756system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 757system.cpu.dcache.tags.replacements 0 # number of replacements | 793system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 794system.cpu.dcache.tags.replacements 0 # number of replacements |
| 758system.cpu.dcache.tags.tagsinuse 83.267922 # Cycle average of tags in use 759system.cpu.dcache.tags.total_refs 2337 # Total number of references to valid blocks. | 795system.cpu.dcache.tags.tagsinuse 83.261165 # Cycle average of tags in use 796system.cpu.dcache.tags.total_refs 2335 # Total number of references to valid blocks. |
| 760system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. | 797system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. |
| 761system.cpu.dcache.tags.avg_refs 16.457746 # Average number of references to valid blocks. | 798system.cpu.dcache.tags.avg_refs 16.443662 # Average number of references to valid blocks. |
| 762system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 799system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 763system.cpu.dcache.tags.occ_blocks::cpu.data 83.267922 # Average occupied blocks per requestor 764system.cpu.dcache.tags.occ_percent::cpu.data 0.020329 # Average percentage of cache occupancy 765system.cpu.dcache.tags.occ_percent::total 0.020329 # Average percentage of cache occupancy | 800system.cpu.dcache.tags.occ_blocks::cpu.data 83.261165 # Average occupied blocks per requestor 801system.cpu.dcache.tags.occ_percent::cpu.data 0.020327 # Average percentage of cache occupancy 802system.cpu.dcache.tags.occ_percent::total 0.020327 # Average percentage of cache occupancy |
| 766system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 767system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 768system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id 769system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id | 803system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 804system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 805system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id 806system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id |
| 770system.cpu.dcache.tags.tag_accesses 5234 # Number of tag accesses 771system.cpu.dcache.tags.data_accesses 5234 # Number of data accesses 772system.cpu.dcache.ReadReq_hits::cpu.data 1479 # number of ReadReq hits 773system.cpu.dcache.ReadReq_hits::total 1479 # number of ReadReq hits | 807system.cpu.dcache.tags.tag_accesses 5232 # Number of tag accesses 808system.cpu.dcache.tags.data_accesses 5232 # Number of data accesses 809system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits 810system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits |
| 774system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits 775system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits | 811system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits 812system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits |
| 776system.cpu.dcache.demand_hits::cpu.data 2337 # number of demand (read+write) hits 777system.cpu.dcache.demand_hits::total 2337 # number of demand (read+write) hits 778system.cpu.dcache.overall_hits::cpu.data 2337 # number of overall hits 779system.cpu.dcache.overall_hits::total 2337 # number of overall hits 780system.cpu.dcache.ReadReq_misses::cpu.data 132 # number of ReadReq misses 781system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses | 813system.cpu.dcache.demand_hits::cpu.data 2335 # number of demand (read+write) hits 814system.cpu.dcache.demand_hits::total 2335 # number of demand (read+write) hits 815system.cpu.dcache.overall_hits::cpu.data 2335 # number of overall hits 816system.cpu.dcache.overall_hits::total 2335 # number of overall hits 817system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses 818system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses |
| 782system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses 783system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses | 819system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses 820system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses |
| 784system.cpu.dcache.demand_misses::cpu.data 209 # number of demand (read+write) misses 785system.cpu.dcache.demand_misses::total 209 # number of demand (read+write) misses 786system.cpu.dcache.overall_misses::cpu.data 209 # number of overall misses 787system.cpu.dcache.overall_misses::total 209 # number of overall misses 788system.cpu.dcache.ReadReq_miss_latency::cpu.data 9669000 # number of ReadReq miss cycles 789system.cpu.dcache.ReadReq_miss_latency::total 9669000 # number of ReadReq miss cycles 790system.cpu.dcache.WriteReq_miss_latency::cpu.data 5702500 # number of WriteReq miss cycles 791system.cpu.dcache.WriteReq_miss_latency::total 5702500 # number of WriteReq miss cycles 792system.cpu.dcache.demand_miss_latency::cpu.data 15371500 # number of demand (read+write) miss cycles 793system.cpu.dcache.demand_miss_latency::total 15371500 # number of demand (read+write) miss cycles 794system.cpu.dcache.overall_miss_latency::cpu.data 15371500 # number of overall miss cycles 795system.cpu.dcache.overall_miss_latency::total 15371500 # number of overall miss cycles 796system.cpu.dcache.ReadReq_accesses::cpu.data 1611 # number of ReadReq accesses(hits+misses) 797system.cpu.dcache.ReadReq_accesses::total 1611 # number of ReadReq accesses(hits+misses) | 821system.cpu.dcache.demand_misses::cpu.data 210 # number of demand (read+write) misses 822system.cpu.dcache.demand_misses::total 210 # number of demand (read+write) misses 823system.cpu.dcache.overall_misses::cpu.data 210 # number of overall misses 824system.cpu.dcache.overall_misses::total 210 # number of overall misses 825system.cpu.dcache.ReadReq_miss_latency::cpu.data 9645750 # number of ReadReq miss cycles 826system.cpu.dcache.ReadReq_miss_latency::total 9645750 # number of ReadReq miss cycles 827system.cpu.dcache.WriteReq_miss_latency::cpu.data 5703500 # number of WriteReq miss cycles 828system.cpu.dcache.WriteReq_miss_latency::total 5703500 # number of WriteReq miss cycles 829system.cpu.dcache.demand_miss_latency::cpu.data 15349250 # number of demand (read+write) miss cycles 830system.cpu.dcache.demand_miss_latency::total 15349250 # number of demand (read+write) miss cycles 831system.cpu.dcache.overall_miss_latency::cpu.data 15349250 # number of overall miss cycles 832system.cpu.dcache.overall_miss_latency::total 15349250 # number of overall miss cycles 833system.cpu.dcache.ReadReq_accesses::cpu.data 1610 # number of ReadReq accesses(hits+misses) 834system.cpu.dcache.ReadReq_accesses::total 1610 # number of ReadReq accesses(hits+misses) |
| 798system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 799system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) | 835system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 836system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) |
| 800system.cpu.dcache.demand_accesses::cpu.data 2546 # number of demand (read+write) accesses 801system.cpu.dcache.demand_accesses::total 2546 # number of demand (read+write) accesses 802system.cpu.dcache.overall_accesses::cpu.data 2546 # number of overall (read+write) accesses 803system.cpu.dcache.overall_accesses::total 2546 # number of overall (read+write) accesses 804system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081937 # miss rate for ReadReq accesses 805system.cpu.dcache.ReadReq_miss_rate::total 0.081937 # miss rate for ReadReq accesses | 837system.cpu.dcache.demand_accesses::cpu.data 2545 # number of demand (read+write) accesses 838system.cpu.dcache.demand_accesses::total 2545 # number of demand (read+write) accesses 839system.cpu.dcache.overall_accesses::cpu.data 2545 # number of overall (read+write) accesses 840system.cpu.dcache.overall_accesses::total 2545 # number of overall (read+write) accesses 841system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082609 # miss rate for ReadReq accesses 842system.cpu.dcache.ReadReq_miss_rate::total 0.082609 # miss rate for ReadReq accesses |
| 806system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses 807system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses | 843system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses 844system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses |
| 808system.cpu.dcache.demand_miss_rate::cpu.data 0.082090 # miss rate for demand accesses 809system.cpu.dcache.demand_miss_rate::total 0.082090 # miss rate for demand accesses 810system.cpu.dcache.overall_miss_rate::cpu.data 0.082090 # miss rate for overall accesses 811system.cpu.dcache.overall_miss_rate::total 0.082090 # miss rate for overall accesses 812system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73250 # average ReadReq miss latency 813system.cpu.dcache.ReadReq_avg_miss_latency::total 73250 # average ReadReq miss latency 814system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74058.441558 # average WriteReq miss latency 815system.cpu.dcache.WriteReq_avg_miss_latency::total 74058.441558 # average WriteReq miss latency 816system.cpu.dcache.demand_avg_miss_latency::cpu.data 73547.846890 # average overall miss latency 817system.cpu.dcache.demand_avg_miss_latency::total 73547.846890 # average overall miss latency 818system.cpu.dcache.overall_avg_miss_latency::cpu.data 73547.846890 # average overall miss latency 819system.cpu.dcache.overall_avg_miss_latency::total 73547.846890 # average overall miss latency | 845system.cpu.dcache.demand_miss_rate::cpu.data 0.082515 # miss rate for demand accesses 846system.cpu.dcache.demand_miss_rate::total 0.082515 # miss rate for demand accesses 847system.cpu.dcache.overall_miss_rate::cpu.data 0.082515 # miss rate for overall accesses 848system.cpu.dcache.overall_miss_rate::total 0.082515 # miss rate for overall accesses 849system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72524.436090 # average ReadReq miss latency 850system.cpu.dcache.ReadReq_avg_miss_latency::total 72524.436090 # average ReadReq miss latency 851system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74071.428571 # average WriteReq miss latency 852system.cpu.dcache.WriteReq_avg_miss_latency::total 74071.428571 # average WriteReq miss latency 853system.cpu.dcache.demand_avg_miss_latency::cpu.data 73091.666667 # average overall miss latency 854system.cpu.dcache.demand_avg_miss_latency::total 73091.666667 # average overall miss latency 855system.cpu.dcache.overall_avg_miss_latency::cpu.data 73091.666667 # average overall miss latency 856system.cpu.dcache.overall_avg_miss_latency::total 73091.666667 # average overall miss latency |
| 820system.cpu.dcache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked 821system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 822system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 823system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 824system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.750000 # average number of cycles each access was blocked 825system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 826system.cpu.dcache.fast_writes 0 # number of fast writes performed 827system.cpu.dcache.cache_copies 0 # number of cache copies performed | 857system.cpu.dcache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked 858system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 859system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 860system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 861system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.750000 # average number of cycles each access was blocked 862system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 863system.cpu.dcache.fast_writes 0 # number of fast writes performed 864system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 828system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits 829system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits 830system.cpu.dcache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits 831system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits 832system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits 833system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits | 865system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits 866system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits 867system.cpu.dcache.demand_mshr_hits::cpu.data 67 # number of demand (read+write) MSHR hits 868system.cpu.dcache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits 869system.cpu.dcache.overall_mshr_hits::cpu.data 67 # number of overall MSHR hits 870system.cpu.dcache.overall_mshr_hits::total 67 # number of overall MSHR hits |
| 834system.cpu.dcache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses 835system.cpu.dcache.ReadReq_mshr_misses::total 66 # number of ReadReq MSHR misses 836system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses 837system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses 838system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses 839system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses 840system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses 841system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses | 871system.cpu.dcache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses 872system.cpu.dcache.ReadReq_mshr_misses::total 66 # number of ReadReq MSHR misses 873system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses 874system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses 875system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses 876system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses 877system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses 878system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses |
| 842system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5340000 # number of ReadReq MSHR miss cycles 843system.cpu.dcache.ReadReq_mshr_miss_latency::total 5340000 # number of ReadReq MSHR miss cycles 844system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5521500 # number of WriteReq MSHR miss cycles 845system.cpu.dcache.WriteReq_mshr_miss_latency::total 5521500 # number of WriteReq MSHR miss cycles 846system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10861500 # number of demand (read+write) MSHR miss cycles 847system.cpu.dcache.demand_mshr_miss_latency::total 10861500 # number of demand (read+write) MSHR miss cycles 848system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10861500 # number of overall MSHR miss cycles 849system.cpu.dcache.overall_mshr_miss_latency::total 10861500 # number of overall MSHR miss cycles 850system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040968 # mshr miss rate for ReadReq accesses 851system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040968 # mshr miss rate for ReadReq accesses | 879system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287250 # number of ReadReq MSHR miss cycles 880system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287250 # number of ReadReq MSHR miss cycles 881system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5522500 # number of WriteReq MSHR miss cycles 882system.cpu.dcache.WriteReq_mshr_miss_latency::total 5522500 # number of WriteReq MSHR miss cycles 883system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10809750 # number of demand (read+write) MSHR miss cycles 884system.cpu.dcache.demand_mshr_miss_latency::total 10809750 # number of demand (read+write) MSHR miss cycles 885system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10809750 # number of overall MSHR miss cycles 886system.cpu.dcache.overall_mshr_miss_latency::total 10809750 # number of overall MSHR miss cycles 887system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040994 # mshr miss rate for ReadReq accesses 888system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040994 # mshr miss rate for ReadReq accesses |
| 852system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses 853system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses | 889system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses 890system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses |
| 854system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for demand accesses 855system.cpu.dcache.demand_mshr_miss_rate::total 0.056167 # mshr miss rate for demand accesses 856system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for overall accesses 857system.cpu.dcache.overall_mshr_miss_rate::total 0.056167 # mshr miss rate for overall accesses 858system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80909.090909 # average ReadReq mshr miss latency 859system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80909.090909 # average ReadReq mshr miss latency 860system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71707.792208 # average WriteReq mshr miss latency 861system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71707.792208 # average WriteReq mshr miss latency 862system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75954.545455 # average overall mshr miss latency 863system.cpu.dcache.demand_avg_mshr_miss_latency::total 75954.545455 # average overall mshr miss latency 864system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75954.545455 # average overall mshr miss latency 865system.cpu.dcache.overall_avg_mshr_miss_latency::total 75954.545455 # average overall mshr miss latency | 891system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056189 # mshr miss rate for demand accesses 892system.cpu.dcache.demand_mshr_miss_rate::total 0.056189 # mshr miss rate for demand accesses 893system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056189 # mshr miss rate for overall accesses 894system.cpu.dcache.overall_mshr_miss_rate::total 0.056189 # mshr miss rate for overall accesses 895system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80109.848485 # average ReadReq mshr miss latency 896system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80109.848485 # average ReadReq mshr miss latency 897system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71720.779221 # average WriteReq mshr miss latency 898system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71720.779221 # average WriteReq mshr miss latency 899system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75592.657343 # average overall mshr miss latency 900system.cpu.dcache.demand_avg_mshr_miss_latency::total 75592.657343 # average overall mshr miss latency 901system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75592.657343 # average overall mshr miss latency 902system.cpu.dcache.overall_avg_mshr_miss_latency::total 75592.657343 # average overall mshr miss latency |
| 866system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 867 868---------- End Simulation Statistics ---------- | 903system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 904 905---------- End Simulation Statistics ---------- |