1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000013 # Number of seconds simulated |
4sim_ticks 12607000 # Number of ticks simulated 5final_tick 12607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 20393 # Simulator instruction rate (inst/s) 8host_op_rate 36936 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47780701 # Simulator tick rate (ticks/s) 10host_mem_usage 271708 # Number of bytes of host memory used |
11host_seconds 0.26 # Real time elapsed on the host 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9745 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 19456 # Number of bytes read from this memory |
15system.physmem.bytes_read::cpu.data 9216 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28672 # Number of bytes read from this memory |
17system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 304 # Number of read requests responded to by this memory |
20system.physmem.num_reads::cpu.data 144 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 448 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1543269612 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 731022448 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2274292060 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1543269612 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1543269612 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1543269612 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 731022448 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2274292060 # Total bandwidth to/from this memory (bytes/s) |
30system.cpu.workload.num_syscalls 11 # Number of system calls |
31system.cpu.numCycles 25215 # number of cpu cycles simulated |
32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
34system.cpu.BPredUnit.lookups 3186 # Number of BP lookups 35system.cpu.BPredUnit.condPredicted 3186 # Number of conditional branches predicted 36system.cpu.BPredUnit.condIncorrect 582 # Number of conditional branches incorrect 37system.cpu.BPredUnit.BTBLookups 2623 # Number of BTB lookups 38system.cpu.BPredUnit.BTBHits 777 # Number of BTB hits |
39system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 40system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 41system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. |
42system.cpu.fetch.icacheStallCycles 8059 # Number of cycles fetch is stalled on an Icache miss 43system.cpu.fetch.Insts 15139 # Number of instructions fetch has processed 44system.cpu.fetch.Branches 3186 # Number of branches that fetch encountered 45system.cpu.fetch.predictedBranches 777 # Number of branches that fetch has predicted taken 46system.cpu.fetch.Cycles 4132 # Number of cycles fetch has run and was not squashing or blocked 47system.cpu.fetch.SquashCycles 2534 # Number of cycles fetch has spent squashing 48system.cpu.fetch.BlockedCycles 3329 # Number of cycles fetch has spent blocked 49system.cpu.fetch.MiscStallCycles 20 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 50system.cpu.fetch.PendingTrapStallCycles 126 # Number of stall cycles due to pending traps 51system.cpu.fetch.CacheLines 1963 # Number of cache lines fetched 52system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed 53system.cpu.fetch.rateDist::samples 17595 # Number of instructions fetched each cycle (Total) 54system.cpu.fetch.rateDist::mean 1.538335 # Number of instructions fetched each cycle (Total) 55system.cpu.fetch.rateDist::stdev 3.007747 # Number of instructions fetched each cycle (Total) |
56system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
57system.cpu.fetch.rateDist::0 13576 77.16% 77.16% # Number of instructions fetched each cycle (Total) 58system.cpu.fetch.rateDist::1 181 1.03% 78.19% # Number of instructions fetched each cycle (Total) 59system.cpu.fetch.rateDist::2 155 0.88% 79.07% # Number of instructions fetched each cycle (Total) 60system.cpu.fetch.rateDist::3 205 1.17% 80.23% # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.rateDist::4 167 0.95% 81.18% # Number of instructions fetched each cycle (Total) 62system.cpu.fetch.rateDist::5 166 0.94% 82.13% # Number of instructions fetched each cycle (Total) 63system.cpu.fetch.rateDist::6 255 1.45% 83.57% # Number of instructions fetched each cycle (Total) 64system.cpu.fetch.rateDist::7 187 1.06% 84.64% # Number of instructions fetched each cycle (Total) 65system.cpu.fetch.rateDist::8 2703 15.36% 100.00% # Number of instructions fetched each cycle (Total) |
66system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 67system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 68system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
69system.cpu.fetch.rateDist::total 17595 # Number of instructions fetched each cycle (Total) 70system.cpu.fetch.branchRate 0.126353 # Number of branch fetches per cycle 71system.cpu.fetch.rate 0.600397 # Number of inst fetches per cycle 72system.cpu.decode.IdleCycles 8491 # Number of cycles decode is idle 73system.cpu.decode.BlockedCycles 3340 # Number of cycles decode is blocked 74system.cpu.decode.RunCycles 3724 # Number of cycles decode is running 75system.cpu.decode.UnblockCycles 111 # Number of cycles decode is unblocking 76system.cpu.decode.SquashCycles 1929 # Number of cycles decode is squashing 77system.cpu.decode.DecodedInsts 25781 # Number of instructions handled by decode 78system.cpu.rename.SquashCycles 1929 # Number of cycles rename is squashing 79system.cpu.rename.IdleCycles 8836 # Number of cycles rename is idle 80system.cpu.rename.BlockCycles 2060 # Number of cycles rename is blocking 81system.cpu.rename.serializeStallCycles 411 # count of cycles rename stalled for serializing inst 82system.cpu.rename.RunCycles 3455 # Number of cycles rename is running 83system.cpu.rename.UnblockCycles 904 # Number of cycles rename is unblocking 84system.cpu.rename.RenamedInsts 24174 # Number of instructions processed by rename 85system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full 86system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full 87system.cpu.rename.LSQFullEvents 785 # Number of times rename has blocked due to LSQ full 88system.cpu.rename.RenamedOperands 26591 # Number of destination operands rename has renamed 89system.cpu.rename.RenameLookups 58087 # Number of register rename lookups that rename has made 90system.cpu.rename.int_rename_lookups 58071 # Number of integer rename lookups |
91system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups |
92system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed 93system.cpu.rename.UndoneMaps 15531 # Number of HB maps that are undone due to squashing 94system.cpu.rename.serializingInsts 32 # count of serializing insts renamed 95system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed 96system.cpu.rename.skidInsts 2042 # count of insts added to the skid buffer 97system.cpu.memDep0.insertedLoads 2405 # Number of loads inserted to the mem dependence unit. 98system.cpu.memDep0.insertedStores 1780 # Number of stores inserted to the mem dependence unit. 99system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. 100system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. 101system.cpu.iq.iqInstsAdded 21436 # Number of instructions added to the IQ (excludes non-spec) 102system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ 103system.cpu.iq.iqInstsIssued 18052 # Number of instructions issued 104system.cpu.iq.iqSquashedInstsIssued 228 # Number of squashed instructions issued 105system.cpu.iq.iqSquashedInstsExamined 10867 # Number of squashed instructions iterated over during squash; mainly for profiling 106system.cpu.iq.iqSquashedOperandsExamined 14920 # Number of squashed operands that are examined and possibly removed from graph 107system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed 108system.cpu.iq.issued_per_cycle::samples 17595 # Number of insts issued each cycle 109system.cpu.iq.issued_per_cycle::mean 1.025973 # Number of insts issued each cycle 110system.cpu.iq.issued_per_cycle::stdev 1.871104 # Number of insts issued each cycle |
111system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
112system.cpu.iq.issued_per_cycle::0 12050 68.49% 68.49% # Number of insts issued each cycle 113system.cpu.iq.issued_per_cycle::1 1507 8.56% 77.05% # Number of insts issued each cycle 114system.cpu.iq.issued_per_cycle::2 947 5.38% 82.43% # Number of insts issued each cycle 115system.cpu.iq.issued_per_cycle::3 676 3.84% 86.27% # Number of insts issued each cycle 116system.cpu.iq.issued_per_cycle::4 766 4.35% 90.63% # Number of insts issued each cycle 117system.cpu.iq.issued_per_cycle::5 693 3.94% 94.57% # Number of insts issued each cycle 118system.cpu.iq.issued_per_cycle::6 642 3.65% 98.22% # Number of insts issued each cycle 119system.cpu.iq.issued_per_cycle::7 270 1.53% 99.75% # Number of insts issued each cycle 120system.cpu.iq.issued_per_cycle::8 44 0.25% 100.00% # Number of insts issued each cycle |
121system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 122system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 123system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
124system.cpu.iq.issued_per_cycle::total 17595 # Number of insts issued each cycle |
125system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
126system.cpu.iq.fu_full::IntAlu 141 77.47% 77.47% # attempts to use FU when none available 127system.cpu.iq.fu_full::IntMult 0 0.00% 77.47% # attempts to use FU when none available 128system.cpu.iq.fu_full::IntDiv 0 0.00% 77.47% # attempts to use FU when none available 129system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.47% # attempts to use FU when none available 130system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.47% # attempts to use FU when none available 131system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.47% # attempts to use FU when none available 132system.cpu.iq.fu_full::FloatMult 0 0.00% 77.47% # attempts to use FU when none available 133system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.47% # attempts to use FU when none available 134system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.47% # attempts to use FU when none available 135system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.47% # attempts to use FU when none available 136system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.47% # attempts to use FU when none available 137system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.47% # attempts to use FU when none available 138system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.47% # attempts to use FU when none available 139system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.47% # attempts to use FU when none available 140system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.47% # attempts to use FU when none available 141system.cpu.iq.fu_full::SimdMult 0 0.00% 77.47% # attempts to use FU when none available 142system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.47% # attempts to use FU when none available 143system.cpu.iq.fu_full::SimdShift 0 0.00% 77.47% # attempts to use FU when none available 144system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.47% # attempts to use FU when none available 145system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.47% # attempts to use FU when none available 146system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.47% # attempts to use FU when none available 147system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.47% # attempts to use FU when none available 148system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.47% # attempts to use FU when none available 149system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.47% # attempts to use FU when none available 150system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.47% # attempts to use FU when none available 151system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.47% # attempts to use FU when none available 152system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.47% # attempts to use FU when none available 153system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.47% # attempts to use FU when none available 154system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.47% # attempts to use FU when none available 155system.cpu.iq.fu_full::MemRead 21 11.54% 89.01% # attempts to use FU when none available 156system.cpu.iq.fu_full::MemWrite 20 10.99% 100.00% # attempts to use FU when none available |
157system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 158system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 159system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued |
160system.cpu.iq.FU_type_0::IntAlu 14462 80.11% 80.14% # Type of FU issued 161system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.14% # Type of FU issued 162system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.14% # Type of FU issued 163system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.14% # Type of FU issued 164system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.14% # Type of FU issued 165system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.14% # Type of FU issued 166system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.14% # Type of FU issued 167system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.14% # Type of FU issued 168system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued 169system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued 170system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued 171system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued 172system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued 173system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued 174system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued 175system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued 176system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued 177system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued 178system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued 179system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued 180system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued 181system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued 182system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued 183system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued 184system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued 185system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued 186system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued 187system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued 188system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued 189system.cpu.iq.FU_type_0::MemRead 2078 11.51% 91.65% # Type of FU issued 190system.cpu.iq.FU_type_0::MemWrite 1508 8.35% 100.00% # Type of FU issued |
191system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 192system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
193system.cpu.iq.FU_type_0::total 18052 # Type of FU issued 194system.cpu.iq.rate 0.715923 # Inst issue rate 195system.cpu.iq.fu_busy_cnt 182 # FU busy when requested 196system.cpu.iq.fu_busy_rate 0.010082 # FU busy rate (busy events/executed inst) 197system.cpu.iq.int_inst_queue_reads 54101 # Number of integer instruction queue reads 198system.cpu.iq.int_inst_queue_writes 32345 # Number of integer instruction queue writes 199system.cpu.iq.int_inst_queue_wakeup_accesses 16592 # Number of integer instruction queue wakeup accesses |
200system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 201system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 202system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses |
203system.cpu.iq.int_alu_accesses 18226 # Number of integer alu accesses |
204system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses |
205system.cpu.iew.lsq.thread0.forwLoads 132 # Number of loads that had data forwarded from stores |
206system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
207system.cpu.iew.lsq.thread0.squashedLoads 1353 # Number of loads squashed 208system.cpu.iew.lsq.thread0.ignoredResponses 19 # Number of memory responses ignored because the instruction is squashed 209system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations 210system.cpu.iew.lsq.thread0.squashedStores 846 # Number of stores squashed |
211system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 212system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 213system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 214system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 215system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
216system.cpu.iew.iewSquashCycles 1929 # Number of cycles IEW is squashing 217system.cpu.iew.iewBlockCycles 1486 # Number of cycles IEW is blocking 218system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking 219system.cpu.iew.iewDispatchedInsts 21473 # Number of instructions dispatched to IQ 220system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch 221system.cpu.iew.iewDispLoadInsts 2405 # Number of dispatched load instructions 222system.cpu.iew.iewDispStoreInsts 1780 # Number of dispatched store instructions 223system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions 224system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall |
225system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
226system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations 227system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly 228system.cpu.iew.predictedNotTakenIncorrect 642 # Number of branches that were predicted not taken incorrectly 229system.cpu.iew.branchMispredicts 708 # Number of branch mispredicts detected at execute 230system.cpu.iew.iewExecutedInsts 17072 # Number of executed instructions 231system.cpu.iew.iewExecLoadInsts 1925 # Number of load instructions executed 232system.cpu.iew.iewExecSquashedInsts 980 # Number of squashed instructions skipped in execute |
233system.cpu.iew.exec_swp 0 # number of swp insts executed 234system.cpu.iew.exec_nop 0 # number of nop insts executed |
235system.cpu.iew.exec_refs 3318 # number of memory reference insts executed 236system.cpu.iew.exec_branches 1690 # Number of branches executed 237system.cpu.iew.exec_stores 1393 # Number of stores executed 238system.cpu.iew.exec_rate 0.677057 # Inst execution rate 239system.cpu.iew.wb_sent 16795 # cumulative count of insts sent to commit 240system.cpu.iew.wb_count 16596 # cumulative count of insts written-back 241system.cpu.iew.wb_producers 10614 # num instructions producing a value 242system.cpu.iew.wb_consumers 16437 # num instructions consuming a value |
243system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
244system.cpu.iew.wb_rate 0.658180 # insts written-back per cycle 245system.cpu.iew.wb_fanout 0.645738 # average fanout of values written-back |
246system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 247system.cpu.commit.commitCommittedInsts 5380 # The number of committed instructions 248system.cpu.commit.commitCommittedOps 9745 # The number of committed instructions |
249system.cpu.commit.commitSquashedInsts 11727 # The number of squashed insts skipped by commit |
250system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards |
251system.cpu.commit.branchMispredicts 596 # The number of times a branch was mispredicted 252system.cpu.commit.committed_per_cycle::samples 15666 # Number of insts commited each cycle 253system.cpu.commit.committed_per_cycle::mean 0.622048 # Number of insts commited each cycle 254system.cpu.commit.committed_per_cycle::stdev 1.485565 # Number of insts commited each cycle |
255system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
256system.cpu.commit.committed_per_cycle::0 12031 76.80% 76.80% # Number of insts commited each cycle 257system.cpu.commit.committed_per_cycle::1 1491 9.52% 86.31% # Number of insts commited each cycle 258system.cpu.commit.committed_per_cycle::2 525 3.35% 89.67% # Number of insts commited each cycle 259system.cpu.commit.committed_per_cycle::3 708 4.52% 94.18% # Number of insts commited each cycle 260system.cpu.commit.committed_per_cycle::4 369 2.36% 96.54% # Number of insts commited each cycle 261system.cpu.commit.committed_per_cycle::5 134 0.86% 97.40% # Number of insts commited each cycle 262system.cpu.commit.committed_per_cycle::6 127 0.81% 98.21% # Number of insts commited each cycle 263system.cpu.commit.committed_per_cycle::7 76 0.49% 98.69% # Number of insts commited each cycle 264system.cpu.commit.committed_per_cycle::8 205 1.31% 100.00% # Number of insts commited each cycle |
265system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 266system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 267system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
268system.cpu.commit.committed_per_cycle::total 15666 # Number of insts commited each cycle |
269system.cpu.commit.committedInsts 5380 # Number of instructions committed 270system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed 271system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 272system.cpu.commit.refs 1986 # Number of memory references committed 273system.cpu.commit.loads 1052 # Number of loads committed 274system.cpu.commit.membars 0 # Number of memory barriers committed 275system.cpu.commit.branches 1208 # Number of branches committed 276system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 277system.cpu.commit.int_insts 9650 # Number of committed integer instructions. 278system.cpu.commit.function_calls 0 # Number of function calls committed. |
279system.cpu.commit.bw_lim_events 205 # number cycles where commit BW limit reached |
280system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
281system.cpu.rob.rob_reads 36933 # The number of ROB reads 282system.cpu.rob.rob_writes 44901 # The number of ROB writes 283system.cpu.timesIdled 145 # Number of times that the entire CPU went into an idle state and unscheduled itself 284system.cpu.idleCycles 7620 # Total number of cycles that the CPU has spent unscheduled due to idling |
285system.cpu.committedInsts 5380 # Number of Instructions Simulated 286system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated 287system.cpu.committedInsts_total 5380 # Number of Instructions Simulated |
288system.cpu.cpi 4.686803 # CPI: Cycles Per Instruction 289system.cpu.cpi_total 4.686803 # CPI: Total CPI of All Threads 290system.cpu.ipc 0.213365 # IPC: Instructions Per Cycle 291system.cpu.ipc_total 0.213365 # IPC: Total IPC of All Threads 292system.cpu.int_regfile_reads 30057 # number of integer regfile reads 293system.cpu.int_regfile_writes 17963 # number of integer regfile writes |
294system.cpu.fp_regfile_reads 4 # number of floating regfile reads |
295system.cpu.misc_regfile_reads 7481 # number of misc regfile reads |
296system.cpu.icache.replacements 0 # number of replacements |
297system.cpu.icache.tagsinuse 145.992239 # Cycle average of tags in use 298system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. |
299system.cpu.icache.sampled_refs 305 # Sample count of references to valid blocks. |
300system.cpu.icache.avg_refs 5.134426 # Average number of references to valid blocks. |
301system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
302system.cpu.icache.occ_blocks::cpu.inst 145.992239 # Average occupied blocks per requestor 303system.cpu.icache.occ_percent::cpu.inst 0.071285 # Average percentage of cache occupancy 304system.cpu.icache.occ_percent::total 0.071285 # Average percentage of cache occupancy 305system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits 306system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits 307system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits 308system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits 309system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits 310system.cpu.icache.overall_hits::total 1566 # number of overall hits 311system.cpu.icache.ReadReq_misses::cpu.inst 397 # number of ReadReq misses 312system.cpu.icache.ReadReq_misses::total 397 # number of ReadReq misses 313system.cpu.icache.demand_misses::cpu.inst 397 # number of demand (read+write) misses 314system.cpu.icache.demand_misses::total 397 # number of demand (read+write) misses 315system.cpu.icache.overall_misses::cpu.inst 397 # number of overall misses 316system.cpu.icache.overall_misses::total 397 # number of overall misses 317system.cpu.icache.ReadReq_miss_latency::cpu.inst 14592000 # number of ReadReq miss cycles 318system.cpu.icache.ReadReq_miss_latency::total 14592000 # number of ReadReq miss cycles 319system.cpu.icache.demand_miss_latency::cpu.inst 14592000 # number of demand (read+write) miss cycles 320system.cpu.icache.demand_miss_latency::total 14592000 # number of demand (read+write) miss cycles 321system.cpu.icache.overall_miss_latency::cpu.inst 14592000 # number of overall miss cycles 322system.cpu.icache.overall_miss_latency::total 14592000 # number of overall miss cycles 323system.cpu.icache.ReadReq_accesses::cpu.inst 1963 # number of ReadReq accesses(hits+misses) 324system.cpu.icache.ReadReq_accesses::total 1963 # number of ReadReq accesses(hits+misses) 325system.cpu.icache.demand_accesses::cpu.inst 1963 # number of demand (read+write) accesses 326system.cpu.icache.demand_accesses::total 1963 # number of demand (read+write) accesses 327system.cpu.icache.overall_accesses::cpu.inst 1963 # number of overall (read+write) accesses 328system.cpu.icache.overall_accesses::total 1963 # number of overall (read+write) accesses 329system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.202241 # miss rate for ReadReq accesses 330system.cpu.icache.ReadReq_miss_rate::total 0.202241 # miss rate for ReadReq accesses 331system.cpu.icache.demand_miss_rate::cpu.inst 0.202241 # miss rate for demand accesses 332system.cpu.icache.demand_miss_rate::total 0.202241 # miss rate for demand accesses 333system.cpu.icache.overall_miss_rate::cpu.inst 0.202241 # miss rate for overall accesses 334system.cpu.icache.overall_miss_rate::total 0.202241 # miss rate for overall accesses 335system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36755.667506 # average ReadReq miss latency 336system.cpu.icache.ReadReq_avg_miss_latency::total 36755.667506 # average ReadReq miss latency 337system.cpu.icache.demand_avg_miss_latency::cpu.inst 36755.667506 # average overall miss latency 338system.cpu.icache.demand_avg_miss_latency::total 36755.667506 # average overall miss latency 339system.cpu.icache.overall_avg_miss_latency::cpu.inst 36755.667506 # average overall miss latency 340system.cpu.icache.overall_avg_miss_latency::total 36755.667506 # average overall miss latency |
341system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 342system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 343system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 344system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 345system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 346system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 347system.cpu.icache.fast_writes 0 # number of fast writes performed 348system.cpu.icache.cache_copies 0 # number of cache copies performed |
349system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits 350system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits 351system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits 352system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits 353system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits 354system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits |
355system.cpu.icache.ReadReq_mshr_misses::cpu.inst 305 # number of ReadReq MSHR misses 356system.cpu.icache.ReadReq_mshr_misses::total 305 # number of ReadReq MSHR misses 357system.cpu.icache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses 358system.cpu.icache.demand_mshr_misses::total 305 # number of demand (read+write) MSHR misses 359system.cpu.icache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses 360system.cpu.icache.overall_mshr_misses::total 305 # number of overall MSHR misses |
361system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11283000 # number of ReadReq MSHR miss cycles 362system.cpu.icache.ReadReq_mshr_miss_latency::total 11283000 # number of ReadReq MSHR miss cycles 363system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11283000 # number of demand (read+write) MSHR miss cycles 364system.cpu.icache.demand_mshr_miss_latency::total 11283000 # number of demand (read+write) MSHR miss cycles 365system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11283000 # number of overall MSHR miss cycles 366system.cpu.icache.overall_mshr_miss_latency::total 11283000 # number of overall MSHR miss cycles 367system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155374 # mshr miss rate for ReadReq accesses 368system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155374 # mshr miss rate for ReadReq accesses 369system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155374 # mshr miss rate for demand accesses 370system.cpu.icache.demand_mshr_miss_rate::total 0.155374 # mshr miss rate for demand accesses 371system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155374 # mshr miss rate for overall accesses 372system.cpu.icache.overall_mshr_miss_rate::total 0.155374 # mshr miss rate for overall accesses 373system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36993.442623 # average ReadReq mshr miss latency 374system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36993.442623 # average ReadReq mshr miss latency 375system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36993.442623 # average overall mshr miss latency 376system.cpu.icache.demand_avg_mshr_miss_latency::total 36993.442623 # average overall mshr miss latency 377system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36993.442623 # average overall mshr miss latency 378system.cpu.icache.overall_avg_mshr_miss_latency::total 36993.442623 # average overall mshr miss latency |
379system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 380system.cpu.dcache.replacements 0 # number of replacements |
381system.cpu.dcache.tagsinuse 83.306580 # Cycle average of tags in use 382system.cpu.dcache.total_refs 2452 # Total number of references to valid blocks. 383system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. 384system.cpu.dcache.avg_refs 17.146853 # Average number of references to valid blocks. |
385system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
386system.cpu.dcache.occ_blocks::cpu.data 83.306580 # Average occupied blocks per requestor 387system.cpu.dcache.occ_percent::cpu.data 0.020339 # Average percentage of cache occupancy 388system.cpu.dcache.occ_percent::total 0.020339 # Average percentage of cache occupancy 389system.cpu.dcache.ReadReq_hits::cpu.data 1594 # number of ReadReq hits 390system.cpu.dcache.ReadReq_hits::total 1594 # number of ReadReq hits |
391system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits 392system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits |
393system.cpu.dcache.demand_hits::cpu.data 2452 # number of demand (read+write) hits 394system.cpu.dcache.demand_hits::total 2452 # number of demand (read+write) hits 395system.cpu.dcache.overall_hits::cpu.data 2452 # number of overall hits 396system.cpu.dcache.overall_hits::total 2452 # number of overall hits 397system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses 398system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses |
399system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses 400system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses |
401system.cpu.dcache.demand_misses::cpu.data 209 # number of demand (read+write) misses 402system.cpu.dcache.demand_misses::total 209 # number of demand (read+write) misses 403system.cpu.dcache.overall_misses::cpu.data 209 # number of overall misses 404system.cpu.dcache.overall_misses::total 209 # number of overall misses 405system.cpu.dcache.ReadReq_miss_latency::cpu.data 5163500 # number of ReadReq miss cycles 406system.cpu.dcache.ReadReq_miss_latency::total 5163500 # number of ReadReq miss cycles 407system.cpu.dcache.WriteReq_miss_latency::cpu.data 3068500 # number of WriteReq miss cycles 408system.cpu.dcache.WriteReq_miss_latency::total 3068500 # number of WriteReq miss cycles 409system.cpu.dcache.demand_miss_latency::cpu.data 8232000 # number of demand (read+write) miss cycles 410system.cpu.dcache.demand_miss_latency::total 8232000 # number of demand (read+write) miss cycles 411system.cpu.dcache.overall_miss_latency::cpu.data 8232000 # number of overall miss cycles 412system.cpu.dcache.overall_miss_latency::total 8232000 # number of overall miss cycles 413system.cpu.dcache.ReadReq_accesses::cpu.data 1727 # number of ReadReq accesses(hits+misses) 414system.cpu.dcache.ReadReq_accesses::total 1727 # number of ReadReq accesses(hits+misses) |
415system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) 416system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) |
417system.cpu.dcache.demand_accesses::cpu.data 2661 # number of demand (read+write) accesses 418system.cpu.dcache.demand_accesses::total 2661 # number of demand (read+write) accesses 419system.cpu.dcache.overall_accesses::cpu.data 2661 # number of overall (read+write) accesses 420system.cpu.dcache.overall_accesses::total 2661 # number of overall (read+write) accesses 421system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077012 # miss rate for ReadReq accesses 422system.cpu.dcache.ReadReq_miss_rate::total 0.077012 # miss rate for ReadReq accesses |
423system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses 424system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses |
425system.cpu.dcache.demand_miss_rate::cpu.data 0.078542 # miss rate for demand accesses 426system.cpu.dcache.demand_miss_rate::total 0.078542 # miss rate for demand accesses 427system.cpu.dcache.overall_miss_rate::cpu.data 0.078542 # miss rate for overall accesses 428system.cpu.dcache.overall_miss_rate::total 0.078542 # miss rate for overall accesses 429system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38823.308271 # average ReadReq miss latency 430system.cpu.dcache.ReadReq_avg_miss_latency::total 38823.308271 # average ReadReq miss latency 431system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40375 # average WriteReq miss latency 432system.cpu.dcache.WriteReq_avg_miss_latency::total 40375 # average WriteReq miss latency 433system.cpu.dcache.demand_avg_miss_latency::cpu.data 39387.559809 # average overall miss latency 434system.cpu.dcache.demand_avg_miss_latency::total 39387.559809 # average overall miss latency 435system.cpu.dcache.overall_avg_miss_latency::cpu.data 39387.559809 # average overall miss latency 436system.cpu.dcache.overall_avg_miss_latency::total 39387.559809 # average overall miss latency |
437system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 438system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 439system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 440system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 441system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 442system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 443system.cpu.dcache.fast_writes 0 # number of fast writes performed 444system.cpu.dcache.cache_copies 0 # number of cache copies performed |
445system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits 446system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits 447system.cpu.dcache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits 448system.cpu.dcache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits 449system.cpu.dcache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits 450system.cpu.dcache.overall_mshr_hits::total 65 # number of overall MSHR hits 451system.cpu.dcache.ReadReq_mshr_misses::cpu.data 68 # number of ReadReq MSHR misses 452system.cpu.dcache.ReadReq_mshr_misses::total 68 # number of ReadReq MSHR misses |
453system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses 454system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses |
455system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses 456system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses 457system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses 458system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses 459system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2714500 # number of ReadReq MSHR miss cycles 460system.cpu.dcache.ReadReq_mshr_miss_latency::total 2714500 # number of ReadReq MSHR miss cycles 461system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2840500 # number of WriteReq MSHR miss cycles 462system.cpu.dcache.WriteReq_mshr_miss_latency::total 2840500 # number of WriteReq MSHR miss cycles 463system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5555000 # number of demand (read+write) MSHR miss cycles 464system.cpu.dcache.demand_mshr_miss_latency::total 5555000 # number of demand (read+write) MSHR miss cycles 465system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5555000 # number of overall MSHR miss cycles 466system.cpu.dcache.overall_mshr_miss_latency::total 5555000 # number of overall MSHR miss cycles 467system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039375 # mshr miss rate for ReadReq accesses 468system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039375 # mshr miss rate for ReadReq accesses |
469system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses 470system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses |
471system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054115 # mshr miss rate for demand accesses 472system.cpu.dcache.demand_mshr_miss_rate::total 0.054115 # mshr miss rate for demand accesses 473system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054115 # mshr miss rate for overall accesses 474system.cpu.dcache.overall_mshr_miss_rate::total 0.054115 # mshr miss rate for overall accesses 475system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39919.117647 # average ReadReq mshr miss latency 476system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39919.117647 # average ReadReq mshr miss latency 477system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37375 # average WriteReq mshr miss latency 478system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37375 # average WriteReq mshr miss latency 479system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38576.388889 # average overall mshr miss latency 480system.cpu.dcache.demand_avg_mshr_miss_latency::total 38576.388889 # average overall mshr miss latency 481system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38576.388889 # average overall mshr miss latency 482system.cpu.dcache.overall_avg_mshr_miss_latency::total 38576.388889 # average overall mshr miss latency |
483system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 484system.cpu.l2cache.replacements 0 # number of replacements |
485system.cpu.l2cache.tagsinuse 178.358150 # Cycle average of tags in use |
486system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. |
487system.cpu.l2cache.sampled_refs 371 # Sample count of references to valid blocks. 488system.cpu.l2cache.avg_refs 0.002695 # Average number of references to valid blocks. |
489system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
490system.cpu.l2cache.occ_blocks::cpu.inst 145.966975 # Average occupied blocks per requestor 491system.cpu.l2cache.occ_blocks::cpu.data 32.391174 # Average occupied blocks per requestor 492system.cpu.l2cache.occ_percent::cpu.inst 0.004455 # Average percentage of cache occupancy 493system.cpu.l2cache.occ_percent::cpu.data 0.000989 # Average percentage of cache occupancy 494system.cpu.l2cache.occ_percent::total 0.005443 # Average percentage of cache occupancy |
495system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 496system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 497system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 498system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 499system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 500system.cpu.l2cache.overall_hits::total 1 # number of overall hits 501system.cpu.l2cache.ReadReq_misses::cpu.inst 304 # number of ReadReq misses |
502system.cpu.l2cache.ReadReq_misses::cpu.data 68 # number of ReadReq misses 503system.cpu.l2cache.ReadReq_misses::total 372 # number of ReadReq misses |
504system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses 505system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses 506system.cpu.l2cache.demand_misses::cpu.inst 304 # number of demand (read+write) misses |
507system.cpu.l2cache.demand_misses::cpu.data 144 # number of demand (read+write) misses 508system.cpu.l2cache.demand_misses::total 448 # number of demand (read+write) misses |
509system.cpu.l2cache.overall_misses::cpu.inst 304 # number of overall misses |
510system.cpu.l2cache.overall_misses::cpu.data 144 # number of overall misses 511system.cpu.l2cache.overall_misses::total 448 # number of overall misses 512system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10974500 # number of ReadReq miss cycles 513system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2644000 # number of ReadReq miss cycles 514system.cpu.l2cache.ReadReq_miss_latency::total 13618500 # number of ReadReq miss cycles 515system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2762000 # number of ReadExReq miss cycles 516system.cpu.l2cache.ReadExReq_miss_latency::total 2762000 # number of ReadExReq miss cycles 517system.cpu.l2cache.demand_miss_latency::cpu.inst 10974500 # number of demand (read+write) miss cycles 518system.cpu.l2cache.demand_miss_latency::cpu.data 5406000 # number of demand (read+write) miss cycles 519system.cpu.l2cache.demand_miss_latency::total 16380500 # number of demand (read+write) miss cycles 520system.cpu.l2cache.overall_miss_latency::cpu.inst 10974500 # number of overall miss cycles 521system.cpu.l2cache.overall_miss_latency::cpu.data 5406000 # number of overall miss cycles 522system.cpu.l2cache.overall_miss_latency::total 16380500 # number of overall miss cycles |
523system.cpu.l2cache.ReadReq_accesses::cpu.inst 305 # number of ReadReq accesses(hits+misses) |
524system.cpu.l2cache.ReadReq_accesses::cpu.data 68 # number of ReadReq accesses(hits+misses) 525system.cpu.l2cache.ReadReq_accesses::total 373 # number of ReadReq accesses(hits+misses) |
526system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) 527system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) 528system.cpu.l2cache.demand_accesses::cpu.inst 305 # number of demand (read+write) accesses |
529system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses 530system.cpu.l2cache.demand_accesses::total 449 # number of demand (read+write) accesses |
531system.cpu.l2cache.overall_accesses::cpu.inst 305 # number of overall (read+write) accesses |
532system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses 533system.cpu.l2cache.overall_accesses::total 449 # number of overall (read+write) accesses |
534system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996721 # miss rate for ReadReq accesses 535system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses |
536system.cpu.l2cache.ReadReq_miss_rate::total 0.997319 # miss rate for ReadReq accesses |
537system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 538system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 539system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996721 # miss rate for demand accesses 540system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
541system.cpu.l2cache.demand_miss_rate::total 0.997773 # miss rate for demand accesses |
542system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996721 # miss rate for overall accesses 543system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
544system.cpu.l2cache.overall_miss_rate::total 0.997773 # miss rate for overall accesses 545system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36100.328947 # average ReadReq miss latency 546system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38882.352941 # average ReadReq miss latency 547system.cpu.l2cache.ReadReq_avg_miss_latency::total 36608.870968 # average ReadReq miss latency 548system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36342.105263 # average ReadExReq miss latency 549system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36342.105263 # average ReadExReq miss latency 550system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36100.328947 # average overall miss latency 551system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37541.666667 # average overall miss latency 552system.cpu.l2cache.demand_avg_miss_latency::total 36563.616071 # average overall miss latency 553system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36100.328947 # average overall miss latency 554system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37541.666667 # average overall miss latency 555system.cpu.l2cache.overall_avg_miss_latency::total 36563.616071 # average overall miss latency |
556system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 557system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 558system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 559system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 560system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 561system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 562system.cpu.l2cache.fast_writes 0 # number of fast writes performed 563system.cpu.l2cache.cache_copies 0 # number of cache copies performed 564system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses |
565system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 68 # number of ReadReq MSHR misses 566system.cpu.l2cache.ReadReq_mshr_misses::total 372 # number of ReadReq MSHR misses |
567system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses 568system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses 569system.cpu.l2cache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses |
570system.cpu.l2cache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses 571system.cpu.l2cache.demand_mshr_misses::total 448 # number of demand (read+write) MSHR misses |
572system.cpu.l2cache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses |
573system.cpu.l2cache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses 574system.cpu.l2cache.overall_mshr_misses::total 448 # number of overall MSHR misses 575system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10010000 # number of ReadReq MSHR miss cycles 576system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2437500 # number of ReadReq MSHR miss cycles 577system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12447500 # number of ReadReq MSHR miss cycles 578system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2532000 # number of ReadExReq MSHR miss cycles 579system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2532000 # number of ReadExReq MSHR miss cycles 580system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10010000 # number of demand (read+write) MSHR miss cycles 581system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4969500 # number of demand (read+write) MSHR miss cycles 582system.cpu.l2cache.demand_mshr_miss_latency::total 14979500 # number of demand (read+write) MSHR miss cycles 583system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10010000 # number of overall MSHR miss cycles 584system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4969500 # number of overall MSHR miss cycles 585system.cpu.l2cache.overall_mshr_miss_latency::total 14979500 # number of overall MSHR miss cycles |
586system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for ReadReq accesses 587system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses |
588system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997319 # mshr miss rate for ReadReq accesses |
589system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 590system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 591system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for demand accesses 592system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
593system.cpu.l2cache.demand_mshr_miss_rate::total 0.997773 # mshr miss rate for demand accesses |
594system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for overall accesses 595system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
596system.cpu.l2cache.overall_mshr_miss_rate::total 0.997773 # mshr miss rate for overall accesses 597system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32927.631579 # average ReadReq mshr miss latency 598system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35845.588235 # average ReadReq mshr miss latency 599system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33461.021505 # average ReadReq mshr miss latency 600system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33315.789474 # average ReadExReq mshr miss latency 601system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33315.789474 # average ReadExReq mshr miss latency 602system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32927.631579 # average overall mshr miss latency 603system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34510.416667 # average overall mshr miss latency 604system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33436.383929 # average overall mshr miss latency 605system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32927.631579 # average overall mshr miss latency 606system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34510.416667 # average overall mshr miss latency 607system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33436.383929 # average overall mshr miss latency |
608system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 609 610---------- End Simulation Statistics ---------- |