7,11c7,11
< host_inst_rate 27776 # Simulator instruction rate (inst/s)
< host_op_rate 50299 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 62542635 # Simulator tick rate (ticks/s)
< host_mem_usage 245428 # Number of bytes of host memory used
< host_seconds 0.20 # Real time elapsed on the host
---
> host_inst_rate 39950 # Simulator instruction rate (inst/s)
> host_op_rate 72345 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 89952499 # Simulator tick rate (ticks/s)
> host_mem_usage 224288 # Number of bytes of host memory used
> host_seconds 0.14 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 28864 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 19328 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 451 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 2366289556 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1584522053 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 2366289556 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 19328 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9536 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28864 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 19328 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 19328 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 302 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 149 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 451 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1584522053 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 781767503 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2366289556 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1584522053 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1584522053 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1584522053 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 781767503 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2366289556 # Total bandwidth to/from this memory (bytes/s)
323a331
> system.cpu.icache.ReadReq_miss_rate::total 0.199897 # miss rate for ReadReq accesses
324a333
> system.cpu.icache.demand_miss_rate::total 0.199897 # miss rate for demand accesses
325a335
> system.cpu.icache.overall_miss_rate::total 0.199897 # miss rate for overall accesses
326a337
> system.cpu.icache.ReadReq_avg_miss_latency::total 35555.128205 # average ReadReq miss latency
327a339
> system.cpu.icache.demand_avg_miss_latency::total 35555.128205 # average overall miss latency
328a341
> system.cpu.icache.overall_avg_miss_latency::total 35555.128205 # average overall miss latency
355a369
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155818 # mshr miss rate for ReadReq accesses
356a371
> system.cpu.icache.demand_mshr_miss_rate::total 0.155818 # mshr miss rate for demand accesses
357a373
> system.cpu.icache.overall_mshr_miss_rate::total 0.155818 # mshr miss rate for overall accesses
358a375
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35154.605263 # average ReadReq mshr miss latency
359a377
> system.cpu.icache.demand_avg_mshr_miss_latency::total 35154.605263 # average overall mshr miss latency
360a379
> system.cpu.icache.overall_avg_mshr_miss_latency::total 35154.605263 # average overall mshr miss latency
403a423
> system.cpu.dcache.ReadReq_miss_rate::total 0.070900 # miss rate for ReadReq accesses
404a425
> system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses
405a427
> system.cpu.dcache.demand_miss_rate::total 0.074726 # miss rate for demand accesses
406a429
> system.cpu.dcache.overall_miss_rate::total 0.074726 # miss rate for overall accesses
407a431
> system.cpu.dcache.ReadReq_avg_miss_latency::total 35047.826087 # average ReadReq miss latency
408a433
> system.cpu.dcache.WriteReq_avg_miss_latency::total 38388.157895 # average WriteReq miss latency
409a435
> system.cpu.dcache.demand_avg_miss_latency::total 36376.963351 # average overall miss latency
410a437
> system.cpu.dcache.overall_avg_miss_latency::total 36376.963351 # average overall miss latency
441a469
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045006 # mshr miss rate for ReadReq accesses
442a471
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses
443a473
> system.cpu.dcache.demand_mshr_miss_rate::total 0.058294 # mshr miss rate for demand accesses
444a475
> system.cpu.dcache.overall_mshr_miss_rate::total 0.058294 # mshr miss rate for overall accesses
445a477
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35260.273973 # average ReadReq mshr miss latency
446a479
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35388.157895 # average WriteReq mshr miss latency
447a481
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 35325.503356 # average overall mshr miss latency
448a483
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 35325.503356 # average overall mshr miss latency
501a537
> system.cpu.l2cache.ReadReq_miss_rate::total 0.994695 # miss rate for ReadReq accesses
502a539
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
504a542
> system.cpu.l2cache.demand_miss_rate::total 0.995585 # miss rate for demand accesses
506a545
> system.cpu.l2cache.overall_miss_rate::total 0.995585 # miss rate for overall accesses
508a548
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34278.666667 # average ReadReq miss latency
509a550
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34250 # average ReadExReq miss latency
511a553
> system.cpu.l2cache.demand_avg_miss_latency::total 34273.835920 # average overall miss latency
513a556
> system.cpu.l2cache.overall_avg_miss_latency::total 34273.835920 # average overall miss latency
545a589
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994695 # mshr miss rate for ReadReq accesses
546a591
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
548a594
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.995585 # mshr miss rate for demand accesses
550a597
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.995585 # mshr miss rate for overall accesses
552a600
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.666667 # average ReadReq mshr miss latency
553a602
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31177.631579 # average ReadExReq mshr miss latency
555a605
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency
557a608
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency
< host_inst_rate 27776 # Simulator instruction rate (inst/s)
< host_op_rate 50299 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 62542635 # Simulator tick rate (ticks/s)
< host_mem_usage 245428 # Number of bytes of host memory used
< host_seconds 0.20 # Real time elapsed on the host
---
> host_inst_rate 39950 # Simulator instruction rate (inst/s)
> host_op_rate 72345 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 89952499 # Simulator tick rate (ticks/s)
> host_mem_usage 224288 # Number of bytes of host memory used
> host_seconds 0.14 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 28864 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 19328 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 451 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 2366289556 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1584522053 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 2366289556 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 19328 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9536 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28864 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 19328 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 19328 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 302 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 149 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 451 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1584522053 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 781767503 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2366289556 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1584522053 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1584522053 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1584522053 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 781767503 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2366289556 # Total bandwidth to/from this memory (bytes/s)
323a331
> system.cpu.icache.ReadReq_miss_rate::total 0.199897 # miss rate for ReadReq accesses
324a333
> system.cpu.icache.demand_miss_rate::total 0.199897 # miss rate for demand accesses
325a335
> system.cpu.icache.overall_miss_rate::total 0.199897 # miss rate for overall accesses
326a337
> system.cpu.icache.ReadReq_avg_miss_latency::total 35555.128205 # average ReadReq miss latency
327a339
> system.cpu.icache.demand_avg_miss_latency::total 35555.128205 # average overall miss latency
328a341
> system.cpu.icache.overall_avg_miss_latency::total 35555.128205 # average overall miss latency
355a369
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155818 # mshr miss rate for ReadReq accesses
356a371
> system.cpu.icache.demand_mshr_miss_rate::total 0.155818 # mshr miss rate for demand accesses
357a373
> system.cpu.icache.overall_mshr_miss_rate::total 0.155818 # mshr miss rate for overall accesses
358a375
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35154.605263 # average ReadReq mshr miss latency
359a377
> system.cpu.icache.demand_avg_mshr_miss_latency::total 35154.605263 # average overall mshr miss latency
360a379
> system.cpu.icache.overall_avg_mshr_miss_latency::total 35154.605263 # average overall mshr miss latency
403a423
> system.cpu.dcache.ReadReq_miss_rate::total 0.070900 # miss rate for ReadReq accesses
404a425
> system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses
405a427
> system.cpu.dcache.demand_miss_rate::total 0.074726 # miss rate for demand accesses
406a429
> system.cpu.dcache.overall_miss_rate::total 0.074726 # miss rate for overall accesses
407a431
> system.cpu.dcache.ReadReq_avg_miss_latency::total 35047.826087 # average ReadReq miss latency
408a433
> system.cpu.dcache.WriteReq_avg_miss_latency::total 38388.157895 # average WriteReq miss latency
409a435
> system.cpu.dcache.demand_avg_miss_latency::total 36376.963351 # average overall miss latency
410a437
> system.cpu.dcache.overall_avg_miss_latency::total 36376.963351 # average overall miss latency
441a469
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045006 # mshr miss rate for ReadReq accesses
442a471
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses
443a473
> system.cpu.dcache.demand_mshr_miss_rate::total 0.058294 # mshr miss rate for demand accesses
444a475
> system.cpu.dcache.overall_mshr_miss_rate::total 0.058294 # mshr miss rate for overall accesses
445a477
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35260.273973 # average ReadReq mshr miss latency
446a479
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35388.157895 # average WriteReq mshr miss latency
447a481
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 35325.503356 # average overall mshr miss latency
448a483
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 35325.503356 # average overall mshr miss latency
501a537
> system.cpu.l2cache.ReadReq_miss_rate::total 0.994695 # miss rate for ReadReq accesses
502a539
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
504a542
> system.cpu.l2cache.demand_miss_rate::total 0.995585 # miss rate for demand accesses
506a545
> system.cpu.l2cache.overall_miss_rate::total 0.995585 # miss rate for overall accesses
508a548
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34278.666667 # average ReadReq miss latency
509a550
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34250 # average ReadExReq miss latency
511a553
> system.cpu.l2cache.demand_avg_miss_latency::total 34273.835920 # average overall miss latency
513a556
> system.cpu.l2cache.overall_avg_miss_latency::total 34273.835920 # average overall miss latency
545a589
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994695 # mshr miss rate for ReadReq accesses
546a591
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
548a594
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.995585 # mshr miss rate for demand accesses
550a597
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.995585 # mshr miss rate for overall accesses
552a600
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.666667 # average ReadReq mshr miss latency
553a602
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31177.631579 # average ReadExReq mshr miss latency
555a605
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency
557a608
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency