7,11c7,11
< host_inst_rate 70304 # Simulator instruction rate (inst/s)
< host_op_rate 127350 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 293494415 # Simulator tick rate (ticks/s)
< host_mem_usage 271256 # Number of bytes of host memory used
< host_seconds 0.08 # Real time elapsed on the host
---
> host_inst_rate 24766 # Simulator instruction rate (inst/s)
> host_op_rate 44863 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 103395613 # Simulator tick rate (ticks/s)
> host_mem_usage 253532 # Number of bytes of host memory used
> host_seconds 0.22 # Real time elapsed on the host
204,205c204,205
< system.physmem.totQLat 6803250 # Total ticks spent queuing
< system.physmem.totMemAccLat 14640750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 6799250 # Total ticks spent queuing
> system.physmem.totMemAccLat 14636750 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 16275.72 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 16266.15 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 35025.72 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 35016.15 # Average memory access latency per DRAM burst
250c250
< system.physmem_1.actBackEnergy 2963430 # Energy for active background per rank (pJ)
---
> system.physmem_1.actBackEnergy 2962290 # Energy for active background per rank (pJ)
252c252
< system.physmem_1.actPowerDownEnergy 7182000 # Energy for active power-down per rank (pJ)
---
> system.physmem_1.actPowerDownEnergy 7183140 # Energy for active power-down per rank (pJ)
357c357
< system.cpu.iq.issued_per_cycle::stdev 1.710819 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::stdev 1.710701 # Number of insts issued each cycle
359,361c359,361
< system.cpu.iq.issued_per_cycle::0 19691 79.28% 79.28% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1200 4.83% 84.12% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 866 3.49% 87.60% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 19689 79.28% 79.28% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1202 4.84% 84.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 867 3.49% 87.61% # Number of insts issued each cycle
363c363
< system.cpu.iq.issued_per_cycle::4 815 3.28% 93.20% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::4 814 3.28% 93.20% # Number of insts issued each cycle
496,497c496,497
< system.cpu.iew.wb_producers 11019 # num instructions producing a value
< system.cpu.iew.wb_consumers 17148 # num instructions consuming a value
---
> system.cpu.iew.wb_producers 11018 # num instructions producing a value
> system.cpu.iew.wb_consumers 17146 # num instructions consuming a value
499c499
< system.cpu.iew.wb_fanout 0.642582 # average fanout of values written-back
---
> system.cpu.iew.wb_fanout 0.642599 # average fanout of values written-back
505c505
< system.cpu.commit.committed_per_cycle::stdev 1.307645 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::stdev 1.307612 # Number of insts commited each cycle
507,509c507,509
< system.cpu.commit.committed_per_cycle::0 19538 85.72% 85.72% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1001 4.39% 90.11% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 566 2.48% 92.59% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 19537 85.71% 85.71% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1003 4.40% 90.12% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 565 2.48% 92.59% # Number of insts commited each cycle
589c589
< system.cpu.dcache.tags.tagsinuse 81.537714 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 81.537314 # Cycle average of tags in use
594c594
< system.cpu.dcache.tags.occ_blocks::cpu.data 81.537714 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 81.537314 # Average occupied blocks per requestor
620,627c620,627
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 10226000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 10226000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 7070500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 7070500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 17296500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 17296500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 17296500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 17296500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 10224000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 10224000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 7069500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 7069500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 17293500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 17293500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 17293500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 17293500 # number of overall miss cycles
644,651c644,651
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87401.709402 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 87401.709402 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93032.894737 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 93032.894737 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 89619.170984 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 89619.170984 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87384.615385 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 87384.615385 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93019.736842 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 93019.736842 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 89603.626943 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 89603.626943 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 89603.626943 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 89603.626943 # average overall miss latency
672,679c672,679
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6448000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6448000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6994500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 6994500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13442500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 13442500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13442500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 13442500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6446000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6446000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6993500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 6993500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13439500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 13439500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13439500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 13439500 # number of overall MSHR miss cycles
688,695c688,695
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99200 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99200 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92032.894737 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92032.894737 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99169.230769 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99169.230769 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92019.736842 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92019.736842 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95315.602837 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 95315.602837 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95315.602837 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 95315.602837 # average overall mshr miss latency
698c698
< system.cpu.icache.tags.tagsinuse 130.260906 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 130.259615 # Cycle average of tags in use
703,705c703,705
< system.cpu.icache.tags.occ_blocks::cpu.inst 130.260906 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.063604 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.063604 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 130.259615 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.063603 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.063603 # Average percentage of cache occupancy
725,730c725,730
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 30146000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 30146000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 30146000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 30146000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 30146000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 30146000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 30145000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 30145000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 30145000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 30145000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 30145000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 30145000 # number of overall miss cycles
743,748c743,748
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78301.298701 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 78301.298701 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 78301.298701 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 78301.298701 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78298.701299 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 78298.701299 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 78298.701299 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 78298.701299 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 78298.701299 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 78298.701299 # average overall miss latency
767,772c767,772
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23206500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23206500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23206500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23206500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23206500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23206500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23205500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23205500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23205500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23205500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23205500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23205500 # number of overall MSHR miss cycles
779,784c779,784
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83476.618705 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83476.618705 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83473.021583 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83473.021583 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83473.021583 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 83473.021583 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83473.021583 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 83473.021583 # average overall mshr miss latency
787c787
< system.cpu.l2cache.tags.tagsinuse 211.897546 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 211.895854 # Cycle average of tags in use
792,793c792,793
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.293933 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603612 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.292642 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603212 # Average occupied blocks per requestor
822,833c822,833
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6880500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 6880500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22777500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 22777500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6350000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 6350000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 22777500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 13230500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 36008000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 22777500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 13230500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 36008000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6879500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6879500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22776500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 22776500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6348000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 6348000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22776500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 13227500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 36004000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22776500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 13227500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 36004000 # number of overall miss cycles
858,869c858,869
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90532.894737 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90532.894737 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82229.241877 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82229.241877 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97692.307692 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 97692.307692 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 86143.540670 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 86143.540670 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90519.736842 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90519.736842 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82225.631769 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82225.631769 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97661.538462 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 97661.538462 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82225.631769 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93812.056738 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 86133.971292 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82225.631769 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93812.056738 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 86133.971292 # average overall miss latency
888,899c888,899
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6120500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6120500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20007500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20007500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5700000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5700000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20007500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11820500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 31828000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20007500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11820500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 31828000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6119500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6119500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20006500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20006500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5698000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5698000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20006500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11817500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 31824000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20006500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11817500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 31824000 # number of overall MSHR miss cycles
912,923c912,923
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80532.894737 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80532.894737 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72229.241877 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72229.241877 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87692.307692 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87692.307692 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80519.736842 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80519.736842 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72225.631769 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72225.631769 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87661.538462 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87661.538462 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72225.631769 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83812.056738 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76133.971292 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72225.631769 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83812.056738 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76133.971292 # average overall mshr miss latency
< host_inst_rate 70304 # Simulator instruction rate (inst/s)
< host_op_rate 127350 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 293494415 # Simulator tick rate (ticks/s)
< host_mem_usage 271256 # Number of bytes of host memory used
< host_seconds 0.08 # Real time elapsed on the host
---
> host_inst_rate 24766 # Simulator instruction rate (inst/s)
> host_op_rate 44863 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 103395613 # Simulator tick rate (ticks/s)
> host_mem_usage 253532 # Number of bytes of host memory used
> host_seconds 0.22 # Real time elapsed on the host
204,205c204,205
< system.physmem.totQLat 6803250 # Total ticks spent queuing
< system.physmem.totMemAccLat 14640750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 6799250 # Total ticks spent queuing
> system.physmem.totMemAccLat 14636750 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 16275.72 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 16266.15 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 35025.72 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 35016.15 # Average memory access latency per DRAM burst
250c250
< system.physmem_1.actBackEnergy 2963430 # Energy for active background per rank (pJ)
---
> system.physmem_1.actBackEnergy 2962290 # Energy for active background per rank (pJ)
252c252
< system.physmem_1.actPowerDownEnergy 7182000 # Energy for active power-down per rank (pJ)
---
> system.physmem_1.actPowerDownEnergy 7183140 # Energy for active power-down per rank (pJ)
357c357
< system.cpu.iq.issued_per_cycle::stdev 1.710819 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::stdev 1.710701 # Number of insts issued each cycle
359,361c359,361
< system.cpu.iq.issued_per_cycle::0 19691 79.28% 79.28% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1200 4.83% 84.12% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 866 3.49% 87.60% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 19689 79.28% 79.28% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1202 4.84% 84.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 867 3.49% 87.61% # Number of insts issued each cycle
363c363
< system.cpu.iq.issued_per_cycle::4 815 3.28% 93.20% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::4 814 3.28% 93.20% # Number of insts issued each cycle
496,497c496,497
< system.cpu.iew.wb_producers 11019 # num instructions producing a value
< system.cpu.iew.wb_consumers 17148 # num instructions consuming a value
---
> system.cpu.iew.wb_producers 11018 # num instructions producing a value
> system.cpu.iew.wb_consumers 17146 # num instructions consuming a value
499c499
< system.cpu.iew.wb_fanout 0.642582 # average fanout of values written-back
---
> system.cpu.iew.wb_fanout 0.642599 # average fanout of values written-back
505c505
< system.cpu.commit.committed_per_cycle::stdev 1.307645 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::stdev 1.307612 # Number of insts commited each cycle
507,509c507,509
< system.cpu.commit.committed_per_cycle::0 19538 85.72% 85.72% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1001 4.39% 90.11% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 566 2.48% 92.59% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 19537 85.71% 85.71% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1003 4.40% 90.12% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 565 2.48% 92.59% # Number of insts commited each cycle
589c589
< system.cpu.dcache.tags.tagsinuse 81.537714 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 81.537314 # Cycle average of tags in use
594c594
< system.cpu.dcache.tags.occ_blocks::cpu.data 81.537714 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 81.537314 # Average occupied blocks per requestor
620,627c620,627
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 10226000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 10226000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 7070500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 7070500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 17296500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 17296500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 17296500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 17296500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 10224000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 10224000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 7069500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 7069500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 17293500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 17293500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 17293500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 17293500 # number of overall miss cycles
644,651c644,651
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87401.709402 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 87401.709402 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93032.894737 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 93032.894737 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 89619.170984 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 89619.170984 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87384.615385 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 87384.615385 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93019.736842 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 93019.736842 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 89603.626943 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 89603.626943 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 89603.626943 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 89603.626943 # average overall miss latency
672,679c672,679
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6448000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6448000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6994500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 6994500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13442500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 13442500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13442500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 13442500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6446000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6446000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6993500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 6993500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13439500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 13439500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13439500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 13439500 # number of overall MSHR miss cycles
688,695c688,695
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99200 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99200 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92032.894737 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92032.894737 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99169.230769 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99169.230769 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92019.736842 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92019.736842 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95315.602837 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 95315.602837 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95315.602837 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 95315.602837 # average overall mshr miss latency
698c698
< system.cpu.icache.tags.tagsinuse 130.260906 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 130.259615 # Cycle average of tags in use
703,705c703,705
< system.cpu.icache.tags.occ_blocks::cpu.inst 130.260906 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.063604 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.063604 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 130.259615 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.063603 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.063603 # Average percentage of cache occupancy
725,730c725,730
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 30146000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 30146000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 30146000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 30146000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 30146000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 30146000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 30145000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 30145000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 30145000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 30145000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 30145000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 30145000 # number of overall miss cycles
743,748c743,748
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78301.298701 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 78301.298701 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 78301.298701 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 78301.298701 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78298.701299 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 78298.701299 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 78298.701299 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 78298.701299 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 78298.701299 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 78298.701299 # average overall miss latency
767,772c767,772
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23206500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23206500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23206500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23206500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23206500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23206500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23205500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23205500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23205500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23205500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23205500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23205500 # number of overall MSHR miss cycles
779,784c779,784
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83476.618705 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83476.618705 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83473.021583 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83473.021583 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83473.021583 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 83473.021583 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83473.021583 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 83473.021583 # average overall mshr miss latency
787c787
< system.cpu.l2cache.tags.tagsinuse 211.897546 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 211.895854 # Cycle average of tags in use
792,793c792,793
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.293933 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603612 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.292642 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603212 # Average occupied blocks per requestor
822,833c822,833
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6880500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 6880500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22777500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 22777500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6350000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 6350000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 22777500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 13230500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 36008000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 22777500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 13230500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 36008000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6879500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6879500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22776500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 22776500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6348000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 6348000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22776500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 13227500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 36004000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22776500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 13227500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 36004000 # number of overall miss cycles
858,869c858,869
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90532.894737 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90532.894737 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82229.241877 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82229.241877 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97692.307692 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 97692.307692 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 86143.540670 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 86143.540670 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90519.736842 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90519.736842 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82225.631769 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82225.631769 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97661.538462 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 97661.538462 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82225.631769 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93812.056738 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 86133.971292 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82225.631769 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93812.056738 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 86133.971292 # average overall miss latency
888,899c888,899
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6120500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6120500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20007500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20007500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5700000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5700000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20007500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11820500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 31828000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20007500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11820500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 31828000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6119500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6119500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20006500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20006500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5698000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5698000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20006500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11817500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 31824000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20006500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11817500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 31824000 # number of overall MSHR miss cycles
912,923c912,923
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80532.894737 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80532.894737 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72229.241877 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72229.241877 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87692.307692 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87692.307692 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80519.736842 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80519.736842 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72225.631769 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72225.631769 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87661.538462 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87661.538462 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72225.631769 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83812.056738 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76133.971292 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72225.631769 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83812.056738 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76133.971292 # average overall mshr miss latency