3,5c3,5
< sim_seconds 0.000021 # Number of seconds simulated
< sim_ticks 21382500 # Number of ticks simulated
< final_tick 21382500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000022 # Number of seconds simulated
> sim_ticks 22466500 # Number of ticks simulated
> final_tick 22466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 21602 # Simulator instruction rate (inst/s)
< host_op_rate 39134 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 85845466 # Simulator tick rate (ticks/s)
< host_mem_usage 271116 # Number of bytes of host memory used
< host_seconds 0.25 # Real time elapsed on the host
---
> host_inst_rate 32079 # Simulator instruction rate (inst/s)
> host_op_rate 58113 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 133941475 # Simulator tick rate (ticks/s)
> host_mem_usage 269032 # Number of bytes of host memory used
> host_seconds 0.17 # Real time elapsed on the host
16,33c16,33
< system.physmem.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory
< system.physmem.bytes_read::total 26688 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 417 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 832082310 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 416041155 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1248123465 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 832082310 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 832082310 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 832082310 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 416041155 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1248123465 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 417 # Number of read requests accepted
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
> system.physmem.bytes_read::total 26752 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 418 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 789085972 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 401664701 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1190750673 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 789085972 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 789085972 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 789085972 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 401664701 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1190750673 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 418 # Number of read requests accepted
35c35
< system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 418 # Number of DRAM read bursts, including those serviced by the write queue
37c37
< system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 26752 # Total number of bytes read from DRAM
40c40
< system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 26752 # Total read bytes from the system interface side
45c45
< system.physmem.perBankRdBursts::0 31 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 32 # Per bank write bursts
49c49
< system.physmem.perBankRdBursts::4 51 # Per bank write bursts
---
> system.physmem.perBankRdBursts::4 50 # Per bank write bursts
53c53
< system.physmem.perBankRdBursts::8 23 # Per bank write bursts
---
> system.physmem.perBankRdBursts::8 24 # Per bank write bursts
58,59c58,59
< system.physmem.perBankRdBursts::13 19 # Per bank write bursts
< system.physmem.perBankRdBursts::14 7 # Per bank write bursts
---
> system.physmem.perBankRdBursts::13 20 # Per bank write bursts
> system.physmem.perBankRdBursts::14 6 # Per bank write bursts
79c79
< system.physmem.totGap 21259500 # Total gap between requests
---
> system.physmem.totGap 22337000 # Total gap between requests
86c86
< system.physmem.readPktSize::6 417 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 418 # Read request sizes (log2)
94,98c94,98
< system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 125 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
190,207c190,207
< system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 248.742268 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 161.877699 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 262.561948 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 36 37.11% 37.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 27 27.84% 64.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 16 16.49% 81.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 4 4.12% 85.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2 2.06% 87.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 4 4.12% 91.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 2 2.06% 93.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1 1.03% 94.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation
< system.physmem.totQLat 5040250 # Total ticks spent queuing
< system.physmem.totMemAccLat 12859000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 12086.93 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 95 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 246.568421 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 159.892164 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 259.040400 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 37 38.95% 38.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 23 24.21% 63.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 16 16.84% 80.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 6 6.32% 86.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2 2.11% 88.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 3 3.16% 91.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 2 2.11% 93.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 2 2.11% 95.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 4 4.21% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 95 # Bytes accessed per row activation
> system.physmem.totQLat 6803250 # Total ticks spent queuing
> system.physmem.totMemAccLat 14640750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2090000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 16275.72 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 30836.93 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1248.12 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 35025.72 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1190.75 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 1248.12 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1190.75 # Average system read bandwidth in MiByte/s
215,216c215,216
< system.physmem.busUtil 9.75 # Data bus utilization in percentage
< system.physmem.busUtilRead 9.75 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 9.30 # Data bus utilization in percentage
> system.physmem.busUtilRead 9.30 # Data bus utilization in percentage for reads
218c218
< system.physmem.avgRdQLen 1.67 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing
220c220
< system.physmem.readRowHits 309 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 310 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 74.16 # Row buffer hit rate for reads
224,228c224,228
< system.physmem.avgGap 50982.01 # Average gap between requests
< system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 173880 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 94875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 912600 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 53437.80 # Average gap between requests
> system.physmem.pageHitRate 74.16 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 285600 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1413720 # Energy for read commands per rank (pJ)
230,235c230,239
< system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 13023390 # Total energy per rank (pJ)
< system.physmem_0.averagePower 822.573188 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 13750 # Time in different power states
---
> system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 2399130 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 30240 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 7645980 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 138240 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 13267425 # Total energy per rank (pJ)
> system.physmem_0.averagePower 590.516301 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 17035500 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states
237,242c241,247
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 415800 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 226875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1497600 # Energy for read commands per rank (pJ)
---
> system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 359250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 4794250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 16769500 # Time in different power states
> system.physmem_1.actEnergy 485520 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 235290 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1570800 # Energy for read commands per rank (pJ)
244,249c249,258
< system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 10696050 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 117000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 13970445 # Total energy per rank (pJ)
< system.physmem_1.averagePower 882.390336 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 103000 # Time in different power states
---
> system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 2963430 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 82560 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 7182000 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 13750320 # Total energy per rank (pJ)
> system.physmem_1.averagePower 612.009347 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 14672000 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 109000 # Time in different power states
251,258c260,268
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 15223250 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 3511 # Number of BP lookups
< system.cpu.branchPred.condPredicted 3511 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 567 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 2933 # Number of BTB lookups
---
> system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 3500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 6091750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 15742250 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 3488 # Number of BP lookups
> system.cpu.branchPred.condPredicted 3488 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 571 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 2960 # Number of BTB lookups
262c272
< system.cpu.branchPred.usedRAS 414 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.usedRAS 360 # Number of times the RAS was used to get a target.
264,267c274,277
< system.cpu.branchPred.indirectLookups 2933 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 496 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 2437 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 406 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.indirectLookups 2960 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 483 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 2477 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 410 # Number of mispredicted indirect branches.
269c279
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
271,272c281,282
< system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states
---
> system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
274,275c284,285
< system.cpu.pwrStateResidencyTicks::ON 21382500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 42766 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 22466500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 44934 # number of cpu cycles simulated
278,284c288,294
< system.cpu.fetch.icacheStallCycles 11494 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 15919 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 3511 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 910 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 9718 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1335 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 93 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.icacheStallCycles 12177 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 15717 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 3488 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 843 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 10477 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1321 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 78 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
287,292c297,302
< system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 2042 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 273 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 23431 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.223593 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.745730 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 2026 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 24836 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.141770 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.668775 # Number of instructions fetched each cycle (Total)
294,302c304,312
< system.cpu.fetch.rateDist::0 19161 81.78% 81.78% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 166 0.71% 82.48% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 156 0.67% 83.15% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 235 1.00% 84.15% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 218 0.93% 85.08% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 215 0.92% 86.00% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 266 1.14% 87.14% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 168 0.72% 87.85% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 2846 12.15% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 20599 82.94% 82.94% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 175 0.70% 83.64% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 165 0.66% 84.31% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 225 0.91% 85.22% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 209 0.84% 86.06% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 222 0.89% 86.95% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 269 1.08% 88.03% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 159 0.64% 88.67% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 2813 11.33% 100.00% # Number of instructions fetched each cycle (Total)
306,327c316,337
< system.cpu.fetch.rateDist::total 23431 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.082098 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.372235 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 11586 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 7313 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 3407 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 458 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 667 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 26631 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 667 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 11849 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 2059 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 1032 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 3561 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 4263 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 25112 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 80 # Number of times rename has blocked due to IQ full
< system.cpu.rename.SQFullEvents 4127 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 28145 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 61260 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 35084 # Number of integer rename lookups
---
> system.cpu.fetch.rateDist::total 24836 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.077625 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.349780 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 12221 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 8128 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 3370 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 457 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 660 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 26405 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 660 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 12481 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 1971 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 1213 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 3524 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 4987 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 24875 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 82 # Number of times rename has blocked due to IQ full
> system.cpu.rename.SQFullEvents 4849 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 27762 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 60616 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 34638 # Number of integer rename lookups
330,347c340,357
< system.cpu.rename.UndoneMaps 17082 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 24 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 1417 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 2745 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1552 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 21890 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 18162 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 138 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 12165 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 16733 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 23431 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.775127 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.748484 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 16699 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 25 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 1436 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 2622 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1598 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 21775 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 18112 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 144 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 12051 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 16553 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 24836 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.729264 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.710819 # Number of insts issued each cycle
349,357c359,367
< system.cpu.iq.issued_per_cycle::0 18255 77.91% 77.91% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1208 5.16% 83.07% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 874 3.73% 86.80% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 566 2.42% 89.21% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 836 3.57% 92.78% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 600 2.56% 95.34% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 613 2.62% 97.96% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 346 1.48% 99.43% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 133 0.57% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 19691 79.28% 79.28% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1200 4.83% 84.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 866 3.49% 87.60% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 575 2.32% 89.92% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 815 3.28% 93.20% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 575 2.32% 95.51% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 614 2.47% 97.99% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 364 1.47% 99.45% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 136 0.55% 100.00% # Number of insts issued each cycle
361c371
< system.cpu.iq.issued_per_cycle::total 23431 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 24836 # Number of insts issued each cycle
363,393c373,403
< system.cpu.iq.fu_full::IntAlu 213 76.07% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 51 18.21% 94.29% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 16 5.71% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 223 79.93% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.93% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 41 14.70% 94.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 15 5.38% 100.00% # attempts to use FU when none available
397,427c407,437
< system.cpu.iq.FU_type_0::IntAlu 14483 79.74% 79.75% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.79% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.83% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 2327 12.81% 92.64% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1337 7.36% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 14478 79.94% 79.95% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.98% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.02% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 2258 12.47% 92.49% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1361 7.51% 100.00% # Type of FU issued
430,436c440,446
< system.cpu.iq.FU_type_0::total 18162 # Type of FU issued
< system.cpu.iq.rate 0.424683 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 280 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.015417 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 60165 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 34082 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 16453 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 18112 # Type of FU issued
> system.cpu.iq.rate 0.403080 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 279 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.015404 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 61475 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 33854 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 16418 # Number of integer instruction queue wakeup accesses
440c450
< system.cpu.iq.int_alu_accesses 18436 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 18385 # Number of integer alu accesses
442c452
< system.cpu.iew.lsq.thread0.forwLoads 200 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 215 # Number of loads that had data forwarded from stores
444,445c454,455
< system.cpu.iew.lsq.thread0.squashedLoads 1692 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1569 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed
447c457
< system.cpu.iew.lsq.thread0.squashedStores 617 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 663 # Number of stores squashed
451c461
< system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked
453,460c463,470
< system.cpu.iew.iewSquashCycles 667 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 1486 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 141 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 21912 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 9 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 2745 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 1552 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions
---
> system.cpu.iew.iewSquashCycles 660 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 1482 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 153 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 21798 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 2622 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 1598 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
462c472
< system.cpu.iew.iewLSQFullEvents 140 # Number of times the LSQ has become full, causing a stall
---
> system.cpu.iew.iewLSQFullEvents 152 # Number of times the LSQ has become full, causing a stall
464,469c474,479
< system.cpu.iew.predictedTakenIncorrect 120 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 685 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 805 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 17078 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 2088 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1084 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 680 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 798 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 17038 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 2047 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1074 # Number of squashed instructions skipped in execute
472,482c482,492
< system.cpu.iew.exec_refs 3333 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1727 # Number of branches executed
< system.cpu.iew.exec_stores 1245 # Number of stores executed
< system.cpu.iew.exec_rate 0.399336 # Inst execution rate
< system.cpu.iew.wb_sent 16776 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 16457 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 11050 # num instructions producing a value
< system.cpu.iew.wb_consumers 17247 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.384815 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.640691 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 12164 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_refs 3306 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1731 # Number of branches executed
> system.cpu.iew.exec_stores 1259 # Number of stores executed
> system.cpu.iew.exec_rate 0.379178 # Inst execution rate
> system.cpu.iew.wb_sent 16737 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 16422 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 11019 # num instructions producing a value
> system.cpu.iew.wb_consumers 17148 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.365469 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.642582 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 12050 # The number of squashed insts skipped by commit
484,487c494,497
< system.cpu.commit.branchMispredicts 655 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 21365 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.456213 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.347578 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 648 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 22793 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.427631 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.307645 # Number of insts commited each cycle
489,497c499,507
< system.cpu.commit.committed_per_cycle::0 18118 84.80% 84.80% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 989 4.63% 89.43% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 572 2.68% 92.11% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 729 3.41% 95.52% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 380 1.78% 97.30% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 132 0.62% 97.92% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 120 0.56% 98.48% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 73 0.34% 98.82% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 252 1.18% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 19538 85.72% 85.72% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1001 4.39% 90.11% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 566 2.48% 92.59% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 727 3.19% 95.78% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 384 1.68% 97.47% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 133 0.58% 98.05% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 124 0.54% 98.60% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 72 0.32% 98.91% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 248 1.09% 100.00% # Number of insts commited each cycle
501c511
< system.cpu.commit.committed_per_cycle::total 21365 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 22793 # Number of insts commited each cycle
547,551c557,561
< system.cpu.commit.bw_lim_events 252 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 43024 # The number of ROB reads
< system.cpu.rob.rob_writes 45919 # The number of ROB writes
< system.cpu.timesIdled 159 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 19335 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 248 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 44342 # The number of ROB reads
> system.cpu.rob.rob_writes 45672 # The number of ROB writes
> system.cpu.timesIdled 156 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 20098 # Total number of cycles that the CPU has spent unscheduled due to idling
554,559c564,569
< system.cpu.cpi 7.949071 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 7.949071 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.125801 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.125801 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 21733 # number of integer regfile reads
< system.cpu.int_regfile_writes 13291 # number of integer regfile writes
---
> system.cpu.cpi 8.352045 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 8.352045 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.119731 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.119731 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 21663 # number of integer regfile reads
> system.cpu.int_regfile_writes 13219 # number of integer regfile writes
561,563c571,573
< system.cpu.cc_regfile_reads 8307 # number of cc regfile reads
< system.cpu.cc_regfile_writes 5092 # number of cc regfile writes
< system.cpu.misc_regfile_reads 7667 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 8286 # number of cc regfile reads
> system.cpu.cc_regfile_writes 5066 # number of cc regfile writes
> system.cpu.misc_regfile_reads 7640 # number of misc regfile reads
565c575
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
567,570c577,580
< system.cpu.dcache.tags.tagsinuse 81.328051 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2579 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 18.553957 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 81.537714 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2520 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 17.872340 # Average number of references to valid blocks.
572,575c582,585
< system.cpu.dcache.tags.occ_blocks::cpu.data 81.328051 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.019855 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.019855 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 81.537714 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.019907 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.019907 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
577,607c587,617
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 5679 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5679 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 1719 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1719 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 860 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 860 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 2579 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2579 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2579 # number of overall hits
< system.cpu.dcache.overall_hits::total 2579 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 116 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 116 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 75 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 75 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 191 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 191 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 191 # number of overall misses
< system.cpu.dcache.overall_misses::total 191 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9465500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9465500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 6317000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 6317000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 15782500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 15782500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 15782500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 15782500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1835 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1835 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 5567 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 5567 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 1661 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1661 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 2520 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2520 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2520 # number of overall hits
> system.cpu.dcache.overall_hits::total 2520 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses
> system.cpu.dcache.overall_misses::total 193 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 10226000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 10226000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 7070500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 7070500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 17296500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 17296500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 17296500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 17296500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1778 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1778 # number of ReadReq accesses(hits+misses)
610,630c620,640
< system.cpu.dcache.demand_accesses::cpu.data 2770 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2770 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2770 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2770 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063215 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.063215 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080214 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.080214 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.068953 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.068953 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.068953 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.068953 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81599.137931 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 81599.137931 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84226.666667 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 84226.666667 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 82630.890052 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 82630.890052 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 82630.890052 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 82630.890052 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked
---
> system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065804 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.065804 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.071139 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.071139 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.071139 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.071139 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87401.709402 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 87401.709402 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93032.894737 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 93032.894737 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 89619.170984 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 89619.170984 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked
634c644
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 41.333333 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked
642,674c652,684
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 75 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 75 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 139 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 139 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5739000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5739000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6242000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 6242000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11981000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11981000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034877 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.080214 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.080214 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050181 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.050181 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050181 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.050181 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89671.875000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89671.875000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83226.666667 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83226.666667 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86194.244604 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 86194.244604 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86194.244604 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 86194.244604 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6448000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6448000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6994500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 6994500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13442500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 13442500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13442500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 13442500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036558 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036558 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.051972 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.051972 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99200 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99200 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92032.894737 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92032.894737 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
676,679c686,689
< system.cpu.icache.tags.tagsinuse 130.610950 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1656 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 5.935484 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 130.260906 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1641 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 5.902878 # Average number of references to valid blocks.
681,727c691,737
< system.cpu.icache.tags.occ_blocks::cpu.inst 130.610950 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.063775 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.063775 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 4363 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4363 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 1656 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1656 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1656 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1656 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1656 # number of overall hits
< system.cpu.icache.overall_hits::total 1656 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 386 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 386 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 386 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 386 # number of overall misses
< system.cpu.icache.overall_misses::total 386 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 29282500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 29282500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 29282500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 29282500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 29282500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 29282500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2042 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2042 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2042 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2042 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2042 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2042 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.189030 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.189030 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.189030 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.189030 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.189030 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.189030 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75861.398964 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 75861.398964 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 75861.398964 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 75861.398964 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 75861.398964 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 75861.398964 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 121 # number of cycles access was blocked
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 130.260906 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.063604 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.063604 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 4330 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4330 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 1641 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1641 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1641 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1641 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1641 # number of overall hits
> system.cpu.icache.overall_hits::total 1641 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses
> system.cpu.icache.overall_misses::total 385 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 30146000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 30146000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 30146000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 30146000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 30146000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 30146000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2026 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2026 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2026 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190030 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.190030 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.190030 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.190030 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.190030 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.190030 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78301.298701 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 78301.298701 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 78301.298701 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 78301.298701 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 171 # number of cycles access was blocked
731c741
< system.cpu.icache.avg_blocked_cycles::no_mshrs 40.333333 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked
739,763c749,773
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22839500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22839500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22839500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22839500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22839500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22839500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136631 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136631 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136631 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.136631 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136631 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.136631 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81862.007168 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81862.007168 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81862.007168 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 81862.007168 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81862.007168 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 81862.007168 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23206500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23206500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23206500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23206500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23206500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23206500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137216 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.137216 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.137216 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83476.618705 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83476.618705 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
765c775
< system.cpu.l2cache.tags.tagsinuse 212.046379 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 211.897546 # Cycle average of tags in use
767,768c777,778
< system.cpu.l2cache.tags.sampled_refs 417 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.002398 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 418 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.002392 # Average number of references to valid blocks.
770,781c780,791
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.650071 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 81.396308 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003987 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.002484 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.006471 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012726 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 3761 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 3761 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.293933 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603612 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003976 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002490 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.006467 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012756 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 3770 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 3770 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
788,823c798,833
< system.cpu.l2cache.ReadExReq_misses::cpu.data 75 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 75 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 64 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 64 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 139 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 139 # number of overall misses
< system.cpu.l2cache.overall_misses::total 417 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6129000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 6129000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22409000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 22409000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5642000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 5642000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 22409000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11771000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 34180000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 22409000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11771000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 34180000 # number of overall miss cycles
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 75 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 75 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 279 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 64 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 139 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 139 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 277 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 277 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 277 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 418 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses
> system.cpu.l2cache.overall_misses::total 418 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6880500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6880500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22777500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 22777500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6350000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 6350000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22777500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 13230500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 36008000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22777500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 13230500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 36008000 # number of overall miss cycles
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 278 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 278 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 278 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 419 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 278 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 419 # number of overall (read+write) accesses
826,827c836,837
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996416 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996403 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996403 # miss rate for ReadCleanReq accesses
830c840
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996403 # miss rate for demand accesses
832,833c842,843
< system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.997613 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996403 # miss rate for overall accesses
835,847c845,857
< system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81720 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81720 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80607.913669 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80607.913669 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88156.250000 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88156.250000 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80607.913669 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84683.453237 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 81966.426859 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80607.913669 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84683.453237 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 81966.426859 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.997613 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90532.894737 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90532.894737 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82229.241877 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82229.241877 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97692.307692 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 97692.307692 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 86143.540670 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 86143.540670 # average overall miss latency
854,877c864,887
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 75 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 75 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5379000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5379000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19629000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19629000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5002000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5002000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19629000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10381000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 30010000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19629000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10381000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 30010000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 418 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 418 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6120500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6120500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20007500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20007500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5700000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5700000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20007500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11820500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 31828000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20007500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11820500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 31828000 # number of overall MSHR miss cycles
880,881c890,891
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996416 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996403 # mshr miss rate for ReadCleanReq accesses
884c894
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses
886,887c896,897
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.997613 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses
889,902c899,912
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71720 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71720 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70607.913669 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70607.913669 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78156.250000 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78156.250000 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70607.913669 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74683.453237 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71966.426859 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70607.913669 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74683.453237 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71966.426859 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.997613 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80532.894737 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80532.894737 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72229.241877 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72229.241877 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87692.307692 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87692.307692 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 419 # Total number of requests made to the snoop filter.
908c918
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
910,919c920,929
< system.cpu.toL2Bus.trans_dist::ReadExReq 75 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 75 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8896 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 76 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 76 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 838 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 26816 # Cumulative packet size per connected master and slave (bytes)
922,924c932,934
< system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.002392 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.048912 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 419 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.002387 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.048853 # Request fanout histogram
926c936
< system.cpu.toL2Bus.snoop_fanout::0 417 99.76% 99.76% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 418 99.76% 99.76% # Request fanout histogram
932,939c942,949
< system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
< system.membus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter.
---
> system.cpu.toL2Bus.snoop_fanout::total 419 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
> system.membus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter.
945c955
< system.membus.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
947,948c957,958
< system.membus.trans_dist::ReadExReq 75 # Transaction distribution
< system.membus.trans_dist::ReadExResp 75 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 76 # Transaction distribution
> system.membus.trans_dist::ReadExResp 76 # Transaction distribution
950,955c960,965
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 834 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 834 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 834 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26688 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26688 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 836 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26752 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26752 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
958c968
< system.membus.snoop_fanout::samples 417 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 418 # Request fanout histogram
962c972
< system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 418 100.00% 100.00% # Request fanout histogram
967,971c977,981
< system.membus.snoop_fanout::total 417 # Request fanout histogram
< system.membus.reqLayer0.occupancy 503500 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
< system.membus.respLayer1.occupancy 2228500 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 10.4 # Layer utilization (%)
---
> system.membus.snoop_fanout::total 418 # Request fanout histogram
> system.membus.reqLayer0.occupancy 506000 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2231250 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 9.9 # Layer utilization (%)