4,5c4,5
< sim_ticks 20818000 # Number of ticks simulated
< final_tick 20818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 21273500 # Number of ticks simulated
> final_tick 21273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
16c16
< system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory
18,21c18,21
< system.physmem.bytes_read::total 26560 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory
23,32c23,32
< system.physmem.num_reads::total 415 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 848496493 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 427322509 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1275819003 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 848496493 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 848496493 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 848496493 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 427322509 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1275819003 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 415 # Number of read requests accepted
---
> system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 833337251 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 418172844 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1251510095 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 833337251 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 833337251 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 833337251 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 418172844 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1251510095 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 416 # Number of read requests accepted
34c34
< system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 416 # Number of DRAM read bursts, including those serviced by the write queue
36c36
< system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 26624 # Total number of bytes read from DRAM
39c39
< system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 26624 # Total read bytes from the system interface side
44c44
< system.physmem.perBankRdBursts::0 32 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 31 # Per bank write bursts
46c46
< system.physmem.perBankRdBursts::2 6 # Per bank write bursts
---
> system.physmem.perBankRdBursts::2 5 # Per bank write bursts
48,49c48,49
< system.physmem.perBankRdBursts::4 50 # Per bank write bursts
< system.physmem.perBankRdBursts::5 46 # Per bank write bursts
---
> system.physmem.perBankRdBursts::4 51 # Per bank write bursts
> system.physmem.perBankRdBursts::5 44 # Per bank write bursts
51,54c51,54
< system.physmem.perBankRdBursts::7 33 # Per bank write bursts
< system.physmem.perBankRdBursts::8 25 # Per bank write bursts
< system.physmem.perBankRdBursts::9 72 # Per bank write bursts
< system.physmem.perBankRdBursts::10 63 # Per bank write bursts
---
> system.physmem.perBankRdBursts::7 37 # Per bank write bursts
> system.physmem.perBankRdBursts::8 23 # Per bank write bursts
> system.physmem.perBankRdBursts::9 71 # Per bank write bursts
> system.physmem.perBankRdBursts::10 64 # Per bank write bursts
57c57
< system.physmem.perBankRdBursts::13 17 # Per bank write bursts
---
> system.physmem.perBankRdBursts::13 19 # Per bank write bursts
78c78
< system.physmem.totGap 20722000 # Total gap between requests
---
> system.physmem.totGap 21151500 # Total gap between requests
85c85
< system.physmem.readPktSize::6 415 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 416 # Read request sizes (log2)
95,97c95,97
< system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::2 39 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
189,206c189,206
< system.physmem.bytesPerActivate::samples 96 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 252 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 164.484740 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 262.126687 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 35 36.46% 36.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 26 27.08% 63.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 15 15.62% 79.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 6 6.25% 85.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3 3.12% 88.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 3 3.12% 91.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 2 2.08% 93.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1 1.04% 94.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 5 5.21% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 96 # Bytes accessed per row activation
< system.physmem.totQLat 4745000 # Total ticks spent queuing
< system.physmem.totMemAccLat 12526250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 11433.73 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 250.721649 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 162.086023 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 265.276929 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 37 38.14% 38.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 25 25.77% 63.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 18 18.56% 82.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3 3.09% 85.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2 2.06% 87.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2 2.06% 89.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 4 4.12% 93.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1 1.03% 94.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation
> system.physmem.totQLat 4187000 # Total ticks spent queuing
> system.physmem.totMemAccLat 11987000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2080000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 10064.90 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 30183.73 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1275.82 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28814.90 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1251.51 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 1275.82 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1251.51 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.physmem.busUtil 9.97 # Data bus utilization in percentage
< system.physmem.busUtilRead 9.97 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 9.78 # Data bus utilization in percentage
> system.physmem.busUtilRead 9.78 # Data bus utilization in percentage for reads
217c217
< system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.63 # Average read queue length when enqueuing
221c221
< system.physmem.readRowHitRate 74.46 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 74.28 # Row buffer hit rate for reads
223,227c223,227
< system.physmem.avgGap 49932.53 # Average gap between requests
< system.physmem.pageHitRate 74.46 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 959400 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 50844.95 # Average gap between requests
> system.physmem.pageHitRate 74.28 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 920400 # Energy for read commands per rank (pJ)
232,233c232,233
< system.physmem_0.totalEnergy 13105245 # Total energy per rank (pJ)
< system.physmem_0.averagePower 827.743250 # Core power per rank (mW)
---
> system.physmem_0.totalEnergy 13042875 # Total energy per rank (pJ)
> system.physmem_0.averagePower 823.803884 # Core power per rank (mW)
239,241c239,241
< system.physmem_1.actEnergy 423360 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 231000 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1536600 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 415800 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 226875 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ)
246,248c246,248
< system.physmem_1.totalEnergy 14021235 # Total energy per rank (pJ)
< system.physmem_1.averagePower 885.598295 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 271750 # Time in different power states
---
> system.physmem_1.totalEnergy 13993950 # Total energy per rank (pJ)
> system.physmem_1.averagePower 883.874941 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 262750 # Time in different power states
253,257c253,257
< system.cpu.branchPred.lookups 3234 # Number of BP lookups
< system.cpu.branchPred.condPredicted 3234 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 514 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 2557 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 881 # Number of BTB hits
---
> system.cpu.branchPred.lookups 3510 # Number of BP lookups
> system.cpu.branchPred.condPredicted 3510 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 564 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 2934 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 0 # Number of BTB hits
259,261c259,265
< system.cpu.branchPred.BTBHitPct 34.454439 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 280 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 86 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 413 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 93 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 2934 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 493 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 2441 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 404 # Number of mispredicted indirect branches.
265c269
< system.cpu.numCycles 41637 # number of cpu cycles simulated
---
> system.cpu.numCycles 42548 # number of cpu cycles simulated
268,281c272,286
< system.cpu.fetch.icacheStallCycles 11661 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 14637 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 3234 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 1161 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 9674 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1159 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.CacheLines 2075 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 22725 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.149527 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.648759 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 11447 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 15916 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 3510 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 906 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 9652 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1329 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 93 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 1405 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 2036 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 273 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 23302 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.230495 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.752458 # Number of instructions fetched each cycle (Total)
283,291c288,296
< system.cpu.fetch.rateDist::0 18699 82.28% 82.28% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 221 0.97% 83.26% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 146 0.64% 83.90% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 231 1.02% 84.92% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 214 0.94% 85.86% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 258 1.14% 86.99% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 336 1.48% 88.47% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 205 0.90% 89.37% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 2415 10.63% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 19034 81.68% 81.68% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 165 0.71% 82.39% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 157 0.67% 83.07% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 234 1.00% 84.07% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 217 0.93% 85.00% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 212 0.91% 85.91% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 264 1.13% 87.04% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 172 0.74% 87.78% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 2847 12.22% 100.00% # Number of instructions fetched each cycle (Total)
295,316c300,321
< system.cpu.fetch.rateDist::total 22725 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.077671 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.351538 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 11462 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 7072 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 3206 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 406 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 579 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 24310 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 579 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 11710 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 1815 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 1004 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 3327 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 4290 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 23005 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 71 # Number of times rename has blocked due to IQ full
< system.cpu.rename.SQFullEvents 4163 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 26169 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 57126 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 32219 # Number of integer rename lookups
---
> system.cpu.fetch.rateDist::total 23302 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.082495 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.374072 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 11533 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 7244 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 3404 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 457 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 664 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 26617 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 664 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 11798 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 1942 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 1135 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 3557 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 4206 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 25098 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 80 # Number of times rename has blocked due to IQ full
> system.cpu.rename.SQFullEvents 4073 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 28145 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 61205 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 35038 # Number of integer rename lookups
319,336c324,341
< system.cpu.rename.UndoneMaps 15106 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 1472 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 2371 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1574 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 20 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 20445 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 17161 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 65 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 10724 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 15317 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 22725 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.755160 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.702113 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 17082 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 25 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 1412 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 2736 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1550 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 21864 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 18142 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 143 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 12140 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 16726 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 23302 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.778560 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.752623 # Number of insts issued each cycle
338,346c343,351
< system.cpu.iq.issued_per_cycle::0 17737 78.05% 78.05% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1126 4.95% 83.01% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 880 3.87% 86.88% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 631 2.78% 89.65% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 810 3.56% 93.22% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 590 2.60% 95.82% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 568 2.50% 98.31% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 280 1.23% 99.55% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 103 0.45% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 18136 77.83% 77.83% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1211 5.20% 83.03% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 861 3.69% 86.72% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 568 2.44% 89.16% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 833 3.57% 92.73% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 596 2.56% 95.29% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 620 2.66% 97.95% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 343 1.47% 99.42% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 134 0.58% 100.00% # Number of insts issued each cycle
350c355
< system.cpu.iq.issued_per_cycle::total 22725 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 23302 # Number of insts issued each cycle
352,382c357,387
< system.cpu.iq.fu_full::IntAlu 151 71.23% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 43 20.28% 91.51% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 18 8.49% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 211 76.17% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 50 18.05% 94.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 16 5.78% 100.00% # attempts to use FU when none available
385,416c390,421
< system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 13707 79.87% 79.89% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 4 0.02% 79.91% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.95% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 2071 12.07% 92.02% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1369 7.98% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 14465 79.73% 79.74% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.78% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.81% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 2325 12.82% 92.63% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1337 7.37% 100.00% # Type of FU issued
419,425c424,430
< system.cpu.iq.FU_type_0::total 17161 # Type of FU issued
< system.cpu.iq.rate 0.412157 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 212 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.012354 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 57316 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 31202 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 15767 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 18142 # Type of FU issued
> system.cpu.iq.rate 0.426389 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 277 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.015268 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 59998 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 34032 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 16436 # Number of integer instruction queue wakeup accesses
429c434
< system.cpu.iq.int_alu_accesses 17366 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 18413 # Number of integer alu accesses
431c436
< system.cpu.iew.lsq.thread0.forwLoads 220 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 190 # Number of loads that had data forwarded from stores
433c438
< system.cpu.iew.lsq.thread0.squashedLoads 1318 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1683 # Number of loads squashed
435,436c440,441
< system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 639 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 615 # Number of stores squashed
440c445
< system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked
442,458c447,463
< system.cpu.iew.iewSquashCycles 579 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 1449 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 20471 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 2371 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 1574 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 34 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 15 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 136 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 524 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 660 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 16265 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 1913 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 896 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 664 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 1478 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 139 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 21887 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 9 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 2736 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 1550 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 138 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 682 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 801 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 17060 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 2081 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1082 # Number of squashed instructions skipped in execute
461,471c466,476
< system.cpu.iew.exec_refs 3175 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1626 # Number of branches executed
< system.cpu.iew.exec_stores 1262 # Number of stores executed
< system.cpu.iew.exec_rate 0.390638 # Inst execution rate
< system.cpu.iew.wb_sent 16001 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 15771 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 10637 # num instructions producing a value
< system.cpu.iew.wb_consumers 16589 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.378774 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.641208 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 10723 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_refs 3326 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1722 # Number of branches executed
> system.cpu.iew.exec_stores 1245 # Number of stores executed
> system.cpu.iew.exec_rate 0.400959 # Inst execution rate
> system.cpu.iew.wb_sent 16760 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 16440 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 11045 # num instructions producing a value
> system.cpu.iew.wb_consumers 17238 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.386387 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.640736 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 12139 # The number of squashed insts skipped by commit
473,476c478,481
< system.cpu.commit.branchMispredicts 565 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 20943 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.465406 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.357230 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 652 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 21245 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.458790 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.350767 # Number of insts commited each cycle
478,486c483,491
< system.cpu.commit.committed_per_cycle::0 17686 84.45% 84.45% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 994 4.75% 89.19% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 561 2.68% 91.87% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 764 3.65% 95.52% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 370 1.77% 97.29% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 129 0.62% 97.90% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 114 0.54% 98.45% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 70 0.33% 98.78% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 255 1.22% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 17995 84.70% 84.70% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 991 4.66% 89.37% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 576 2.71% 92.08% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 726 3.42% 95.50% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 383 1.80% 97.30% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 128 0.60% 97.90% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 121 0.57% 98.47% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 72 0.34% 98.81% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 253 1.19% 100.00% # Number of insts commited each cycle
490c495
< system.cpu.commit.committed_per_cycle::total 20943 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 21245 # Number of insts commited each cycle
536,540c541,545
< system.cpu.commit.bw_lim_events 255 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 41158 # The number of ROB reads
< system.cpu.rob.rob_writes 42744 # The number of ROB writes
< system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 18912 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 253 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 42878 # The number of ROB reads
> system.cpu.rob.rob_writes 45859 # The number of ROB writes
> system.cpu.timesIdled 160 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 19246 # Total number of cycles that the CPU has spent unscheduled due to idling
543,548c548,553
< system.cpu.cpi 7.739219 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 7.739219 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.129212 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.129212 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 20872 # number of integer regfile reads
< system.cpu.int_regfile_writes 12651 # number of integer regfile writes
---
> system.cpu.cpi 7.908550 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 7.908550 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.126445 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.126445 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 21687 # number of integer regfile reads
> system.cpu.int_regfile_writes 13280 # number of integer regfile writes
550,552c555,557
< system.cpu.cc_regfile_reads 8081 # number of cc regfile reads
< system.cpu.cc_regfile_writes 4880 # number of cc regfile writes
< system.cpu.misc_regfile_reads 7277 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 8296 # number of cc regfile reads
> system.cpu.cc_regfile_writes 5092 # number of cc regfile writes
> system.cpu.misc_regfile_reads 7660 # number of misc regfile reads
555,556c560,561
< system.cpu.dcache.tags.tagsinuse 81.973847 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2383 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 81.534494 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2583 # Total number of references to valid blocks.
558c563
< system.cpu.dcache.tags.avg_refs 17.143885 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 18.582734 # Average number of references to valid blocks.
560,562c565,567
< system.cpu.dcache.tags.occ_blocks::cpu.data 81.973847 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.020013 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.020013 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 81.534494 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.019906 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.019906 # Average percentage of cache occupancy
564,565c569,570
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
567,594c572,599
< system.cpu.dcache.tags.tag_accesses 5305 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5305 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1525 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1525 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 2383 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2383 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2383 # number of overall hits
< system.cpu.dcache.overall_hits::total 2383 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 123 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 123 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 200 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 200 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 200 # number of overall misses
< system.cpu.dcache.overall_misses::total 200 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9653500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9653500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 6433000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 6433000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 16086500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 16086500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 16086500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 16086500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1648 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1648 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.tags.tag_accesses 5685 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 5685 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 860 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 860 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 2583 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2583 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2583 # number of overall hits
> system.cpu.dcache.overall_hits::total 2583 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 75 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 75 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 190 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 190 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 190 # number of overall misses
> system.cpu.dcache.overall_misses::total 190 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 9038500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 9038500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 6225500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 6225500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 15264000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 15264000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 15264000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 15264000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1838 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1838 # number of ReadReq accesses(hits+misses)
597,617c602,622
< system.cpu.dcache.demand_accesses::cpu.data 2583 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2583 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2583 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2583 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074636 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.074636 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.077429 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.077429 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.077429 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.077429 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78483.739837 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 78483.739837 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83545.454545 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 83545.454545 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 80432.500000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 80432.500000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 80432.500000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 80432.500000 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked
---
> system.cpu.dcache.demand_accesses::cpu.data 2773 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2773 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2773 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2773 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062568 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.062568 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080214 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.080214 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.068518 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.068518 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.068518 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.068518 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78595.652174 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 78595.652174 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83006.666667 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 83006.666667 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 80336.842105 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 80336.842105 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 80336.842105 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 80336.842105 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 122 # number of cycles access was blocked
619c624
< system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
621c626
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.250000 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.666667 # average number of cycles each access was blocked
625,634c630,639
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 61 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 62 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 51 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 51 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 51 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 75 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 75 # number of WriteReq MSHR misses
639,662c644,667
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5286500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5286500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6356000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 6356000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11642500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11642500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11642500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11642500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.037621 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.037621 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.053813 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.053813 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.053813 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.053813 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85266.129032 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85266.129032 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82545.454545 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82545.454545 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83758.992806 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 83758.992806 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83758.992806 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 83758.992806 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5459500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5459500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6150500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 6150500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11610000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11610000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11610000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11610000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034820 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034820 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.080214 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.080214 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050126 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.050126 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050126 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.050126 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85304.687500 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85304.687500 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82006.666667 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82006.666667 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency
665,668c670,673
< system.cpu.icache.tags.tagsinuse 130.304167 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1706 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 277 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 6.158845 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 130.801873 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1651 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 5.938849 # Average number of references to valid blocks.
670,715c675,720
< system.cpu.icache.tags.occ_blocks::cpu.inst 130.304167 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.063625 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.063625 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 277 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.135254 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 4427 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4427 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 1706 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1706 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1706 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1706 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1706 # number of overall hits
< system.cpu.icache.overall_hits::total 1706 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses
< system.cpu.icache.overall_misses::total 369 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 28132500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 28132500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 28132500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 28132500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 28132500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 28132500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2075 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2075 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2075 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2075 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2075 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2075 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.177831 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.177831 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.177831 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.177831 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.177831 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.177831 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76239.837398 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 76239.837398 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 76239.837398 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 76239.837398 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 76239.837398 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 76239.837398 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 130.801873 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.063868 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.063868 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 4350 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4350 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 1651 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1651 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1651 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1651 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1651 # number of overall hits
> system.cpu.icache.overall_hits::total 1651 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses
> system.cpu.icache.overall_misses::total 385 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 28516500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 28516500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 28516500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 28516500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 28516500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 28516500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2036 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2036 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2036 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2036 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2036 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2036 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.189096 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.189096 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.189096 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.189096 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.189096 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.189096 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74068.831169 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 74068.831169 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 74068.831169 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 74068.831169 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 74068.831169 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 74068.831169 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 142 # number of cycles access was blocked
717c722
< system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
719c724
< system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 47.333333 # average number of cycles each access was blocked
723,752c728,757
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 277 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 277 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 277 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22319000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22319000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22319000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22319000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22319000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22319000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133494 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.133494 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.133494 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80574.007220 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80574.007220 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80574.007220 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 80574.007220 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80574.007220 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 80574.007220 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 107 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 107 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 107 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21868500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 21868500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21868500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 21868500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21868500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 21868500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136542 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.136542 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.136542 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78663.669065 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78663.669065 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency
755c760
< system.cpu.l2cache.tags.tagsinuse 162.380689 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 163.058861 # Cycle average of tags in use
757,758c762,763
< system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 341 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.002933 # Average number of references to valid blocks.
760,765c765,770
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.343988 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 32.036700 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003978 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.000978 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.004955 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.841735 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 32.217126 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003993 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.000983 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.004976 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id
767,770c772,775
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010315 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 3743 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 3743 # Number of data accesses
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010406 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 3752 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 3752 # Number of data accesses
777,783c782,788
< system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 276 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 276 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 62 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 62 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 75 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 75 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 277 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 277 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 64 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 64 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 277 # number of demand (read+write) misses
785,786c790,791
< system.cpu.l2cache.demand_misses::total 415 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses
788,807c793,812
< system.cpu.l2cache.overall_misses::total 415 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6240500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 6240500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21891500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 21891500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5193000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 5193000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 21891500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11433500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 33325000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 21891500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11433500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 33325000 # number of overall miss cycles
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 277 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 277 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 62 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 62 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 277 # number of demand (read+write) accesses
---
> system.cpu.l2cache.overall_misses::total 416 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6037500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6037500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21439500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 21439500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5362500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 5362500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 21439500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11400000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 32839500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 21439500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11400000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 32839500 # number of overall miss cycles
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 75 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 75 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 278 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 278 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 64 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 278 # number of demand (read+write) accesses
809,810c814,815
< system.cpu.l2cache.demand_accesses::total 416 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 277 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 417 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 278 # number of overall (read+write) accesses
812c817
< system.cpu.l2cache.overall_accesses::total 416 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 417 # number of overall (read+write) accesses
815,816c820,821
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996390 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996390 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996403 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996403 # miss rate for ReadCleanReq accesses
819c824
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996390 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996403 # miss rate for demand accesses
821,822c826,827
< system.cpu.l2cache.demand_miss_rate::total 0.997596 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996390 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.997602 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996403 # miss rate for overall accesses
824,836c829,841
< system.cpu.l2cache.overall_miss_rate::total 0.997596 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81045.454545 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81045.454545 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79317.028986 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79317.028986 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83758.064516 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83758.064516 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79317.028986 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82255.395683 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 80301.204819 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79317.028986 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82255.395683 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 80301.204819 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.997602 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77398.916968 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77398.916968 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83789.062500 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83789.062500 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77398.916968 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82014.388489 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 78941.105769 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77398.916968 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82014.388489 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 78941.105769 # average overall miss latency
845,851c850,856
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 276 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 276 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 62 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 62 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 75 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 75 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses
853,854c858,859
< system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses
856,868c861,873
< system.cpu.l2cache.overall_mshr_misses::total 415 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5470500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5470500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19131500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19131500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4573000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4573000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19131500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10043500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 29175000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19131500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10043500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 29175000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5287500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5287500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18669500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18669500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4722500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4722500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18669500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10010000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 28679500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18669500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10010000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 28679500 # number of overall MSHR miss cycles
871,872c876,877
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996390 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996403 # mshr miss rate for ReadCleanReq accesses
875c880
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses
877,878c882,883
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.997596 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.997602 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses
880,892c885,897
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.997596 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71045.454545 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71045.454545 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69317.028986 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69317.028986 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73758.064516 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73758.064516 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69317.028986 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69317.028986 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.997602 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67398.916968 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67398.916968 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73789.062500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73789.062500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency
894c899
< system.cpu.toL2Bus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter.
---
> system.cpu.toL2Bus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter.
900,905c905,910
< system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 277 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 62 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 554 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadResp 342 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 75 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 75 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes)
907,908c912,913
< system.cpu.toL2Bus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17728 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 834 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes)
910c915
< system.cpu.toL2Bus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes)
912,914c917,919
< system.cpu.toL2Bus.snoop_fanout::samples 416 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.002404 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.049029 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 417 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.002398 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.048970 # Request fanout histogram
916c921
< system.cpu.toL2Bus.snoop_fanout::0 415 99.76% 99.76% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 416 99.76% 99.76% # Request fanout histogram
922,923c927,928
< system.cpu.toL2Bus.snoop_fanout::total 416 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 417 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks)
925c930
< system.cpu.toL2Bus.respLayer0.occupancy 415500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks)
929,938c934,943
< system.membus.trans_dist::ReadResp 338 # Transaction distribution
< system.membus.trans_dist::ReadExReq 77 # Transaction distribution
< system.membus.trans_dist::ReadExResp 77 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 338 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 830 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 830 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 830 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26560 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26560 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 26560 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadResp 341 # Transaction distribution
> system.membus.trans_dist::ReadExReq 75 # Transaction distribution
> system.membus.trans_dist::ReadExResp 75 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 341 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 832 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
940c945
< system.membus.snoop_fanout::samples 415 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 416 # Request fanout histogram
944c949
< system.membus.snoop_fanout::0 415 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram
949,950c954,955
< system.membus.snoop_fanout::total 415 # Request fanout histogram
< system.membus.reqLayer0.occupancy 500000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 416 # Request fanout histogram
> system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks)
952,953c957,958
< system.membus.respLayer1.occupancy 2216750 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 10.6 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 2222250 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 10.4 # Layer utilization (%)