4,5c4,5
< sim_ticks 19744000 # Number of ticks simulated
< final_tick 19744000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 19678000 # Number of ticks simulated
> final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 27433 # Simulator instruction rate (inst/s)
< host_op_rate 49695 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 100653274 # Simulator tick rate (ticks/s)
< host_mem_usage 249652 # Number of bytes of host memory used
< host_seconds 0.20 # Real time elapsed on the host
---
> host_inst_rate 48979 # Simulator instruction rate (inst/s)
> host_op_rate 88725 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 179100946 # Simulator tick rate (ticks/s)
> host_mem_usage 305852 # Number of bytes of host memory used
> host_seconds 0.11 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 891410049 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 457050243 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1348460292 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 891410049 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 891410049 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 891410049 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 457050243 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1348460292 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 894399837 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 458583189 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1352983027 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 894399837 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 894399837 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 894399837 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 458583189 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1352983027 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 19695500 # Total gap between requests
---
> system.physmem.totGap 19629500 # Total gap between requests
93,95c93,95
< system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see
191,195c191,195
< system.physmem.bytesPerActivate::gmean 159.132678 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 257.193096 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 35 35.71% 35.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 32 32.65% 68.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 12 12.24% 80.61% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::gmean 158.475642 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 257.521253 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 36 36.73% 36.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 30 30.61% 67.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 13 13.27% 80.61% # Bytes accessed per row activation
201,202c201,202
< system.physmem.totQLat 4076000 # Total ticks spent queuing
< system.physmem.totMemAccLat 11894750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 4347000 # Total ticks spent queuing
> system.physmem.totMemAccLat 12165750 # Total ticks spent from burst creation until serviced by the DRAM
204c204
< system.physmem.avgQLat 9774.58 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 10424.46 # Average queueing delay per DRAM burst
206,207c206,207
< system.physmem.avgMemAccLat 28524.58 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1351.70 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 29174.46 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1356.24 # Average DRAM read bandwidth in MiByte/s
209c209
< system.physmem.avgRdBWSys 1351.70 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1356.24 # Average system read bandwidth in MiByte/s
212,213c212,213
< system.physmem.busUtil 10.56 # Data bus utilization in percentage
< system.physmem.busUtilRead 10.56 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 10.60 # Data bus utilization in percentage
> system.physmem.busUtilRead 10.60 # Data bus utilization in percentage for reads
215c215
< system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing
221c221
< system.physmem.avgGap 47231.41 # Average gap between requests
---
> system.physmem.avgGap 47073.14 # Average gap between requests
226c226
< system.physmem.memoryStateTime::ACT 15315250 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 15318250 # Time in different power states
228d227
< system.membus.throughput 1348460292 # Throughput (bytes/s)
236,240c235,248
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 26624 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 417 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 417 # Request fanout histogram
244c252
< system.membus.respLayer1.utilization 19.7 # Layer utilization (%)
---
> system.membus.respLayer1.utilization 19.8 # Layer utilization (%)
257c265
< system.cpu.numCycles 39489 # number of cpu cycles simulated
---
> system.cpu.numCycles 39357 # number of cpu cycles simulated
288,289c296,297
< system.cpu.fetch.branchRate 0.086682 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.393223 # Number of inst fetches per cycle
---
> system.cpu.fetch.branchRate 0.086973 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.394542 # Number of inst fetches per cycle
412c420
< system.cpu.iq.rate 0.453215 # Inst issue rate
---
> system.cpu.iq.rate 0.454735 # Inst issue rate
456c464
< system.cpu.iew.exec_rate 0.428626 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.430063 # Inst execution rate
462c470
< system.cpu.iew.wb_rate 0.414647 # insts written-back per cycle
---
> system.cpu.iew.wb_rate 0.416038 # insts written-back per cycle
535c543
< system.cpu.idleCycles 17596 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 17464 # Total number of cycles that the CPU has spent unscheduled due to idling
538,541c546,549
< system.cpu.cpi 7.339963 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 7.339963 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.136240 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.136240 # IPC: Total IPC of All Threads
---
> system.cpu.cpi 7.315428 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 7.315428 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.136697 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.136697 # IPC: Total IPC of All Threads
549d556
< system.cpu.toL2Bus.throughput 1351701783 # Throughput (bytes/s)
557,561c564,580
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 26688 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
564,566c583,585
< system.cpu.toL2Bus.respLayer0.occupancy 462750 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks)
569c588
< system.cpu.icache.tags.tagsinuse 131.753616 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 131.539722 # Cycle average of tags in use
574,576c593,595
< system.cpu.icache.tags.occ_blocks::cpu.inst 131.753616 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.064333 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.064333 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 131.539722 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.064228 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.064228 # Average percentage of cache occupancy
595,600c614,619
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 25386000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 25386000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 25386000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 25386000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 25386000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 25386000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25557250 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25557250 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25557250 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25557250 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25557250 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25557250 # number of overall miss cycles
613,618c632,637
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68983.695652 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 68983.695652 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 68983.695652 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 68983.695652 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 68983.695652 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 68983.695652 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69449.048913 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 69449.048913 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 69449.048913 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 69449.048913 # average overall miss latency
639,644c658,663
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19887250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 19887250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19887250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 19887250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19887250 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 19887250 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20059000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 20059000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20059000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 20059000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20059000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 20059000 # number of overall MSHR miss cycles
651,656c670,675
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72055.253623 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72055.253623 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72055.253623 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 72055.253623 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72055.253623 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 72055.253623 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72677.536232 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72677.536232 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency
659c678
< system.cpu.l2cache.tags.tagsinuse 163.478116 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 163.220102 # Cycle average of tags in use
664,668c683,687
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.827183 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31.650934 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004023 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.000966 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.004989 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.613484 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31.606618 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004017 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.004981 # Average percentage of cache occupancy
692c711
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19600750 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19772500 # number of ReadReq miss cycles
694,702c713,721
< system.cpu.l2cache.ReadReq_miss_latency::total 24547250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5508750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5508750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 19600750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10455250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 30056000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 19600750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10455250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 30056000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::total 24719000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5510000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5510000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 19772500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10456500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 30229000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 19772500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10456500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 30229000 # number of overall miss cycles
725c744
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71275.454545 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71900 # average ReadReq miss latency
727,735c746,754
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 72410.766962 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70625 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70625 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71275.454545 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73628.521127 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 72076.738609 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71275.454545 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73628.521127 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 72076.738609 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 72917.404130 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70641.025641 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70641.025641 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71900 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 72491.606715 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71900 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 72491.606715 # average overall miss latency
755c774
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16144250 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16317000 # number of ReadReq MSHR miss cycles
757,765c776,784
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20300250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4539250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16144250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8695250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 24839500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16144250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 24839500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20473000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4539500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16317000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8695500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 25012500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16317000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 25012500 # number of overall MSHR miss cycles
777c796
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58706.363636 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59334.545455 # average ReadReq mshr miss latency
779,787c798,806
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59882.743363 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58195.512821 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58195.512821 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58706.363636 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61234.154930 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59567.146283 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58706.363636 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61234.154930 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59567.146283 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60392.330383 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58198.717949 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58198.717949 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency
790c809
< system.cpu.dcache.tags.tagsinuse 82.450988 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use
795,797c814,816
< system.cpu.dcache.tags.occ_blocks::cpu.data 82.450988 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.020130 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.020130 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy
822,827c841,846
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5769250 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5769250 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 15584750 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 15584750 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 15584750 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 15584750 # number of overall miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles
846,851c865,870
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73964.743590 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 73964.743590 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 72825.934579 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 72825.934579 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 72825.934579 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 72825.934579 # average overall miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency
876,881c895,900
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5586750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5586750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10596250 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10596250 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10596250 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10596250 # number of overall MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles
892,897c911,916
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71625 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71625 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74621.478873 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 74621.478873 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74621.478873 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 74621.478873 # average overall mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency
< sim_ticks 19744000 # Number of ticks simulated
< final_tick 19744000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 19678000 # Number of ticks simulated
> final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 27433 # Simulator instruction rate (inst/s)
< host_op_rate 49695 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 100653274 # Simulator tick rate (ticks/s)
< host_mem_usage 249652 # Number of bytes of host memory used
< host_seconds 0.20 # Real time elapsed on the host
---
> host_inst_rate 48979 # Simulator instruction rate (inst/s)
> host_op_rate 88725 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 179100946 # Simulator tick rate (ticks/s)
> host_mem_usage 305852 # Number of bytes of host memory used
> host_seconds 0.11 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 891410049 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 457050243 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1348460292 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 891410049 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 891410049 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 891410049 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 457050243 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1348460292 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 894399837 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 458583189 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1352983027 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 894399837 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 894399837 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 894399837 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 458583189 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1352983027 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 19695500 # Total gap between requests
---
> system.physmem.totGap 19629500 # Total gap between requests
93,95c93,95
< system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see
191,195c191,195
< system.physmem.bytesPerActivate::gmean 159.132678 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 257.193096 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 35 35.71% 35.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 32 32.65% 68.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 12 12.24% 80.61% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::gmean 158.475642 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 257.521253 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 36 36.73% 36.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 30 30.61% 67.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 13 13.27% 80.61% # Bytes accessed per row activation
201,202c201,202
< system.physmem.totQLat 4076000 # Total ticks spent queuing
< system.physmem.totMemAccLat 11894750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 4347000 # Total ticks spent queuing
> system.physmem.totMemAccLat 12165750 # Total ticks spent from burst creation until serviced by the DRAM
204c204
< system.physmem.avgQLat 9774.58 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 10424.46 # Average queueing delay per DRAM burst
206,207c206,207
< system.physmem.avgMemAccLat 28524.58 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1351.70 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 29174.46 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1356.24 # Average DRAM read bandwidth in MiByte/s
209c209
< system.physmem.avgRdBWSys 1351.70 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1356.24 # Average system read bandwidth in MiByte/s
212,213c212,213
< system.physmem.busUtil 10.56 # Data bus utilization in percentage
< system.physmem.busUtilRead 10.56 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 10.60 # Data bus utilization in percentage
> system.physmem.busUtilRead 10.60 # Data bus utilization in percentage for reads
215c215
< system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing
221c221
< system.physmem.avgGap 47231.41 # Average gap between requests
---
> system.physmem.avgGap 47073.14 # Average gap between requests
226c226
< system.physmem.memoryStateTime::ACT 15315250 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 15318250 # Time in different power states
228d227
< system.membus.throughput 1348460292 # Throughput (bytes/s)
236,240c235,248
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 26624 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 417 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 417 # Request fanout histogram
244c252
< system.membus.respLayer1.utilization 19.7 # Layer utilization (%)
---
> system.membus.respLayer1.utilization 19.8 # Layer utilization (%)
257c265
< system.cpu.numCycles 39489 # number of cpu cycles simulated
---
> system.cpu.numCycles 39357 # number of cpu cycles simulated
288,289c296,297
< system.cpu.fetch.branchRate 0.086682 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.393223 # Number of inst fetches per cycle
---
> system.cpu.fetch.branchRate 0.086973 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.394542 # Number of inst fetches per cycle
412c420
< system.cpu.iq.rate 0.453215 # Inst issue rate
---
> system.cpu.iq.rate 0.454735 # Inst issue rate
456c464
< system.cpu.iew.exec_rate 0.428626 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.430063 # Inst execution rate
462c470
< system.cpu.iew.wb_rate 0.414647 # insts written-back per cycle
---
> system.cpu.iew.wb_rate 0.416038 # insts written-back per cycle
535c543
< system.cpu.idleCycles 17596 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 17464 # Total number of cycles that the CPU has spent unscheduled due to idling
538,541c546,549
< system.cpu.cpi 7.339963 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 7.339963 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.136240 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.136240 # IPC: Total IPC of All Threads
---
> system.cpu.cpi 7.315428 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 7.315428 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.136697 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.136697 # IPC: Total IPC of All Threads
549d556
< system.cpu.toL2Bus.throughput 1351701783 # Throughput (bytes/s)
557,561c564,580
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 26688 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
564,566c583,585
< system.cpu.toL2Bus.respLayer0.occupancy 462750 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks)
569c588
< system.cpu.icache.tags.tagsinuse 131.753616 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 131.539722 # Cycle average of tags in use
574,576c593,595
< system.cpu.icache.tags.occ_blocks::cpu.inst 131.753616 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.064333 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.064333 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 131.539722 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.064228 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.064228 # Average percentage of cache occupancy
595,600c614,619
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 25386000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 25386000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 25386000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 25386000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 25386000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 25386000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25557250 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25557250 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25557250 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25557250 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25557250 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25557250 # number of overall miss cycles
613,618c632,637
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68983.695652 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 68983.695652 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 68983.695652 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 68983.695652 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 68983.695652 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 68983.695652 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69449.048913 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 69449.048913 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 69449.048913 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 69449.048913 # average overall miss latency
639,644c658,663
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19887250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 19887250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19887250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 19887250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19887250 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 19887250 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20059000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 20059000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20059000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 20059000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20059000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 20059000 # number of overall MSHR miss cycles
651,656c670,675
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72055.253623 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72055.253623 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72055.253623 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 72055.253623 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72055.253623 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 72055.253623 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72677.536232 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72677.536232 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency
659c678
< system.cpu.l2cache.tags.tagsinuse 163.478116 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 163.220102 # Cycle average of tags in use
664,668c683,687
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.827183 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31.650934 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004023 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.000966 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.004989 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.613484 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31.606618 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004017 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.004981 # Average percentage of cache occupancy
692c711
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19600750 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19772500 # number of ReadReq miss cycles
694,702c713,721
< system.cpu.l2cache.ReadReq_miss_latency::total 24547250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5508750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5508750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 19600750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10455250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 30056000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 19600750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10455250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 30056000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::total 24719000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5510000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5510000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 19772500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10456500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 30229000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 19772500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10456500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 30229000 # number of overall miss cycles
725c744
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71275.454545 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71900 # average ReadReq miss latency
727,735c746,754
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 72410.766962 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70625 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70625 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71275.454545 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73628.521127 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 72076.738609 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71275.454545 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73628.521127 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 72076.738609 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 72917.404130 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70641.025641 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70641.025641 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71900 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 72491.606715 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71900 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 72491.606715 # average overall miss latency
755c774
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16144250 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16317000 # number of ReadReq MSHR miss cycles
757,765c776,784
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20300250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4539250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16144250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8695250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 24839500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16144250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 24839500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20473000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4539500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16317000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8695500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 25012500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16317000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 25012500 # number of overall MSHR miss cycles
777c796
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58706.363636 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59334.545455 # average ReadReq mshr miss latency
779,787c798,806
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59882.743363 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58195.512821 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58195.512821 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58706.363636 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61234.154930 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59567.146283 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58706.363636 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61234.154930 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59567.146283 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60392.330383 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58198.717949 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58198.717949 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency
790c809
< system.cpu.dcache.tags.tagsinuse 82.450988 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use
795,797c814,816
< system.cpu.dcache.tags.occ_blocks::cpu.data 82.450988 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.020130 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.020130 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy
822,827c841,846
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5769250 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5769250 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 15584750 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 15584750 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 15584750 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 15584750 # number of overall miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles
846,851c865,870
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73964.743590 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 73964.743590 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 72825.934579 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 72825.934579 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 72825.934579 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 72825.934579 # average overall miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency
876,881c895,900
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5586750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5586750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10596250 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10596250 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10596250 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10596250 # number of overall MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles
892,897c911,916
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71625 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71625 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74621.478873 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 74621.478873 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74621.478873 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 74621.478873 # average overall mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency