4,5c4,5
< sim_ticks 20069500 # Number of ticks simulated
< final_tick 20069500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 20011500 # Number of ticks simulated
> final_tick 20011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 42536 # Simulator instruction rate (inst/s)
< host_op_rate 77054 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 158640887 # Simulator tick rate (ticks/s)
< host_mem_usage 283320 # Number of bytes of host memory used
---
> host_inst_rate 41048 # Simulator instruction rate (inst/s)
> host_op_rate 74359 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 152650007 # Simulator tick rate (ticks/s)
> host_mem_usage 284392 # Number of bytes of host memory used
24,31c24,31
< system.physmem.bw_read::cpu.inst 870574753 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 449637510 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1320212262 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 870574753 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 870574753 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 870574753 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 449637510 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1320212262 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 873097969 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 450940709 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1324038678 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 873097969 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 873097969 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 873097969 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 450940709 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1324038678 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 20021000 # Total gap between requests
---
> system.physmem.totGap 19963000 # Total gap between requests
189,202c189,202
< system.physmem.bytesPerActivate::samples 71 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 240.676056 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 152.837127 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 281.987222 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 26 36.62% 36.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 26 36.62% 73.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 8 11.27% 84.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2 2.82% 87.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2 2.82% 90.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 2 2.82% 92.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 5 7.04% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 71 # Bytes accessed per row activation
< system.physmem.totQLat 2360500 # Total ticks spent queuing
< system.physmem.totMemAccLat 12135500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 248.742268 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 161.697208 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 270.249471 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 33 34.02% 34.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 34 35.05% 69.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 13 13.40% 82.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3 3.09% 85.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 6 6.19% 91.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 3 3.09% 94.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation
> system.physmem.totQLat 4234000 # Total ticks spent queuing
> system.physmem.totMemAccLat 12015250 # Total ticks spent from burst creation until serviced by the DRAM
204,206c204
< system.physmem.totBankLat 7700000 # Total ticks spent accessing banks
< system.physmem.avgQLat 5687.95 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 18554.22 # Average bank access latency per DRAM burst
---
> system.physmem.avgQLat 10202.41 # Average queueing delay per DRAM burst
208,209c206,207
< system.physmem.avgMemAccLat 29242.17 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1323.40 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28952.41 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1327.24 # Average DRAM read bandwidth in MiByte/s
211c209
< system.physmem.avgRdBWSys 1323.40 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1327.24 # Average system read bandwidth in MiByte/s
214,215c212,213
< system.physmem.busUtil 10.34 # Data bus utilization in percentage
< system.physmem.busUtilRead 10.34 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 10.37 # Data bus utilization in percentage
> system.physmem.busUtilRead 10.37 # Data bus utilization in percentage for reads
223c221
< system.physmem.avgGap 48243.37 # Average gap between requests
---
> system.physmem.avgGap 48103.61 # Average gap between requests
225,226c223,228
< system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state
< system.membus.throughput 1320212262 # Throughput (bytes/s)
---
> system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
> system.physmem.memoryStateTime::REF 520000 # Time in different power states
> system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
> system.physmem.memoryStateTime::ACT 15333750 # Time in different power states
> system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
> system.membus.throughput 1324038678 # Throughput (bytes/s)
239c241
< system.membus.reqLayer0.occupancy 500500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 501000 # Layer occupancy (ticks)
241,242c243,244
< system.membus.respLayer1.occupancy 3871750 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 19.3 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 3873250 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 19.4 # Layer utilization (%)
244,248c246,250
< system.cpu.branchPred.lookups 3084 # Number of BP lookups
< system.cpu.branchPred.condPredicted 3084 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 542 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 2283 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 726 # Number of BTB hits
---
> system.cpu.branchPred.lookups 3083 # Number of BP lookups
> system.cpu.branchPred.condPredicted 3083 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 2281 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 725 # Number of BTB hits
250c252
< system.cpu.branchPred.BTBHitPct 31.800263 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 31.784305 # BTB Hit Percentage
255c257
< system.cpu.numCycles 40140 # number of cpu cycles simulated
---
> system.cpu.numCycles 40024 # number of cpu cycles simulated
258,264c260,266
< system.cpu.fetch.icacheStallCycles 10289 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 14134 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 3084 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 3940 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 5352 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.icacheStallCycles 10292 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 14141 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 3083 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 3942 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 2472 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 5349 # Number of cycles fetch has spent blocked
268,272c270,274
< system.cpu.fetch.CacheLines 1980 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 21899 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.150509 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.666400 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 1981 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 21900 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.150913 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.666787 # Number of instructions fetched each cycle (Total)
274,275c276,277
< system.cpu.fetch.rateDist::0 18060 82.47% 82.47% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 216 0.99% 83.46% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 18059 82.46% 82.46% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 217 0.99% 83.45% # Number of instructions fetched each cycle (Total)
277,279c279,281
< system.cpu.fetch.rateDist::3 224 1.02% 85.13% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 181 0.83% 85.95% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 200 0.91% 86.87% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::3 224 1.02% 85.12% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 180 0.82% 85.95% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 201 0.92% 86.86% # Number of instructions fetched each cycle (Total)
281,282c283,284
< system.cpu.fetch.rateDist::7 159 0.73% 88.85% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 2442 11.15% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::7 159 0.73% 88.84% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 2443 11.16% 100.00% # Number of instructions fetched each cycle (Total)
286,290c288,292
< system.cpu.fetch.rateDist::total 21899 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.076831 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.352118 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 11081 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 5247 # Number of cycles decode is blocked
---
> system.cpu.fetch.rateDist::total 21900 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.077029 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.353313 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 11088 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 5242 # Number of cycles decode is blocked
293,296c295,298
< system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 24173 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 11446 # Number of cycles rename is idle
---
> system.cpu.decode.SquashCycles 1856 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 24179 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 1856 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 11454 # Number of cycles rename is idle
298,301c300,303
< system.cpu.rename.serializeStallCycles 603 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 3331 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 776 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 22661 # Number of instructions processed by rename
---
> system.cpu.rename.serializeStallCycles 592 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 3330 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 782 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 22657 # Number of instructions processed by rename
303,306c305,308
< system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 663 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.RenamedOperands 25256 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 55040 # Number of register rename lookups that rename has made
---
> system.cpu.rename.IQFullEvents 37 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 664 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.RenamedOperands 25254 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 55037 # Number of register rename lookups that rename has made
310c312
< system.cpu.rename.UndoneMaps 14193 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 14191 # Number of HB maps that are undone due to squashing
313c315
< system.cpu.rename.skidInsts 2047 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 2053 # count of insts added to the skid buffer
318c320
< system.cpu.iq.iqInstsAdded 20236 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 20246 # Number of instructions added to the IQ (excludes non-spec)
320,323c322,325
< system.cpu.iq.iqInstsIssued 17027 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 9729 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 13960 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 17025 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 298 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 9739 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 13977 # Number of squashed operands that are examined and possibly removed from graph
325,327c327,329
< system.cpu.iq.issued_per_cycle::samples 21899 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.777524 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.652832 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 21900 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.777397 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.653011 # Number of insts issued each cycle
329,335c331,337
< system.cpu.iq.issued_per_cycle::0 16413 74.95% 74.95% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1539 7.03% 81.98% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1092 4.99% 86.96% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 724 3.31% 90.27% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 698 3.19% 93.46% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 576 2.63% 96.09% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 581 2.65% 98.74% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 16414 74.95% 74.95% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1544 7.05% 82.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1087 4.96% 86.96% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 722 3.30% 90.26% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 701 3.20% 93.46% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 573 2.62% 96.08% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 583 2.66% 98.74% # Number of insts issued each cycle
341c343
< system.cpu.iq.issued_per_cycle::total 21899 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 21900 # Number of insts issued each cycle
377c379
< system.cpu.iq.FU_type_0::IntAlu 13667 80.27% 80.28% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 13665 80.26% 80.28% # Type of FU issued
410,411c412,413
< system.cpu.iq.FU_type_0::total 17027 # Type of FU issued
< system.cpu.iq.rate 0.424190 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 17025 # Type of FU issued
> system.cpu.iq.rate 0.425370 # Inst issue rate
413,416c415,418
< system.cpu.iq.fu_busy_rate 0.010630 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 56416 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 29998 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 15642 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.fu_busy_rate 0.010631 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 56421 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 30018 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 15641 # Number of integer instruction queue wakeup accesses
420c422
< system.cpu.iq.int_alu_accesses 17201 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 17199 # Number of integer alu accesses
433,434c435,436
< system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 3086 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewSquashCycles 1856 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 3085 # Number of cycles IEW is blocking
436c438
< system.cpu.iew.iewDispatchedInsts 20262 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 20272 # Number of instructions dispatched to IQ
445,448c447,450
< system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 686 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 16124 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 1854 # Number of load instructions executed
---
> system.cpu.iew.predictedNotTakenIncorrect 571 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 687 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 16122 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 1853 # Number of load instructions executed
452c454
< system.cpu.iew.exec_refs 3127 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 3126 # number of memory reference insts executed
455,457c457,459
< system.cpu.iew.exec_rate 0.401694 # Inst execution rate
< system.cpu.iew.wb_sent 15865 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 15646 # cumulative count of insts written-back
---
> system.cpu.iew.exec_rate 0.402808 # Inst execution rate
> system.cpu.iew.wb_sent 15864 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 15645 # cumulative count of insts written-back
459c461
< system.cpu.iew.wb_consumers 15579 # num instructions consuming a value
---
> system.cpu.iew.wb_consumers 15590 # num instructions consuming a value
461,462c463,464
< system.cpu.iew.wb_rate 0.389786 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.650106 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.390890 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.649647 # average fanout of values written-back
464c466
< system.cpu.commit.commitSquashedInsts 10526 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 10536 # The number of squashed insts skipped by commit
466,469c468,471
< system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 20042 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.486329 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.342699 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 592 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 20044 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.486280 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.342641 # Number of insts commited each cycle
471c473
< system.cpu.commit.committed_per_cycle::0 16474 82.20% 82.20% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 16476 82.20% 82.20% # Number of insts commited each cycle
483c485
< system.cpu.commit.committed_per_cycle::total 20042 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 20044 # Number of insts commited each cycle
493a496,530
> system.cpu.commit.op_class_0::No_OpClass 1 0.01% 0.01% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 7748 79.49% 79.50% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 3 0.03% 79.53% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 7 0.07% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatAdd 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCmp 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCvt 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMult 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatDiv 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAdd 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAlu 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCmp 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCvt 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMisc 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMult 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShift 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::total 9747 # Class of committed instruction
496,499c533,536
< system.cpu.rob.rob_reads 40103 # The number of ROB reads
< system.cpu.rob.rob_writes 42426 # The number of ROB writes
< system.cpu.timesIdled 166 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 18241 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 40115 # The number of ROB reads
> system.cpu.rob.rob_writes 42444 # The number of ROB writes
> system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 18124 # Total number of cycles that the CPU has spent unscheduled due to idling
503,508c540,545
< system.cpu.cpi 7.460967 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 7.460967 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.134031 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.134031 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 20727 # number of integer regfile reads
< system.cpu.int_regfile_writes 12358 # number of integer regfile writes
---
> system.cpu.cpi 7.439405 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 7.439405 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.134419 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.134419 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 20731 # number of integer regfile reads
> system.cpu.int_regfile_writes 12356 # number of integer regfile writes
510,512c547,549
< system.cpu.cc_regfile_reads 8004 # number of cc regfile reads
< system.cpu.cc_regfile_writes 4850 # number of cc regfile writes
< system.cpu.misc_regfile_reads 7135 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 8007 # number of cc regfile reads
> system.cpu.cc_regfile_writes 4854 # number of cc regfile writes
> system.cpu.misc_regfile_reads 7133 # number of misc regfile reads
514c551
< system.cpu.toL2Bus.throughput 1326590099 # Throughput (bytes/s)
---
> system.cpu.toL2Bus.throughput 1330435000 # Throughput (bytes/s)
529c566
< system.cpu.toL2Bus.respLayer0.occupancy 458250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 459500 # Layer occupancy (ticks)
531c568
< system.cpu.toL2Bus.respLayer1.occupancy 235500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 236250 # Layer occupancy (ticks)
534,535c571,572
< system.cpu.icache.tags.tagsinuse 130.897576 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 130.942440 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks.
537c574
< system.cpu.icache.tags.avg_refs 5.872263 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 5.875912 # Average number of references to valid blocks.
539,541c576,578
< system.cpu.icache.tags.occ_blocks::cpu.inst 130.897576 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.063915 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.063915 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 130.942440 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.063937 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.063937 # Average percentage of cache occupancy
546,553c583,590
< system.cpu.icache.tags.tag_accesses 4234 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4234 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1609 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1609 # number of overall hits
< system.cpu.icache.overall_hits::total 1609 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 4236 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4236 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1610 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1610 # number of overall hits
> system.cpu.icache.overall_hits::total 1610 # number of overall hits
560,583c597,620
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 25180750 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 25180750 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 25180750 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 25180750 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 25180750 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 25180750 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 1980 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 1980 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 1980 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 1980 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 1980 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187374 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.187374 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.187374 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.187374 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.187374 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.187374 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67872.641509 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 67872.641509 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 67872.641509 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 67872.641509 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 67872.641509 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 67872.641509 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25106250 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25106250 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25106250 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25106250 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25106250 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25106250 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 1981 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 1981 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 1981 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 1981 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 1981 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 1981 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187279 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.187279 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.187279 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.187279 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.187279 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.187279 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67671.832884 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 67671.832884 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 67671.832884 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 67671.832884 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 67671.832884 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 67671.832884 # average overall miss latency
604,621c641,658
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19745750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 19745750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19745750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 19745750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19745750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 19745750 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138384 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.138384 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.138384 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72064.781022 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72064.781022 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72064.781022 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 72064.781022 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72064.781022 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 72064.781022 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19660000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 19660000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19660000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 19660000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19660000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 19660000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138314 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.138314 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.138314 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71751.824818 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71751.824818 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71751.824818 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 71751.824818 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71751.824818 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 71751.824818 # average overall mshr miss latency
624c661
< system.cpu.l2cache.tags.tagsinuse 163.708534 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 163.759335 # Cycle average of tags in use
629,631c666,668
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.966386 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 32.742148 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003997 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.011600 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 32.747734 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003998 # Average percentage of cache occupancy
633c670
< system.cpu.l2cache.tags.occ_percent::total 0.004996 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.004998 # Average percentage of cache occupancy
635,636c672,673
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id
660,670c697,707
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19460250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5265000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 24725250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5444500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5444500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 19460250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10709500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 30169750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 19460250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10709500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 30169750 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19374500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5212250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 24586750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5445500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5445500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 19374500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10657750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 30032250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 19374500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10657750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 30032250 # number of overall miss cycles
693,703c730,740
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71282.967033 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 73151.627219 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70707.792208 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70707.792208 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71282.967033 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75419.014085 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 72698.192771 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71282.967033 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75419.014085 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 72698.192771 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70968.864469 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80188.461538 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 72741.863905 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70720.779221 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70720.779221 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70968.864469 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75054.577465 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 72366.867470 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70968.864469 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75054.577465 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 72366.867470 # average overall miss latency
723,733c760,770
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16034750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4466500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20501250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4485000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4485000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16034750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8951500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 24986250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16034750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8951500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 24986250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15946000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4413250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20359250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4486000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4486000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15946000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8899250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 24845250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15946000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8899250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 24845250 # number of overall MSHR miss cycles
745,755c782,792
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58735.347985 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68715.384615 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60654.585799 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58246.753247 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58246.753247 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58735.347985 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63038.732394 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60207.831325 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58735.347985 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63038.732394 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60207.831325 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58410.256410 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67896.153846 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60234.467456 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58259.740260 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58259.740260 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58410.256410 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62670.774648 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59868.072289 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58410.256410 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62670.774648 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59868.072289 # average overall mshr miss latency
758,759c795,796
< system.cpu.dcache.tags.tagsinuse 83.267922 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2337 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 83.261165 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2335 # Total number of references to valid blocks.
761c798
< system.cpu.dcache.tags.avg_refs 16.457746 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 16.443662 # Average number of references to valid blocks.
763,765c800,802
< system.cpu.dcache.tags.occ_blocks::cpu.data 83.267922 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.020329 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.020329 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 83.261165 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.020327 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.020327 # Average percentage of cache occupancy
770,773c807,810
< system.cpu.dcache.tags.tag_accesses 5234 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5234 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1479 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1479 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 5232 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 5232 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits
776,781c813,818
< system.cpu.dcache.demand_hits::cpu.data 2337 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2337 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2337 # number of overall hits
< system.cpu.dcache.overall_hits::total 2337 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 132 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 2335 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2335 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2335 # number of overall hits
> system.cpu.dcache.overall_hits::total 2335 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses
784,797c821,834
< system.cpu.dcache.demand_misses::cpu.data 209 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 209 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 209 # number of overall misses
< system.cpu.dcache.overall_misses::total 209 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9669000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9669000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5702500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5702500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 15371500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 15371500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 15371500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 15371500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1611 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1611 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 210 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 210 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 210 # number of overall misses
> system.cpu.dcache.overall_misses::total 210 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 9645750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 9645750 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5703500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5703500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 15349250 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 15349250 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 15349250 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 15349250 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1610 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1610 # number of ReadReq accesses(hits+misses)
800,805c837,842
< system.cpu.dcache.demand_accesses::cpu.data 2546 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2546 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2546 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2546 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081937 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.081937 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2545 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2545 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2545 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2545 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082609 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.082609 # miss rate for ReadReq accesses
808,819c845,856
< system.cpu.dcache.demand_miss_rate::cpu.data 0.082090 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.082090 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.082090 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.082090 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73250 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 73250 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74058.441558 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 74058.441558 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 73547.846890 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 73547.846890 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 73547.846890 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 73547.846890 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.082515 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.082515 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.082515 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.082515 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72524.436090 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 72524.436090 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74071.428571 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 74071.428571 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 73091.666667 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 73091.666667 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 73091.666667 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 73091.666667 # average overall miss latency
828,833c865,870
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 67 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 67 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 67 # number of overall MSHR hits
842,851c879,888
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5340000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5340000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5521500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5521500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10861500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10861500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10861500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10861500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040968 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040968 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287250 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287250 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5522500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5522500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10809750 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10809750 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10809750 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10809750 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040994 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040994 # mshr miss rate for ReadReq accesses
854,865c891,902
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.056167 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.056167 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80909.090909 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80909.090909 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71707.792208 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71707.792208 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75954.545455 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 75954.545455 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75954.545455 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 75954.545455 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056189 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.056189 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056189 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.056189 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80109.848485 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80109.848485 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71720.779221 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71720.779221 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75592.657343 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 75592.657343 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75592.657343 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 75592.657343 # average overall mshr miss latency
< sim_ticks 20069500 # Number of ticks simulated
< final_tick 20069500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 20011500 # Number of ticks simulated
> final_tick 20011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 42536 # Simulator instruction rate (inst/s)
< host_op_rate 77054 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 158640887 # Simulator tick rate (ticks/s)
< host_mem_usage 283320 # Number of bytes of host memory used
---
> host_inst_rate 41048 # Simulator instruction rate (inst/s)
> host_op_rate 74359 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 152650007 # Simulator tick rate (ticks/s)
> host_mem_usage 284392 # Number of bytes of host memory used
24,31c24,31
< system.physmem.bw_read::cpu.inst 870574753 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 449637510 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1320212262 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 870574753 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 870574753 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 870574753 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 449637510 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1320212262 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 873097969 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 450940709 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1324038678 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 873097969 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 873097969 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 873097969 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 450940709 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1324038678 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 20021000 # Total gap between requests
---
> system.physmem.totGap 19963000 # Total gap between requests
189,202c189,202
< system.physmem.bytesPerActivate::samples 71 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 240.676056 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 152.837127 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 281.987222 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 26 36.62% 36.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 26 36.62% 73.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 8 11.27% 84.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2 2.82% 87.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2 2.82% 90.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 2 2.82% 92.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 5 7.04% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 71 # Bytes accessed per row activation
< system.physmem.totQLat 2360500 # Total ticks spent queuing
< system.physmem.totMemAccLat 12135500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 248.742268 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 161.697208 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 270.249471 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 33 34.02% 34.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 34 35.05% 69.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 13 13.40% 82.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3 3.09% 85.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 6 6.19% 91.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 3 3.09% 94.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation
> system.physmem.totQLat 4234000 # Total ticks spent queuing
> system.physmem.totMemAccLat 12015250 # Total ticks spent from burst creation until serviced by the DRAM
204,206c204
< system.physmem.totBankLat 7700000 # Total ticks spent accessing banks
< system.physmem.avgQLat 5687.95 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 18554.22 # Average bank access latency per DRAM burst
---
> system.physmem.avgQLat 10202.41 # Average queueing delay per DRAM burst
208,209c206,207
< system.physmem.avgMemAccLat 29242.17 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1323.40 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28952.41 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1327.24 # Average DRAM read bandwidth in MiByte/s
211c209
< system.physmem.avgRdBWSys 1323.40 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1327.24 # Average system read bandwidth in MiByte/s
214,215c212,213
< system.physmem.busUtil 10.34 # Data bus utilization in percentage
< system.physmem.busUtilRead 10.34 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 10.37 # Data bus utilization in percentage
> system.physmem.busUtilRead 10.37 # Data bus utilization in percentage for reads
223c221
< system.physmem.avgGap 48243.37 # Average gap between requests
---
> system.physmem.avgGap 48103.61 # Average gap between requests
225,226c223,228
< system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state
< system.membus.throughput 1320212262 # Throughput (bytes/s)
---
> system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
> system.physmem.memoryStateTime::REF 520000 # Time in different power states
> system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
> system.physmem.memoryStateTime::ACT 15333750 # Time in different power states
> system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
> system.membus.throughput 1324038678 # Throughput (bytes/s)
239c241
< system.membus.reqLayer0.occupancy 500500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 501000 # Layer occupancy (ticks)
241,242c243,244
< system.membus.respLayer1.occupancy 3871750 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 19.3 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 3873250 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 19.4 # Layer utilization (%)
244,248c246,250
< system.cpu.branchPred.lookups 3084 # Number of BP lookups
< system.cpu.branchPred.condPredicted 3084 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 542 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 2283 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 726 # Number of BTB hits
---
> system.cpu.branchPred.lookups 3083 # Number of BP lookups
> system.cpu.branchPred.condPredicted 3083 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 2281 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 725 # Number of BTB hits
250c252
< system.cpu.branchPred.BTBHitPct 31.800263 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 31.784305 # BTB Hit Percentage
255c257
< system.cpu.numCycles 40140 # number of cpu cycles simulated
---
> system.cpu.numCycles 40024 # number of cpu cycles simulated
258,264c260,266
< system.cpu.fetch.icacheStallCycles 10289 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 14134 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 3084 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 3940 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 5352 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.icacheStallCycles 10292 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 14141 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 3083 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 3942 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 2472 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 5349 # Number of cycles fetch has spent blocked
268,272c270,274
< system.cpu.fetch.CacheLines 1980 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 21899 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.150509 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.666400 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 1981 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 21900 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.150913 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.666787 # Number of instructions fetched each cycle (Total)
274,275c276,277
< system.cpu.fetch.rateDist::0 18060 82.47% 82.47% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 216 0.99% 83.46% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 18059 82.46% 82.46% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 217 0.99% 83.45% # Number of instructions fetched each cycle (Total)
277,279c279,281
< system.cpu.fetch.rateDist::3 224 1.02% 85.13% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 181 0.83% 85.95% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 200 0.91% 86.87% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::3 224 1.02% 85.12% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 180 0.82% 85.95% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 201 0.92% 86.86% # Number of instructions fetched each cycle (Total)
281,282c283,284
< system.cpu.fetch.rateDist::7 159 0.73% 88.85% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 2442 11.15% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::7 159 0.73% 88.84% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 2443 11.16% 100.00% # Number of instructions fetched each cycle (Total)
286,290c288,292
< system.cpu.fetch.rateDist::total 21899 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.076831 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.352118 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 11081 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 5247 # Number of cycles decode is blocked
---
> system.cpu.fetch.rateDist::total 21900 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.077029 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.353313 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 11088 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 5242 # Number of cycles decode is blocked
293,296c295,298
< system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 24173 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 11446 # Number of cycles rename is idle
---
> system.cpu.decode.SquashCycles 1856 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 24179 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 1856 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 11454 # Number of cycles rename is idle
298,301c300,303
< system.cpu.rename.serializeStallCycles 603 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 3331 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 776 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 22661 # Number of instructions processed by rename
---
> system.cpu.rename.serializeStallCycles 592 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 3330 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 782 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 22657 # Number of instructions processed by rename
303,306c305,308
< system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 663 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.RenamedOperands 25256 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 55040 # Number of register rename lookups that rename has made
---
> system.cpu.rename.IQFullEvents 37 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 664 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.RenamedOperands 25254 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 55037 # Number of register rename lookups that rename has made
310c312
< system.cpu.rename.UndoneMaps 14193 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 14191 # Number of HB maps that are undone due to squashing
313c315
< system.cpu.rename.skidInsts 2047 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 2053 # count of insts added to the skid buffer
318c320
< system.cpu.iq.iqInstsAdded 20236 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 20246 # Number of instructions added to the IQ (excludes non-spec)
320,323c322,325
< system.cpu.iq.iqInstsIssued 17027 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 9729 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 13960 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 17025 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 298 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 9739 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 13977 # Number of squashed operands that are examined and possibly removed from graph
325,327c327,329
< system.cpu.iq.issued_per_cycle::samples 21899 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.777524 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.652832 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 21900 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.777397 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.653011 # Number of insts issued each cycle
329,335c331,337
< system.cpu.iq.issued_per_cycle::0 16413 74.95% 74.95% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1539 7.03% 81.98% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1092 4.99% 86.96% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 724 3.31% 90.27% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 698 3.19% 93.46% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 576 2.63% 96.09% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 581 2.65% 98.74% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 16414 74.95% 74.95% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1544 7.05% 82.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1087 4.96% 86.96% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 722 3.30% 90.26% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 701 3.20% 93.46% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 573 2.62% 96.08% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 583 2.66% 98.74% # Number of insts issued each cycle
341c343
< system.cpu.iq.issued_per_cycle::total 21899 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 21900 # Number of insts issued each cycle
377c379
< system.cpu.iq.FU_type_0::IntAlu 13667 80.27% 80.28% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 13665 80.26% 80.28% # Type of FU issued
410,411c412,413
< system.cpu.iq.FU_type_0::total 17027 # Type of FU issued
< system.cpu.iq.rate 0.424190 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 17025 # Type of FU issued
> system.cpu.iq.rate 0.425370 # Inst issue rate
413,416c415,418
< system.cpu.iq.fu_busy_rate 0.010630 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 56416 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 29998 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 15642 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.fu_busy_rate 0.010631 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 56421 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 30018 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 15641 # Number of integer instruction queue wakeup accesses
420c422
< system.cpu.iq.int_alu_accesses 17201 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 17199 # Number of integer alu accesses
433,434c435,436
< system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 3086 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewSquashCycles 1856 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 3085 # Number of cycles IEW is blocking
436c438
< system.cpu.iew.iewDispatchedInsts 20262 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 20272 # Number of instructions dispatched to IQ
445,448c447,450
< system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 686 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 16124 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 1854 # Number of load instructions executed
---
> system.cpu.iew.predictedNotTakenIncorrect 571 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 687 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 16122 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 1853 # Number of load instructions executed
452c454
< system.cpu.iew.exec_refs 3127 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 3126 # number of memory reference insts executed
455,457c457,459
< system.cpu.iew.exec_rate 0.401694 # Inst execution rate
< system.cpu.iew.wb_sent 15865 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 15646 # cumulative count of insts written-back
---
> system.cpu.iew.exec_rate 0.402808 # Inst execution rate
> system.cpu.iew.wb_sent 15864 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 15645 # cumulative count of insts written-back
459c461
< system.cpu.iew.wb_consumers 15579 # num instructions consuming a value
---
> system.cpu.iew.wb_consumers 15590 # num instructions consuming a value
461,462c463,464
< system.cpu.iew.wb_rate 0.389786 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.650106 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.390890 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.649647 # average fanout of values written-back
464c466
< system.cpu.commit.commitSquashedInsts 10526 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 10536 # The number of squashed insts skipped by commit
466,469c468,471
< system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 20042 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.486329 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.342699 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 592 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 20044 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.486280 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.342641 # Number of insts commited each cycle
471c473
< system.cpu.commit.committed_per_cycle::0 16474 82.20% 82.20% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 16476 82.20% 82.20% # Number of insts commited each cycle
483c485
< system.cpu.commit.committed_per_cycle::total 20042 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 20044 # Number of insts commited each cycle
493a496,530
> system.cpu.commit.op_class_0::No_OpClass 1 0.01% 0.01% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 7748 79.49% 79.50% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 3 0.03% 79.53% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 7 0.07% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatAdd 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCmp 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCvt 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMult 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatDiv 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAdd 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAlu 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCmp 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCvt 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMisc 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMult 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShift 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction
> system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::total 9747 # Class of committed instruction
496,499c533,536
< system.cpu.rob.rob_reads 40103 # The number of ROB reads
< system.cpu.rob.rob_writes 42426 # The number of ROB writes
< system.cpu.timesIdled 166 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 18241 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 40115 # The number of ROB reads
> system.cpu.rob.rob_writes 42444 # The number of ROB writes
> system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 18124 # Total number of cycles that the CPU has spent unscheduled due to idling
503,508c540,545
< system.cpu.cpi 7.460967 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 7.460967 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.134031 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.134031 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 20727 # number of integer regfile reads
< system.cpu.int_regfile_writes 12358 # number of integer regfile writes
---
> system.cpu.cpi 7.439405 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 7.439405 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.134419 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.134419 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 20731 # number of integer regfile reads
> system.cpu.int_regfile_writes 12356 # number of integer regfile writes
510,512c547,549
< system.cpu.cc_regfile_reads 8004 # number of cc regfile reads
< system.cpu.cc_regfile_writes 4850 # number of cc regfile writes
< system.cpu.misc_regfile_reads 7135 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 8007 # number of cc regfile reads
> system.cpu.cc_regfile_writes 4854 # number of cc regfile writes
> system.cpu.misc_regfile_reads 7133 # number of misc regfile reads
514c551
< system.cpu.toL2Bus.throughput 1326590099 # Throughput (bytes/s)
---
> system.cpu.toL2Bus.throughput 1330435000 # Throughput (bytes/s)
529c566
< system.cpu.toL2Bus.respLayer0.occupancy 458250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 459500 # Layer occupancy (ticks)
531c568
< system.cpu.toL2Bus.respLayer1.occupancy 235500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 236250 # Layer occupancy (ticks)
534,535c571,572
< system.cpu.icache.tags.tagsinuse 130.897576 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 130.942440 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks.
537c574
< system.cpu.icache.tags.avg_refs 5.872263 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 5.875912 # Average number of references to valid blocks.
539,541c576,578
< system.cpu.icache.tags.occ_blocks::cpu.inst 130.897576 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.063915 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.063915 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 130.942440 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.063937 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.063937 # Average percentage of cache occupancy
546,553c583,590
< system.cpu.icache.tags.tag_accesses 4234 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4234 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1609 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1609 # number of overall hits
< system.cpu.icache.overall_hits::total 1609 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 4236 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4236 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1610 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1610 # number of overall hits
> system.cpu.icache.overall_hits::total 1610 # number of overall hits
560,583c597,620
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 25180750 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 25180750 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 25180750 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 25180750 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 25180750 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 25180750 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 1980 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 1980 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 1980 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 1980 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 1980 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187374 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.187374 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.187374 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.187374 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.187374 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.187374 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67872.641509 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 67872.641509 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 67872.641509 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 67872.641509 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 67872.641509 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 67872.641509 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25106250 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25106250 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25106250 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25106250 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25106250 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25106250 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 1981 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 1981 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 1981 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 1981 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 1981 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 1981 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187279 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.187279 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.187279 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.187279 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.187279 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.187279 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67671.832884 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 67671.832884 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 67671.832884 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 67671.832884 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 67671.832884 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 67671.832884 # average overall miss latency
604,621c641,658
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19745750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 19745750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19745750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 19745750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19745750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 19745750 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138384 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.138384 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.138384 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72064.781022 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72064.781022 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72064.781022 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 72064.781022 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72064.781022 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 72064.781022 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19660000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 19660000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19660000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 19660000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19660000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 19660000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138314 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.138314 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.138314 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71751.824818 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71751.824818 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71751.824818 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 71751.824818 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71751.824818 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 71751.824818 # average overall mshr miss latency
624c661
< system.cpu.l2cache.tags.tagsinuse 163.708534 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 163.759335 # Cycle average of tags in use
629,631c666,668
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.966386 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 32.742148 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003997 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.011600 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 32.747734 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003998 # Average percentage of cache occupancy
633c670
< system.cpu.l2cache.tags.occ_percent::total 0.004996 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.004998 # Average percentage of cache occupancy
635,636c672,673
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id
660,670c697,707
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19460250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5265000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 24725250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5444500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5444500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 19460250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10709500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 30169750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 19460250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10709500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 30169750 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19374500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5212250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 24586750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5445500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5445500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 19374500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10657750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 30032250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 19374500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10657750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 30032250 # number of overall miss cycles
693,703c730,740
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71282.967033 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 73151.627219 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70707.792208 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70707.792208 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71282.967033 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75419.014085 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 72698.192771 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71282.967033 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75419.014085 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 72698.192771 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70968.864469 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80188.461538 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 72741.863905 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70720.779221 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70720.779221 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70968.864469 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75054.577465 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 72366.867470 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70968.864469 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75054.577465 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 72366.867470 # average overall miss latency
723,733c760,770
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16034750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4466500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20501250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4485000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4485000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16034750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8951500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 24986250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16034750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8951500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 24986250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15946000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4413250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20359250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4486000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4486000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15946000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8899250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 24845250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15946000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8899250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 24845250 # number of overall MSHR miss cycles
745,755c782,792
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58735.347985 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68715.384615 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60654.585799 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58246.753247 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58246.753247 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58735.347985 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63038.732394 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60207.831325 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58735.347985 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63038.732394 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60207.831325 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58410.256410 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67896.153846 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60234.467456 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58259.740260 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58259.740260 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58410.256410 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62670.774648 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59868.072289 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58410.256410 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62670.774648 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59868.072289 # average overall mshr miss latency
758,759c795,796
< system.cpu.dcache.tags.tagsinuse 83.267922 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2337 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 83.261165 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2335 # Total number of references to valid blocks.
761c798
< system.cpu.dcache.tags.avg_refs 16.457746 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 16.443662 # Average number of references to valid blocks.
763,765c800,802
< system.cpu.dcache.tags.occ_blocks::cpu.data 83.267922 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.020329 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.020329 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 83.261165 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.020327 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.020327 # Average percentage of cache occupancy
770,773c807,810
< system.cpu.dcache.tags.tag_accesses 5234 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5234 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1479 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1479 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 5232 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 5232 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits
776,781c813,818
< system.cpu.dcache.demand_hits::cpu.data 2337 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2337 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2337 # number of overall hits
< system.cpu.dcache.overall_hits::total 2337 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 132 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 2335 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2335 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2335 # number of overall hits
> system.cpu.dcache.overall_hits::total 2335 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses
784,797c821,834
< system.cpu.dcache.demand_misses::cpu.data 209 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 209 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 209 # number of overall misses
< system.cpu.dcache.overall_misses::total 209 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9669000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9669000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5702500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5702500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 15371500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 15371500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 15371500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 15371500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1611 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1611 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 210 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 210 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 210 # number of overall misses
> system.cpu.dcache.overall_misses::total 210 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 9645750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 9645750 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5703500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5703500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 15349250 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 15349250 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 15349250 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 15349250 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1610 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1610 # number of ReadReq accesses(hits+misses)
800,805c837,842
< system.cpu.dcache.demand_accesses::cpu.data 2546 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2546 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2546 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2546 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081937 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.081937 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2545 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2545 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2545 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2545 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082609 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.082609 # miss rate for ReadReq accesses
808,819c845,856
< system.cpu.dcache.demand_miss_rate::cpu.data 0.082090 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.082090 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.082090 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.082090 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73250 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 73250 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74058.441558 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 74058.441558 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 73547.846890 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 73547.846890 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 73547.846890 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 73547.846890 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.082515 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.082515 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.082515 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.082515 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72524.436090 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 72524.436090 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74071.428571 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 74071.428571 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 73091.666667 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 73091.666667 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 73091.666667 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 73091.666667 # average overall miss latency
828,833c865,870
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 67 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 67 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 67 # number of overall MSHR hits
842,851c879,888
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5340000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5340000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5521500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5521500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10861500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10861500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10861500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10861500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040968 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040968 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287250 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287250 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5522500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5522500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10809750 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10809750 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10809750 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10809750 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040994 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040994 # mshr miss rate for ReadReq accesses
854,865c891,902
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.056167 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.056167 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80909.090909 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80909.090909 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71707.792208 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71707.792208 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75954.545455 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 75954.545455 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75954.545455 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 75954.545455 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056189 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.056189 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056189 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.056189 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80109.848485 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80109.848485 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71720.779221 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71720.779221 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75592.657343 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 75592.657343 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75592.657343 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 75592.657343 # average overall mshr miss latency