1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000020 # Number of seconds simulated
4sim_ticks 19639500 # Number of ticks simulated
5final_tick 19639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000020 # Number of seconds simulated
4sim_ticks 19639500 # Number of ticks simulated
5final_tick 19639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 30549 # Simulator instruction rate (inst/s)
8host_op_rate 55338 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 111488682 # Simulator tick rate (ticks/s)
10host_mem_usage 243516 # Number of bytes of host memory used
11host_seconds 0.18 # Real time elapsed on the host
| 7host_inst_rate 27608 # Simulator instruction rate (inst/s)
8host_op_rate 50013 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 100764572 # Simulator tick rate (ticks/s)
10host_mem_usage 247304 # Number of bytes of host memory used
11host_seconds 0.20 # Real time elapsed on the host
|
12sim_insts 5380 # Number of instructions simulated
13sim_ops 9747 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory
16system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 17536 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 17536 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 274 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 892894422 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 462740905 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 1355635327 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 892894422 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 892894422 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 892894422 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 462740905 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 1355635327 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 417 # Total number of read requests accepted by DRAM controller
31system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
32system.physmem.readBursts 417 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
33system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
34system.physmem.bytesRead 26624 # Total number of bytes read from memory
35system.physmem.bytesWritten 0 # Total number of bytes written to memory
36system.physmem.bytesConsumedRd 26624 # bytesRead derated as per pkt->getSize()
37system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
38system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
39system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
40system.physmem.perBankRdReqs::0 34 # Track reads on a per bank basis
41system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis
42system.physmem.perBankRdReqs::2 6 # Track reads on a per bank basis
43system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis
44system.physmem.perBankRdReqs::4 51 # Track reads on a per bank basis
45system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis
46system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::10 63 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::12 2 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::14 6 # Track reads on a per bank basis
55system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis
56system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
57system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
58system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
59system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
60system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
61system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
62system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
72system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
73system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
74system.physmem.totGap 19591000 # Total gap between requests
75system.physmem.readPktSize::0 0 # Categorize read packet sizes
76system.physmem.readPktSize::1 0 # Categorize read packet sizes
77system.physmem.readPktSize::2 0 # Categorize read packet sizes
78system.physmem.readPktSize::3 0 # Categorize read packet sizes
79system.physmem.readPktSize::4 0 # Categorize read packet sizes
80system.physmem.readPktSize::5 0 # Categorize read packet sizes
81system.physmem.readPktSize::6 417 # Categorize read packet sizes
82system.physmem.writePktSize::0 0 # Categorize write packet sizes
83system.physmem.writePktSize::1 0 # Categorize write packet sizes
84system.physmem.writePktSize::2 0 # Categorize write packet sizes
85system.physmem.writePktSize::3 0 # Categorize write packet sizes
86system.physmem.writePktSize::4 0 # Categorize write packet sizes
87system.physmem.writePktSize::5 0 # Categorize write packet sizes
88system.physmem.writePktSize::6 0 # Categorize write packet sizes
89system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see
90system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see
91system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
121system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
122system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
123system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
124system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
125system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
126system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
153system.physmem.bytesPerActivate::samples 88 # Bytes accessed per row activation
154system.physmem.bytesPerActivate::mean 216 # Bytes accessed per row activation
155system.physmem.bytesPerActivate::gmean 132.605669 # Bytes accessed per row activation
156system.physmem.bytesPerActivate::stdev 322.610045 # Bytes accessed per row activation
157system.physmem.bytesPerActivate::64 42 47.73% 47.73% # Bytes accessed per row activation
158system.physmem.bytesPerActivate::128 13 14.77% 62.50% # Bytes accessed per row activation
159system.physmem.bytesPerActivate::192 12 13.64% 76.14% # Bytes accessed per row activation
160system.physmem.bytesPerActivate::256 4 4.55% 80.68% # Bytes accessed per row activation
161system.physmem.bytesPerActivate::320 6 6.82% 87.50% # Bytes accessed per row activation
162system.physmem.bytesPerActivate::384 3 3.41% 90.91% # Bytes accessed per row activation
163system.physmem.bytesPerActivate::512 1 1.14% 92.05% # Bytes accessed per row activation
164system.physmem.bytesPerActivate::640 1 1.14% 93.18% # Bytes accessed per row activation
165system.physmem.bytesPerActivate::704 1 1.14% 94.32% # Bytes accessed per row activation
166system.physmem.bytesPerActivate::768 1 1.14% 95.45% # Bytes accessed per row activation
167system.physmem.bytesPerActivate::960 2 2.27% 97.73% # Bytes accessed per row activation
168system.physmem.bytesPerActivate::1344 1 1.14% 98.86% # Bytes accessed per row activation
169system.physmem.bytesPerActivate::2368 1 1.14% 100.00% # Bytes accessed per row activation
170system.physmem.bytesPerActivate::total 88 # Bytes accessed per row activation
171system.physmem.totQLat 1395750 # Total cycles spent in queuing delays
172system.physmem.totMemAccLat 11125750 # Sum of mem lat for all requests
173system.physmem.totBusLat 2085000 # Total cycles spent in databus access
174system.physmem.totBankLat 7645000 # Total cycles spent in bank access
175system.physmem.avgQLat 3347.12 # Average queueing delay per request
176system.physmem.avgBankLat 18333.33 # Average bank access latency per request
177system.physmem.avgBusLat 5000.00 # Average bus latency per request
178system.physmem.avgMemAccLat 26680.46 # Average memory access latency
179system.physmem.avgRdBW 1355.64 # Average achieved read bandwidth in MB/s
180system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
181system.physmem.avgConsumedRdBW 1355.64 # Average consumed read bandwidth in MB/s
182system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
183system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
184system.physmem.busUtil 10.59 # Data bus utilization in percentage
185system.physmem.avgRdQLen 0.57 # Average read queue length over time
186system.physmem.avgWrQLen 0.00 # Average write queue length over time
187system.physmem.readRowHits 329 # Number of row buffer hits during reads
188system.physmem.writeRowHits 0 # Number of row buffer hits during writes
189system.physmem.readRowHitRate 78.90 # Row buffer hit rate for reads
190system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
191system.physmem.avgGap 46980.82 # Average gap between requests
192system.membus.throughput 1355635327 # Throughput (bytes/s)
193system.membus.trans_dist::ReadReq 340 # Transaction distribution
194system.membus.trans_dist::ReadResp 339 # Transaction distribution
195system.membus.trans_dist::ReadExReq 77 # Transaction distribution
196system.membus.trans_dist::ReadExResp 77 # Transaction distribution
197system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes)
198system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes)
199system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes)
200system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
201system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
202system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
203system.membus.data_through_bus 26624 # Total data (bytes)
204system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
205system.membus.reqLayer0.occupancy 505500 # Layer occupancy (ticks)
206system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
207system.membus.respLayer1.occupancy 3891500 # Layer occupancy (ticks)
208system.membus.respLayer1.utilization 19.8 # Layer utilization (%)
209system.cpu.branchPred.lookups 3060 # Number of BP lookups
210system.cpu.branchPred.condPredicted 3060 # Number of conditional branches predicted
211system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect
212system.cpu.branchPred.BTBLookups 2257 # Number of BTB lookups
213system.cpu.branchPred.BTBHits 719 # Number of BTB hits
214system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
215system.cpu.branchPred.BTBHitPct 31.856447 # BTB Hit Percentage
216system.cpu.branchPred.usedRAS 208 # Number of times the RAS was used to get a target.
217system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions.
218system.cpu.workload.num_syscalls 11 # Number of system calls
219system.cpu.numCycles 39280 # number of cpu cycles simulated
220system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
221system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
222system.cpu.fetch.icacheStallCycles 10420 # Number of cycles fetch is stalled on an Icache miss
223system.cpu.fetch.Insts 14154 # Number of instructions fetch has processed
224system.cpu.fetch.Branches 3060 # Number of branches that fetch encountered
225system.cpu.fetch.predictedBranches 927 # Number of branches that fetch has predicted taken
226system.cpu.fetch.Cycles 3932 # Number of cycles fetch has run and was not squashing or blocked
227system.cpu.fetch.SquashCycles 2487 # Number of cycles fetch has spent squashing
228system.cpu.fetch.BlockedCycles 5289 # Number of cycles fetch has spent blocked
229system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
230system.cpu.fetch.PendingTrapStallCycles 384 # Number of stall cycles due to pending traps
231system.cpu.fetch.CacheLines 1977 # Number of cache lines fetched
232system.cpu.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed
233system.cpu.fetch.rateDist::samples 21952 # Number of instructions fetched each cycle (Total)
234system.cpu.fetch.rateDist::mean 1.145317 # Number of instructions fetched each cycle (Total)
235system.cpu.fetch.rateDist::stdev 2.661061 # Number of instructions fetched each cycle (Total)
236system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
237system.cpu.fetch.rateDist::0 18121 82.55% 82.55% # Number of instructions fetched each cycle (Total)
238system.cpu.fetch.rateDist::1 212 0.97% 83.51% # Number of instructions fetched each cycle (Total)
239system.cpu.fetch.rateDist::2 149 0.68% 84.19% # Number of instructions fetched each cycle (Total)
240system.cpu.fetch.rateDist::3 217 0.99% 85.18% # Number of instructions fetched each cycle (Total)
241system.cpu.fetch.rateDist::4 180 0.82% 86.00% # Number of instructions fetched each cycle (Total)
242system.cpu.fetch.rateDist::5 202 0.92% 86.92% # Number of instructions fetched each cycle (Total)
243system.cpu.fetch.rateDist::6 278 1.27% 88.19% # Number of instructions fetched each cycle (Total)
244system.cpu.fetch.rateDist::7 161 0.73% 88.92% # Number of instructions fetched each cycle (Total)
245system.cpu.fetch.rateDist::8 2432 11.08% 100.00% # Number of instructions fetched each cycle (Total)
246system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
247system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
248system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
249system.cpu.fetch.rateDist::total 21952 # Number of instructions fetched each cycle (Total)
250system.cpu.fetch.branchRate 0.077902 # Number of branch fetches per cycle
251system.cpu.fetch.rate 0.360336 # Number of inst fetches per cycle
252system.cpu.decode.IdleCycles 11197 # Number of cycles decode is idle
253system.cpu.decode.BlockedCycles 5173 # Number of cycles decode is blocked
254system.cpu.decode.RunCycles 3579 # Number of cycles decode is running
255system.cpu.decode.UnblockCycles 137 # Number of cycles decode is unblocking
256system.cpu.decode.SquashCycles 1866 # Number of cycles decode is squashing
257system.cpu.decode.DecodedInsts 24141 # Number of instructions handled by decode
258system.cpu.rename.SquashCycles 1866 # Number of cycles rename is squashing
259system.cpu.rename.IdleCycles 11552 # Number of cycles rename is idle
260system.cpu.rename.BlockCycles 3842 # Number of cycles rename is blocking
261system.cpu.rename.serializeStallCycles 569 # count of cycles rename stalled for serializing inst
262system.cpu.rename.RunCycles 3343 # Number of cycles rename is running
263system.cpu.rename.UnblockCycles 780 # Number of cycles rename is unblocking
264system.cpu.rename.RenamedInsts 22717 # Number of instructions processed by rename
265system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full
266system.cpu.rename.IQFullEvents 35 # Number of times rename has blocked due to IQ full
267system.cpu.rename.LSQFullEvents 666 # Number of times rename has blocked due to LSQ full
268system.cpu.rename.RenamedOperands 25267 # Number of destination operands rename has renamed
269system.cpu.rename.RenameLookups 55251 # Number of register rename lookups that rename has made
| 12sim_insts 5380 # Number of instructions simulated
13sim_ops 9747 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory
16system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 17536 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 17536 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 274 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 892894422 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 462740905 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 1355635327 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 892894422 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 892894422 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 892894422 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 462740905 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 1355635327 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 417 # Total number of read requests accepted by DRAM controller
31system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
32system.physmem.readBursts 417 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
33system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
34system.physmem.bytesRead 26624 # Total number of bytes read from memory
35system.physmem.bytesWritten 0 # Total number of bytes written to memory
36system.physmem.bytesConsumedRd 26624 # bytesRead derated as per pkt->getSize()
37system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
38system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
39system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
40system.physmem.perBankRdReqs::0 34 # Track reads on a per bank basis
41system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis
42system.physmem.perBankRdReqs::2 6 # Track reads on a per bank basis
43system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis
44system.physmem.perBankRdReqs::4 51 # Track reads on a per bank basis
45system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis
46system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::10 63 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::12 2 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::14 6 # Track reads on a per bank basis
55system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis
56system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
57system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
58system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
59system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
60system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
61system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
62system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
72system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
73system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
74system.physmem.totGap 19591000 # Total gap between requests
75system.physmem.readPktSize::0 0 # Categorize read packet sizes
76system.physmem.readPktSize::1 0 # Categorize read packet sizes
77system.physmem.readPktSize::2 0 # Categorize read packet sizes
78system.physmem.readPktSize::3 0 # Categorize read packet sizes
79system.physmem.readPktSize::4 0 # Categorize read packet sizes
80system.physmem.readPktSize::5 0 # Categorize read packet sizes
81system.physmem.readPktSize::6 417 # Categorize read packet sizes
82system.physmem.writePktSize::0 0 # Categorize write packet sizes
83system.physmem.writePktSize::1 0 # Categorize write packet sizes
84system.physmem.writePktSize::2 0 # Categorize write packet sizes
85system.physmem.writePktSize::3 0 # Categorize write packet sizes
86system.physmem.writePktSize::4 0 # Categorize write packet sizes
87system.physmem.writePktSize::5 0 # Categorize write packet sizes
88system.physmem.writePktSize::6 0 # Categorize write packet sizes
89system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see
90system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see
91system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
121system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
122system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
123system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
124system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
125system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
126system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
153system.physmem.bytesPerActivate::samples 88 # Bytes accessed per row activation
154system.physmem.bytesPerActivate::mean 216 # Bytes accessed per row activation
155system.physmem.bytesPerActivate::gmean 132.605669 # Bytes accessed per row activation
156system.physmem.bytesPerActivate::stdev 322.610045 # Bytes accessed per row activation
157system.physmem.bytesPerActivate::64 42 47.73% 47.73% # Bytes accessed per row activation
158system.physmem.bytesPerActivate::128 13 14.77% 62.50% # Bytes accessed per row activation
159system.physmem.bytesPerActivate::192 12 13.64% 76.14% # Bytes accessed per row activation
160system.physmem.bytesPerActivate::256 4 4.55% 80.68% # Bytes accessed per row activation
161system.physmem.bytesPerActivate::320 6 6.82% 87.50% # Bytes accessed per row activation
162system.physmem.bytesPerActivate::384 3 3.41% 90.91% # Bytes accessed per row activation
163system.physmem.bytesPerActivate::512 1 1.14% 92.05% # Bytes accessed per row activation
164system.physmem.bytesPerActivate::640 1 1.14% 93.18% # Bytes accessed per row activation
165system.physmem.bytesPerActivate::704 1 1.14% 94.32% # Bytes accessed per row activation
166system.physmem.bytesPerActivate::768 1 1.14% 95.45% # Bytes accessed per row activation
167system.physmem.bytesPerActivate::960 2 2.27% 97.73% # Bytes accessed per row activation
168system.physmem.bytesPerActivate::1344 1 1.14% 98.86% # Bytes accessed per row activation
169system.physmem.bytesPerActivate::2368 1 1.14% 100.00% # Bytes accessed per row activation
170system.physmem.bytesPerActivate::total 88 # Bytes accessed per row activation
171system.physmem.totQLat 1395750 # Total cycles spent in queuing delays
172system.physmem.totMemAccLat 11125750 # Sum of mem lat for all requests
173system.physmem.totBusLat 2085000 # Total cycles spent in databus access
174system.physmem.totBankLat 7645000 # Total cycles spent in bank access
175system.physmem.avgQLat 3347.12 # Average queueing delay per request
176system.physmem.avgBankLat 18333.33 # Average bank access latency per request
177system.physmem.avgBusLat 5000.00 # Average bus latency per request
178system.physmem.avgMemAccLat 26680.46 # Average memory access latency
179system.physmem.avgRdBW 1355.64 # Average achieved read bandwidth in MB/s
180system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
181system.physmem.avgConsumedRdBW 1355.64 # Average consumed read bandwidth in MB/s
182system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
183system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
184system.physmem.busUtil 10.59 # Data bus utilization in percentage
185system.physmem.avgRdQLen 0.57 # Average read queue length over time
186system.physmem.avgWrQLen 0.00 # Average write queue length over time
187system.physmem.readRowHits 329 # Number of row buffer hits during reads
188system.physmem.writeRowHits 0 # Number of row buffer hits during writes
189system.physmem.readRowHitRate 78.90 # Row buffer hit rate for reads
190system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
191system.physmem.avgGap 46980.82 # Average gap between requests
192system.membus.throughput 1355635327 # Throughput (bytes/s)
193system.membus.trans_dist::ReadReq 340 # Transaction distribution
194system.membus.trans_dist::ReadResp 339 # Transaction distribution
195system.membus.trans_dist::ReadExReq 77 # Transaction distribution
196system.membus.trans_dist::ReadExResp 77 # Transaction distribution
197system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes)
198system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes)
199system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes)
200system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
201system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
202system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
203system.membus.data_through_bus 26624 # Total data (bytes)
204system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
205system.membus.reqLayer0.occupancy 505500 # Layer occupancy (ticks)
206system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
207system.membus.respLayer1.occupancy 3891500 # Layer occupancy (ticks)
208system.membus.respLayer1.utilization 19.8 # Layer utilization (%)
209system.cpu.branchPred.lookups 3060 # Number of BP lookups
210system.cpu.branchPred.condPredicted 3060 # Number of conditional branches predicted
211system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect
212system.cpu.branchPred.BTBLookups 2257 # Number of BTB lookups
213system.cpu.branchPred.BTBHits 719 # Number of BTB hits
214system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
215system.cpu.branchPred.BTBHitPct 31.856447 # BTB Hit Percentage
216system.cpu.branchPred.usedRAS 208 # Number of times the RAS was used to get a target.
217system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions.
218system.cpu.workload.num_syscalls 11 # Number of system calls
219system.cpu.numCycles 39280 # number of cpu cycles simulated
220system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
221system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
222system.cpu.fetch.icacheStallCycles 10420 # Number of cycles fetch is stalled on an Icache miss
223system.cpu.fetch.Insts 14154 # Number of instructions fetch has processed
224system.cpu.fetch.Branches 3060 # Number of branches that fetch encountered
225system.cpu.fetch.predictedBranches 927 # Number of branches that fetch has predicted taken
226system.cpu.fetch.Cycles 3932 # Number of cycles fetch has run and was not squashing or blocked
227system.cpu.fetch.SquashCycles 2487 # Number of cycles fetch has spent squashing
228system.cpu.fetch.BlockedCycles 5289 # Number of cycles fetch has spent blocked
229system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
230system.cpu.fetch.PendingTrapStallCycles 384 # Number of stall cycles due to pending traps
231system.cpu.fetch.CacheLines 1977 # Number of cache lines fetched
232system.cpu.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed
233system.cpu.fetch.rateDist::samples 21952 # Number of instructions fetched each cycle (Total)
234system.cpu.fetch.rateDist::mean 1.145317 # Number of instructions fetched each cycle (Total)
235system.cpu.fetch.rateDist::stdev 2.661061 # Number of instructions fetched each cycle (Total)
236system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
237system.cpu.fetch.rateDist::0 18121 82.55% 82.55% # Number of instructions fetched each cycle (Total)
238system.cpu.fetch.rateDist::1 212 0.97% 83.51% # Number of instructions fetched each cycle (Total)
239system.cpu.fetch.rateDist::2 149 0.68% 84.19% # Number of instructions fetched each cycle (Total)
240system.cpu.fetch.rateDist::3 217 0.99% 85.18% # Number of instructions fetched each cycle (Total)
241system.cpu.fetch.rateDist::4 180 0.82% 86.00% # Number of instructions fetched each cycle (Total)
242system.cpu.fetch.rateDist::5 202 0.92% 86.92% # Number of instructions fetched each cycle (Total)
243system.cpu.fetch.rateDist::6 278 1.27% 88.19% # Number of instructions fetched each cycle (Total)
244system.cpu.fetch.rateDist::7 161 0.73% 88.92% # Number of instructions fetched each cycle (Total)
245system.cpu.fetch.rateDist::8 2432 11.08% 100.00% # Number of instructions fetched each cycle (Total)
246system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
247system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
248system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
249system.cpu.fetch.rateDist::total 21952 # Number of instructions fetched each cycle (Total)
250system.cpu.fetch.branchRate 0.077902 # Number of branch fetches per cycle
251system.cpu.fetch.rate 0.360336 # Number of inst fetches per cycle
252system.cpu.decode.IdleCycles 11197 # Number of cycles decode is idle
253system.cpu.decode.BlockedCycles 5173 # Number of cycles decode is blocked
254system.cpu.decode.RunCycles 3579 # Number of cycles decode is running
255system.cpu.decode.UnblockCycles 137 # Number of cycles decode is unblocking
256system.cpu.decode.SquashCycles 1866 # Number of cycles decode is squashing
257system.cpu.decode.DecodedInsts 24141 # Number of instructions handled by decode
258system.cpu.rename.SquashCycles 1866 # Number of cycles rename is squashing
259system.cpu.rename.IdleCycles 11552 # Number of cycles rename is idle
260system.cpu.rename.BlockCycles 3842 # Number of cycles rename is blocking
261system.cpu.rename.serializeStallCycles 569 # count of cycles rename stalled for serializing inst
262system.cpu.rename.RunCycles 3343 # Number of cycles rename is running
263system.cpu.rename.UnblockCycles 780 # Number of cycles rename is unblocking
264system.cpu.rename.RenamedInsts 22717 # Number of instructions processed by rename
265system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full
266system.cpu.rename.IQFullEvents 35 # Number of times rename has blocked due to IQ full
267system.cpu.rename.LSQFullEvents 666 # Number of times rename has blocked due to LSQ full
268system.cpu.rename.RenamedOperands 25267 # Number of destination operands rename has renamed
269system.cpu.rename.RenameLookups 55251 # Number of register rename lookups that rename has made
|
270system.cpu.rename.int_rename_lookups 55235 # Number of integer rename lookups
271system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
| 270system.cpu.rename.int_rename_lookups 31469 # Number of integer rename lookups
271system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
|
272system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed
273system.cpu.rename.UndoneMaps 14204 # Number of HB maps that are undone due to squashing
274system.cpu.rename.serializingInsts 30 # count of serializing insts renamed
275system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed
276system.cpu.rename.skidInsts 2015 # count of insts added to the skid buffer
277system.cpu.memDep0.insertedLoads 2290 # Number of loads inserted to the mem dependence unit.
278system.cpu.memDep0.insertedStores 1582 # Number of stores inserted to the mem dependence unit.
279system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
280system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
281system.cpu.iq.iqInstsAdded 20306 # Number of instructions added to the IQ (excludes non-spec)
282system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ
283system.cpu.iq.iqInstsIssued 17094 # Number of instructions issued
284system.cpu.iq.iqSquashedInstsIssued 292 # Number of squashed instructions issued
285system.cpu.iq.iqSquashedInstsExamined 9804 # Number of squashed instructions iterated over during squash; mainly for profiling
286system.cpu.iq.iqSquashedOperandsExamined 14093 # Number of squashed operands that are examined and possibly removed from graph
287system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
288system.cpu.iq.issued_per_cycle::samples 21952 # Number of insts issued each cycle
289system.cpu.iq.issued_per_cycle::mean 0.778699 # Number of insts issued each cycle
290system.cpu.iq.issued_per_cycle::stdev 1.655311 # Number of insts issued each cycle
291system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
292system.cpu.iq.issued_per_cycle::0 16455 74.96% 74.96% # Number of insts issued each cycle
293system.cpu.iq.issued_per_cycle::1 1544 7.03% 81.99% # Number of insts issued each cycle
294system.cpu.iq.issued_per_cycle::2 1078 4.91% 86.90% # Number of insts issued each cycle
295system.cpu.iq.issued_per_cycle::3 728 3.32% 90.22% # Number of insts issued each cycle
296system.cpu.iq.issued_per_cycle::4 707 3.22% 93.44% # Number of insts issued each cycle
297system.cpu.iq.issued_per_cycle::5 584 2.66% 96.10% # Number of insts issued each cycle
298system.cpu.iq.issued_per_cycle::6 572 2.61% 98.71% # Number of insts issued each cycle
299system.cpu.iq.issued_per_cycle::7 242 1.10% 99.81% # Number of insts issued each cycle
300system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle
301system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
302system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
303system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
304system.cpu.iq.issued_per_cycle::total 21952 # Number of insts issued each cycle
305system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
306system.cpu.iq.fu_full::IntAlu 143 77.72% 77.72% # attempts to use FU when none available
307system.cpu.iq.fu_full::IntMult 0 0.00% 77.72% # attempts to use FU when none available
308system.cpu.iq.fu_full::IntDiv 0 0.00% 77.72% # attempts to use FU when none available
309system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.72% # attempts to use FU when none available
310system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.72% # attempts to use FU when none available
311system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.72% # attempts to use FU when none available
312system.cpu.iq.fu_full::FloatMult 0 0.00% 77.72% # attempts to use FU when none available
313system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.72% # attempts to use FU when none available
314system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.72% # attempts to use FU when none available
315system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.72% # attempts to use FU when none available
316system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.72% # attempts to use FU when none available
317system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.72% # attempts to use FU when none available
318system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.72% # attempts to use FU when none available
319system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.72% # attempts to use FU when none available
320system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.72% # attempts to use FU when none available
321system.cpu.iq.fu_full::SimdMult 0 0.00% 77.72% # attempts to use FU when none available
322system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.72% # attempts to use FU when none available
323system.cpu.iq.fu_full::SimdShift 0 0.00% 77.72% # attempts to use FU when none available
324system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.72% # attempts to use FU when none available
325system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.72% # attempts to use FU when none available
326system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.72% # attempts to use FU when none available
327system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.72% # attempts to use FU when none available
328system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.72% # attempts to use FU when none available
329system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.72% # attempts to use FU when none available
330system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.72% # attempts to use FU when none available
331system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.72% # attempts to use FU when none available
332system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.72% # attempts to use FU when none available
333system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.72% # attempts to use FU when none available
334system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.72% # attempts to use FU when none available
335system.cpu.iq.fu_full::MemRead 26 14.13% 91.85% # attempts to use FU when none available
336system.cpu.iq.fu_full::MemWrite 15 8.15% 100.00% # attempts to use FU when none available
337system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
338system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
339system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
340system.cpu.iq.FU_type_0::IntAlu 13719 80.26% 80.27% # Type of FU issued
341system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.30% # Type of FU issued
342system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.34% # Type of FU issued
343system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.34% # Type of FU issued
344system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.34% # Type of FU issued
345system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.34% # Type of FU issued
346system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.34% # Type of FU issued
347system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.34% # Type of FU issued
348system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.34% # Type of FU issued
349system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.34% # Type of FU issued
350system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.34% # Type of FU issued
351system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.34% # Type of FU issued
352system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.34% # Type of FU issued
353system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.34% # Type of FU issued
354system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.34% # Type of FU issued
355system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.34% # Type of FU issued
356system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.34% # Type of FU issued
357system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.34% # Type of FU issued
358system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.34% # Type of FU issued
359system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.34% # Type of FU issued
360system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.34% # Type of FU issued
361system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.34% # Type of FU issued
362system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.34% # Type of FU issued
363system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.34% # Type of FU issued
364system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.34% # Type of FU issued
365system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.34% # Type of FU issued
366system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.34% # Type of FU issued
367system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.34% # Type of FU issued
368system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.34% # Type of FU issued
369system.cpu.iq.FU_type_0::MemRead 1979 11.58% 91.92% # Type of FU issued
370system.cpu.iq.FU_type_0::MemWrite 1382 8.08% 100.00% # Type of FU issued
371system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
372system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
373system.cpu.iq.FU_type_0::total 17094 # Type of FU issued
374system.cpu.iq.rate 0.435183 # Inst issue rate
375system.cpu.iq.fu_busy_cnt 184 # FU busy when requested
376system.cpu.iq.fu_busy_rate 0.010764 # FU busy rate (busy events/executed inst)
377system.cpu.iq.int_inst_queue_reads 56608 # Number of integer instruction queue reads
378system.cpu.iq.int_inst_queue_writes 30145 # Number of integer instruction queue writes
379system.cpu.iq.int_inst_queue_wakeup_accesses 15699 # Number of integer instruction queue wakeup accesses
380system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
381system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
382system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
383system.cpu.iq.int_alu_accesses 17271 # Number of integer alu accesses
384system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
385system.cpu.iew.lsq.thread0.forwLoads 170 # Number of loads that had data forwarded from stores
386system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
387system.cpu.iew.lsq.thread0.squashedLoads 1237 # Number of loads squashed
388system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
389system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
390system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed
391system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
392system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
393system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
394system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked
395system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
396system.cpu.iew.iewSquashCycles 1866 # Number of cycles IEW is squashing
397system.cpu.iew.iewBlockCycles 3033 # Number of cycles IEW is blocking
398system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking
399system.cpu.iew.iewDispatchedInsts 20334 # Number of instructions dispatched to IQ
400system.cpu.iew.iewDispSquashedInsts 50 # Number of squashed instructions skipped by dispatch
401system.cpu.iew.iewDispLoadInsts 2290 # Number of dispatched load instructions
402system.cpu.iew.iewDispStoreInsts 1582 # Number of dispatched store instructions
403system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions
404system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
405system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
406system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
407system.cpu.iew.predictedTakenIncorrect 113 # Number of branches that were predicted taken incorrectly
408system.cpu.iew.predictedNotTakenIncorrect 578 # Number of branches that were predicted not taken incorrectly
409system.cpu.iew.branchMispredicts 691 # Number of branch mispredicts detected at execute
410system.cpu.iew.iewExecutedInsts 16182 # Number of executed instructions
411system.cpu.iew.iewExecLoadInsts 1848 # Number of load instructions executed
412system.cpu.iew.iewExecSquashedInsts 912 # Number of squashed instructions skipped in execute
413system.cpu.iew.exec_swp 0 # number of swp insts executed
414system.cpu.iew.exec_nop 0 # number of nop insts executed
415system.cpu.iew.exec_refs 3125 # number of memory reference insts executed
416system.cpu.iew.exec_branches 1615 # Number of branches executed
417system.cpu.iew.exec_stores 1277 # Number of stores executed
418system.cpu.iew.exec_rate 0.411965 # Inst execution rate
419system.cpu.iew.wb_sent 15923 # cumulative count of insts sent to commit
420system.cpu.iew.wb_count 15703 # cumulative count of insts written-back
421system.cpu.iew.wb_producers 10139 # num instructions producing a value
422system.cpu.iew.wb_consumers 15623 # num instructions consuming a value
423system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
424system.cpu.iew.wb_rate 0.399771 # insts written-back per cycle
425system.cpu.iew.wb_fanout 0.648979 # average fanout of values written-back
426system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
427system.cpu.commit.commitSquashedInsts 10598 # The number of squashed insts skipped by commit
428system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
429system.cpu.commit.branchMispredicts 599 # The number of times a branch was mispredicted
430system.cpu.commit.committed_per_cycle::samples 20086 # Number of insts commited each cycle
431system.cpu.commit.committed_per_cycle::mean 0.485263 # Number of insts commited each cycle
432system.cpu.commit.committed_per_cycle::stdev 1.340827 # Number of insts commited each cycle
433system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
434system.cpu.commit.committed_per_cycle::0 16512 82.21% 82.21% # Number of insts commited each cycle
435system.cpu.commit.committed_per_cycle::1 1365 6.80% 89.00% # Number of insts commited each cycle
436system.cpu.commit.committed_per_cycle::2 596 2.97% 91.97% # Number of insts commited each cycle
437system.cpu.commit.committed_per_cycle::3 708 3.52% 95.49% # Number of insts commited each cycle
438system.cpu.commit.committed_per_cycle::4 362 1.80% 97.30% # Number of insts commited each cycle
439system.cpu.commit.committed_per_cycle::5 137 0.68% 97.98% # Number of insts commited each cycle
440system.cpu.commit.committed_per_cycle::6 121 0.60% 98.58% # Number of insts commited each cycle
441system.cpu.commit.committed_per_cycle::7 73 0.36% 98.94% # Number of insts commited each cycle
442system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Number of insts commited each cycle
443system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
444system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
445system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
446system.cpu.commit.committed_per_cycle::total 20086 # Number of insts commited each cycle
447system.cpu.commit.committedInsts 5380 # Number of instructions committed
448system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed
449system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
450system.cpu.commit.refs 1988 # Number of memory references committed
451system.cpu.commit.loads 1053 # Number of loads committed
452system.cpu.commit.membars 0 # Number of memory barriers committed
453system.cpu.commit.branches 1208 # Number of branches committed
454system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
| 272system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed
273system.cpu.rename.UndoneMaps 14204 # Number of HB maps that are undone due to squashing
274system.cpu.rename.serializingInsts 30 # count of serializing insts renamed
275system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed
276system.cpu.rename.skidInsts 2015 # count of insts added to the skid buffer
277system.cpu.memDep0.insertedLoads 2290 # Number of loads inserted to the mem dependence unit.
278system.cpu.memDep0.insertedStores 1582 # Number of stores inserted to the mem dependence unit.
279system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
280system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
281system.cpu.iq.iqInstsAdded 20306 # Number of instructions added to the IQ (excludes non-spec)
282system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ
283system.cpu.iq.iqInstsIssued 17094 # Number of instructions issued
284system.cpu.iq.iqSquashedInstsIssued 292 # Number of squashed instructions issued
285system.cpu.iq.iqSquashedInstsExamined 9804 # Number of squashed instructions iterated over during squash; mainly for profiling
286system.cpu.iq.iqSquashedOperandsExamined 14093 # Number of squashed operands that are examined and possibly removed from graph
287system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
288system.cpu.iq.issued_per_cycle::samples 21952 # Number of insts issued each cycle
289system.cpu.iq.issued_per_cycle::mean 0.778699 # Number of insts issued each cycle
290system.cpu.iq.issued_per_cycle::stdev 1.655311 # Number of insts issued each cycle
291system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
292system.cpu.iq.issued_per_cycle::0 16455 74.96% 74.96% # Number of insts issued each cycle
293system.cpu.iq.issued_per_cycle::1 1544 7.03% 81.99% # Number of insts issued each cycle
294system.cpu.iq.issued_per_cycle::2 1078 4.91% 86.90% # Number of insts issued each cycle
295system.cpu.iq.issued_per_cycle::3 728 3.32% 90.22% # Number of insts issued each cycle
296system.cpu.iq.issued_per_cycle::4 707 3.22% 93.44% # Number of insts issued each cycle
297system.cpu.iq.issued_per_cycle::5 584 2.66% 96.10% # Number of insts issued each cycle
298system.cpu.iq.issued_per_cycle::6 572 2.61% 98.71% # Number of insts issued each cycle
299system.cpu.iq.issued_per_cycle::7 242 1.10% 99.81% # Number of insts issued each cycle
300system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle
301system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
302system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
303system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
304system.cpu.iq.issued_per_cycle::total 21952 # Number of insts issued each cycle
305system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
306system.cpu.iq.fu_full::IntAlu 143 77.72% 77.72% # attempts to use FU when none available
307system.cpu.iq.fu_full::IntMult 0 0.00% 77.72% # attempts to use FU when none available
308system.cpu.iq.fu_full::IntDiv 0 0.00% 77.72% # attempts to use FU when none available
309system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.72% # attempts to use FU when none available
310system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.72% # attempts to use FU when none available
311system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.72% # attempts to use FU when none available
312system.cpu.iq.fu_full::FloatMult 0 0.00% 77.72% # attempts to use FU when none available
313system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.72% # attempts to use FU when none available
314system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.72% # attempts to use FU when none available
315system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.72% # attempts to use FU when none available
316system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.72% # attempts to use FU when none available
317system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.72% # attempts to use FU when none available
318system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.72% # attempts to use FU when none available
319system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.72% # attempts to use FU when none available
320system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.72% # attempts to use FU when none available
321system.cpu.iq.fu_full::SimdMult 0 0.00% 77.72% # attempts to use FU when none available
322system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.72% # attempts to use FU when none available
323system.cpu.iq.fu_full::SimdShift 0 0.00% 77.72% # attempts to use FU when none available
324system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.72% # attempts to use FU when none available
325system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.72% # attempts to use FU when none available
326system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.72% # attempts to use FU when none available
327system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.72% # attempts to use FU when none available
328system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.72% # attempts to use FU when none available
329system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.72% # attempts to use FU when none available
330system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.72% # attempts to use FU when none available
331system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.72% # attempts to use FU when none available
332system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.72% # attempts to use FU when none available
333system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.72% # attempts to use FU when none available
334system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.72% # attempts to use FU when none available
335system.cpu.iq.fu_full::MemRead 26 14.13% 91.85% # attempts to use FU when none available
336system.cpu.iq.fu_full::MemWrite 15 8.15% 100.00% # attempts to use FU when none available
337system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
338system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
339system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
340system.cpu.iq.FU_type_0::IntAlu 13719 80.26% 80.27% # Type of FU issued
341system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.30% # Type of FU issued
342system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.34% # Type of FU issued
343system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.34% # Type of FU issued
344system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.34% # Type of FU issued
345system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.34% # Type of FU issued
346system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.34% # Type of FU issued
347system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.34% # Type of FU issued
348system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.34% # Type of FU issued
349system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.34% # Type of FU issued
350system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.34% # Type of FU issued
351system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.34% # Type of FU issued
352system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.34% # Type of FU issued
353system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.34% # Type of FU issued
354system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.34% # Type of FU issued
355system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.34% # Type of FU issued
356system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.34% # Type of FU issued
357system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.34% # Type of FU issued
358system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.34% # Type of FU issued
359system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.34% # Type of FU issued
360system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.34% # Type of FU issued
361system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.34% # Type of FU issued
362system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.34% # Type of FU issued
363system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.34% # Type of FU issued
364system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.34% # Type of FU issued
365system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.34% # Type of FU issued
366system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.34% # Type of FU issued
367system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.34% # Type of FU issued
368system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.34% # Type of FU issued
369system.cpu.iq.FU_type_0::MemRead 1979 11.58% 91.92% # Type of FU issued
370system.cpu.iq.FU_type_0::MemWrite 1382 8.08% 100.00% # Type of FU issued
371system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
372system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
373system.cpu.iq.FU_type_0::total 17094 # Type of FU issued
374system.cpu.iq.rate 0.435183 # Inst issue rate
375system.cpu.iq.fu_busy_cnt 184 # FU busy when requested
376system.cpu.iq.fu_busy_rate 0.010764 # FU busy rate (busy events/executed inst)
377system.cpu.iq.int_inst_queue_reads 56608 # Number of integer instruction queue reads
378system.cpu.iq.int_inst_queue_writes 30145 # Number of integer instruction queue writes
379system.cpu.iq.int_inst_queue_wakeup_accesses 15699 # Number of integer instruction queue wakeup accesses
380system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
381system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
382system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
383system.cpu.iq.int_alu_accesses 17271 # Number of integer alu accesses
384system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
385system.cpu.iew.lsq.thread0.forwLoads 170 # Number of loads that had data forwarded from stores
386system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
387system.cpu.iew.lsq.thread0.squashedLoads 1237 # Number of loads squashed
388system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
389system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
390system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed
391system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
392system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
393system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
394system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked
395system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
396system.cpu.iew.iewSquashCycles 1866 # Number of cycles IEW is squashing
397system.cpu.iew.iewBlockCycles 3033 # Number of cycles IEW is blocking
398system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking
399system.cpu.iew.iewDispatchedInsts 20334 # Number of instructions dispatched to IQ
400system.cpu.iew.iewDispSquashedInsts 50 # Number of squashed instructions skipped by dispatch
401system.cpu.iew.iewDispLoadInsts 2290 # Number of dispatched load instructions
402system.cpu.iew.iewDispStoreInsts 1582 # Number of dispatched store instructions
403system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions
404system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
405system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
406system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
407system.cpu.iew.predictedTakenIncorrect 113 # Number of branches that were predicted taken incorrectly
408system.cpu.iew.predictedNotTakenIncorrect 578 # Number of branches that were predicted not taken incorrectly
409system.cpu.iew.branchMispredicts 691 # Number of branch mispredicts detected at execute
410system.cpu.iew.iewExecutedInsts 16182 # Number of executed instructions
411system.cpu.iew.iewExecLoadInsts 1848 # Number of load instructions executed
412system.cpu.iew.iewExecSquashedInsts 912 # Number of squashed instructions skipped in execute
413system.cpu.iew.exec_swp 0 # number of swp insts executed
414system.cpu.iew.exec_nop 0 # number of nop insts executed
415system.cpu.iew.exec_refs 3125 # number of memory reference insts executed
416system.cpu.iew.exec_branches 1615 # Number of branches executed
417system.cpu.iew.exec_stores 1277 # Number of stores executed
418system.cpu.iew.exec_rate 0.411965 # Inst execution rate
419system.cpu.iew.wb_sent 15923 # cumulative count of insts sent to commit
420system.cpu.iew.wb_count 15703 # cumulative count of insts written-back
421system.cpu.iew.wb_producers 10139 # num instructions producing a value
422system.cpu.iew.wb_consumers 15623 # num instructions consuming a value
423system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
424system.cpu.iew.wb_rate 0.399771 # insts written-back per cycle
425system.cpu.iew.wb_fanout 0.648979 # average fanout of values written-back
426system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
427system.cpu.commit.commitSquashedInsts 10598 # The number of squashed insts skipped by commit
428system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
429system.cpu.commit.branchMispredicts 599 # The number of times a branch was mispredicted
430system.cpu.commit.committed_per_cycle::samples 20086 # Number of insts commited each cycle
431system.cpu.commit.committed_per_cycle::mean 0.485263 # Number of insts commited each cycle
432system.cpu.commit.committed_per_cycle::stdev 1.340827 # Number of insts commited each cycle
433system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
434system.cpu.commit.committed_per_cycle::0 16512 82.21% 82.21% # Number of insts commited each cycle
435system.cpu.commit.committed_per_cycle::1 1365 6.80% 89.00% # Number of insts commited each cycle
436system.cpu.commit.committed_per_cycle::2 596 2.97% 91.97% # Number of insts commited each cycle
437system.cpu.commit.committed_per_cycle::3 708 3.52% 95.49% # Number of insts commited each cycle
438system.cpu.commit.committed_per_cycle::4 362 1.80% 97.30% # Number of insts commited each cycle
439system.cpu.commit.committed_per_cycle::5 137 0.68% 97.98% # Number of insts commited each cycle
440system.cpu.commit.committed_per_cycle::6 121 0.60% 98.58% # Number of insts commited each cycle
441system.cpu.commit.committed_per_cycle::7 73 0.36% 98.94% # Number of insts commited each cycle
442system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Number of insts commited each cycle
443system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
444system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
445system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
446system.cpu.commit.committed_per_cycle::total 20086 # Number of insts commited each cycle
447system.cpu.commit.committedInsts 5380 # Number of instructions committed
448system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed
449system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
450system.cpu.commit.refs 1988 # Number of memory references committed
451system.cpu.commit.loads 1053 # Number of loads committed
452system.cpu.commit.membars 0 # Number of memory barriers committed
453system.cpu.commit.branches 1208 # Number of branches committed
454system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
455system.cpu.commit.int_insts 9654 # Number of committed integer instructions.
| 455system.cpu.commit.int_insts 9653 # Number of committed integer instructions.
|
456system.cpu.commit.function_calls 106 # Number of function calls committed.
457system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached
458system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
459system.cpu.rob.rob_reads 40219 # The number of ROB reads
460system.cpu.rob.rob_writes 42582 # The number of ROB writes
461system.cpu.timesIdled 167 # Number of times that the entire CPU went into an idle state and unscheduled itself
462system.cpu.idleCycles 17328 # Total number of cycles that the CPU has spent unscheduled due to idling
463system.cpu.committedInsts 5380 # Number of Instructions Simulated
464system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
465system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
466system.cpu.cpi 7.301115 # CPI: Cycles Per Instruction
467system.cpu.cpi_total 7.301115 # CPI: Total CPI of All Threads
468system.cpu.ipc 0.136965 # IPC: Instructions Per Cycle
469system.cpu.ipc_total 0.136965 # IPC: Total IPC of All Threads
| 456system.cpu.commit.function_calls 106 # Number of function calls committed.
457system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached
458system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
459system.cpu.rob.rob_reads 40219 # The number of ROB reads
460system.cpu.rob.rob_writes 42582 # The number of ROB writes
461system.cpu.timesIdled 167 # Number of times that the entire CPU went into an idle state and unscheduled itself
462system.cpu.idleCycles 17328 # Total number of cycles that the CPU has spent unscheduled due to idling
463system.cpu.committedInsts 5380 # Number of Instructions Simulated
464system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
465system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
466system.cpu.cpi 7.301115 # CPI: Cycles Per Instruction
467system.cpu.cpi_total 7.301115 # CPI: Total CPI of All Threads
468system.cpu.ipc 0.136965 # IPC: Instructions Per Cycle
469system.cpu.ipc_total 0.136965 # IPC: Total IPC of All Threads
|
470system.cpu.int_regfile_reads 28824 # number of integer regfile reads
471system.cpu.int_regfile_writes 17237 # number of integer regfile writes
| 470system.cpu.int_regfile_reads 20780 # number of integer regfile reads
471system.cpu.int_regfile_writes 12385 # number of integer regfile writes
|
472system.cpu.fp_regfile_reads 4 # number of floating regfile reads
| 472system.cpu.fp_regfile_reads 4 # number of floating regfile reads
|
| 473system.cpu.cc_regfile_reads 8044 # number of cc regfile reads
474system.cpu.cc_regfile_writes 4852 # number of cc regfile writes
|
473system.cpu.misc_regfile_reads 7122 # number of misc regfile reads
474system.cpu.misc_regfile_writes 1 # number of misc regfile writes
475system.cpu.toL2Bus.throughput 1362152804 # Throughput (bytes/s)
476system.cpu.toL2Bus.trans_dist::ReadReq 342 # Transaction distribution
477system.cpu.toL2Bus.trans_dist::ReadResp 341 # Transaction distribution
478system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution
479system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution
480system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550 # Packet count per connected master and slave (bytes)
481system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes)
482system.cpu.toL2Bus.pkt_count::total 837 # Packet count per connected master and slave (bytes)
483system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes)
484system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes)
485system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
486system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes)
487system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
488system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks)
489system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
490system.cpu.toL2Bus.respLayer0.occupancy 463250 # Layer occupancy (ticks)
491system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
492system.cpu.toL2Bus.respLayer1.occupancy 239750 # Layer occupancy (ticks)
493system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
494system.cpu.icache.tags.replacements 0 # number of replacements
495system.cpu.icache.tags.tagsinuse 130.740950 # Cycle average of tags in use
496system.cpu.icache.tags.total_refs 1608 # Total number of references to valid blocks.
497system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks.
498system.cpu.icache.tags.avg_refs 5.847273 # Average number of references to valid blocks.
499system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
500system.cpu.icache.tags.occ_blocks::cpu.inst 130.740950 # Average occupied blocks per requestor
501system.cpu.icache.tags.occ_percent::cpu.inst 0.063838 # Average percentage of cache occupancy
502system.cpu.icache.tags.occ_percent::total 0.063838 # Average percentage of cache occupancy
503system.cpu.icache.ReadReq_hits::cpu.inst 1608 # number of ReadReq hits
504system.cpu.icache.ReadReq_hits::total 1608 # number of ReadReq hits
505system.cpu.icache.demand_hits::cpu.inst 1608 # number of demand (read+write) hits
506system.cpu.icache.demand_hits::total 1608 # number of demand (read+write) hits
507system.cpu.icache.overall_hits::cpu.inst 1608 # number of overall hits
508system.cpu.icache.overall_hits::total 1608 # number of overall hits
509system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses
510system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses
511system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses
512system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses
513system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses
514system.cpu.icache.overall_misses::total 369 # number of overall misses
515system.cpu.icache.ReadReq_miss_latency::cpu.inst 24439500 # number of ReadReq miss cycles
516system.cpu.icache.ReadReq_miss_latency::total 24439500 # number of ReadReq miss cycles
517system.cpu.icache.demand_miss_latency::cpu.inst 24439500 # number of demand (read+write) miss cycles
518system.cpu.icache.demand_miss_latency::total 24439500 # number of demand (read+write) miss cycles
519system.cpu.icache.overall_miss_latency::cpu.inst 24439500 # number of overall miss cycles
520system.cpu.icache.overall_miss_latency::total 24439500 # number of overall miss cycles
521system.cpu.icache.ReadReq_accesses::cpu.inst 1977 # number of ReadReq accesses(hits+misses)
522system.cpu.icache.ReadReq_accesses::total 1977 # number of ReadReq accesses(hits+misses)
523system.cpu.icache.demand_accesses::cpu.inst 1977 # number of demand (read+write) accesses
524system.cpu.icache.demand_accesses::total 1977 # number of demand (read+write) accesses
525system.cpu.icache.overall_accesses::cpu.inst 1977 # number of overall (read+write) accesses
526system.cpu.icache.overall_accesses::total 1977 # number of overall (read+write) accesses
527system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186646 # miss rate for ReadReq accesses
528system.cpu.icache.ReadReq_miss_rate::total 0.186646 # miss rate for ReadReq accesses
529system.cpu.icache.demand_miss_rate::cpu.inst 0.186646 # miss rate for demand accesses
530system.cpu.icache.demand_miss_rate::total 0.186646 # miss rate for demand accesses
531system.cpu.icache.overall_miss_rate::cpu.inst 0.186646 # miss rate for overall accesses
532system.cpu.icache.overall_miss_rate::total 0.186646 # miss rate for overall accesses
533system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66231.707317 # average ReadReq miss latency
534system.cpu.icache.ReadReq_avg_miss_latency::total 66231.707317 # average ReadReq miss latency
535system.cpu.icache.demand_avg_miss_latency::cpu.inst 66231.707317 # average overall miss latency
536system.cpu.icache.demand_avg_miss_latency::total 66231.707317 # average overall miss latency
537system.cpu.icache.overall_avg_miss_latency::cpu.inst 66231.707317 # average overall miss latency
538system.cpu.icache.overall_avg_miss_latency::total 66231.707317 # average overall miss latency
539system.cpu.icache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked
540system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
541system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
542system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
543system.cpu.icache.avg_blocked_cycles::no_mshrs 70 # average number of cycles each access was blocked
544system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
545system.cpu.icache.fast_writes 0 # number of fast writes performed
546system.cpu.icache.cache_copies 0 # number of cache copies performed
547system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits
548system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits
549system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits
550system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits
551system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits
552system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits
553system.cpu.icache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses
554system.cpu.icache.ReadReq_mshr_misses::total 275 # number of ReadReq MSHR misses
555system.cpu.icache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses
556system.cpu.icache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses
557system.cpu.icache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses
558system.cpu.icache.overall_mshr_misses::total 275 # number of overall MSHR misses
559system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19054250 # number of ReadReq MSHR miss cycles
560system.cpu.icache.ReadReq_mshr_miss_latency::total 19054250 # number of ReadReq MSHR miss cycles
561system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19054250 # number of demand (read+write) MSHR miss cycles
562system.cpu.icache.demand_mshr_miss_latency::total 19054250 # number of demand (read+write) MSHR miss cycles
563system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19054250 # number of overall MSHR miss cycles
564system.cpu.icache.overall_mshr_miss_latency::total 19054250 # number of overall MSHR miss cycles
565system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.139100 # mshr miss rate for ReadReq accesses
566system.cpu.icache.ReadReq_mshr_miss_rate::total 0.139100 # mshr miss rate for ReadReq accesses
567system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.139100 # mshr miss rate for demand accesses
568system.cpu.icache.demand_mshr_miss_rate::total 0.139100 # mshr miss rate for demand accesses
569system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.139100 # mshr miss rate for overall accesses
570system.cpu.icache.overall_mshr_miss_rate::total 0.139100 # mshr miss rate for overall accesses
571system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69288.181818 # average ReadReq mshr miss latency
572system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69288.181818 # average ReadReq mshr miss latency
573system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69288.181818 # average overall mshr miss latency
574system.cpu.icache.demand_avg_mshr_miss_latency::total 69288.181818 # average overall mshr miss latency
575system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69288.181818 # average overall mshr miss latency
576system.cpu.icache.overall_avg_mshr_miss_latency::total 69288.181818 # average overall mshr miss latency
577system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
578system.cpu.l2cache.tags.replacements 0 # number of replacements
579system.cpu.l2cache.tags.tagsinuse 163.561658 # Cycle average of tags in use
580system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
581system.cpu.l2cache.tags.sampled_refs 339 # Sample count of references to valid blocks.
582system.cpu.l2cache.tags.avg_refs 0.005900 # Average number of references to valid blocks.
583system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
584system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.812999 # Average occupied blocks per requestor
585system.cpu.l2cache.tags.occ_blocks::cpu.data 32.748659 # Average occupied blocks per requestor
586system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003992 # Average percentage of cache occupancy
587system.cpu.l2cache.tags.occ_percent::cpu.data 0.000999 # Average percentage of cache occupancy
588system.cpu.l2cache.tags.occ_percent::total 0.004992 # Average percentage of cache occupancy
589system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
590system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
591system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
592system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
593system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
594system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
595system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
596system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
597system.cpu.l2cache.overall_hits::total 2 # number of overall hits
598system.cpu.l2cache.ReadReq_misses::cpu.inst 274 # number of ReadReq misses
599system.cpu.l2cache.ReadReq_misses::cpu.data 66 # number of ReadReq misses
600system.cpu.l2cache.ReadReq_misses::total 340 # number of ReadReq misses
601system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses
602system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses
603system.cpu.l2cache.demand_misses::cpu.inst 274 # number of demand (read+write) misses
604system.cpu.l2cache.demand_misses::cpu.data 143 # number of demand (read+write) misses
605system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses
606system.cpu.l2cache.overall_misses::cpu.inst 274 # number of overall misses
607system.cpu.l2cache.overall_misses::cpu.data 143 # number of overall misses
608system.cpu.l2cache.overall_misses::total 417 # number of overall misses
609system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18767750 # number of ReadReq miss cycles
610system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5075750 # number of ReadReq miss cycles
611system.cpu.l2cache.ReadReq_miss_latency::total 23843500 # number of ReadReq miss cycles
612system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5461000 # number of ReadExReq miss cycles
613system.cpu.l2cache.ReadExReq_miss_latency::total 5461000 # number of ReadExReq miss cycles
614system.cpu.l2cache.demand_miss_latency::cpu.inst 18767750 # number of demand (read+write) miss cycles
615system.cpu.l2cache.demand_miss_latency::cpu.data 10536750 # number of demand (read+write) miss cycles
616system.cpu.l2cache.demand_miss_latency::total 29304500 # number of demand (read+write) miss cycles
617system.cpu.l2cache.overall_miss_latency::cpu.inst 18767750 # number of overall miss cycles
618system.cpu.l2cache.overall_miss_latency::cpu.data 10536750 # number of overall miss cycles
619system.cpu.l2cache.overall_miss_latency::total 29304500 # number of overall miss cycles
620system.cpu.l2cache.ReadReq_accesses::cpu.inst 275 # number of ReadReq accesses(hits+misses)
621system.cpu.l2cache.ReadReq_accesses::cpu.data 67 # number of ReadReq accesses(hits+misses)
622system.cpu.l2cache.ReadReq_accesses::total 342 # number of ReadReq accesses(hits+misses)
623system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses)
624system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses)
625system.cpu.l2cache.demand_accesses::cpu.inst 275 # number of demand (read+write) accesses
626system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses
627system.cpu.l2cache.demand_accesses::total 419 # number of demand (read+write) accesses
628system.cpu.l2cache.overall_accesses::cpu.inst 275 # number of overall (read+write) accesses
629system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses
630system.cpu.l2cache.overall_accesses::total 419 # number of overall (read+write) accesses
631system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996364 # miss rate for ReadReq accesses
632system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.985075 # miss rate for ReadReq accesses
633system.cpu.l2cache.ReadReq_miss_rate::total 0.994152 # miss rate for ReadReq accesses
634system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
635system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
636system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996364 # miss rate for demand accesses
637system.cpu.l2cache.demand_miss_rate::cpu.data 0.993056 # miss rate for demand accesses
638system.cpu.l2cache.demand_miss_rate::total 0.995227 # miss rate for demand accesses
639system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996364 # miss rate for overall accesses
640system.cpu.l2cache.overall_miss_rate::cpu.data 0.993056 # miss rate for overall accesses
641system.cpu.l2cache.overall_miss_rate::total 0.995227 # miss rate for overall accesses
642system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68495.437956 # average ReadReq miss latency
643system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76905.303030 # average ReadReq miss latency
644system.cpu.l2cache.ReadReq_avg_miss_latency::total 70127.941176 # average ReadReq miss latency
645system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70922.077922 # average ReadExReq miss latency
646system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70922.077922 # average ReadExReq miss latency
647system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68495.437956 # average overall miss latency
648system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73683.566434 # average overall miss latency
649system.cpu.l2cache.demand_avg_miss_latency::total 70274.580336 # average overall miss latency
650system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68495.437956 # average overall miss latency
651system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73683.566434 # average overall miss latency
652system.cpu.l2cache.overall_avg_miss_latency::total 70274.580336 # average overall miss latency
653system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
654system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
655system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
656system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
657system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
658system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
659system.cpu.l2cache.fast_writes 0 # number of fast writes performed
660system.cpu.l2cache.cache_copies 0 # number of cache copies performed
661system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses
662system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses
663system.cpu.l2cache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses
664system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses
665system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses
666system.cpu.l2cache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses
667system.cpu.l2cache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses
668system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses
669system.cpu.l2cache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses
670system.cpu.l2cache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses
671system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses
672system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15323250 # number of ReadReq MSHR miss cycles
673system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4265250 # number of ReadReq MSHR miss cycles
674system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19588500 # number of ReadReq MSHR miss cycles
675system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4500500 # number of ReadExReq MSHR miss cycles
676system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4500500 # number of ReadExReq MSHR miss cycles
677system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15323250 # number of demand (read+write) MSHR miss cycles
678system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8765750 # number of demand (read+write) MSHR miss cycles
679system.cpu.l2cache.demand_mshr_miss_latency::total 24089000 # number of demand (read+write) MSHR miss cycles
680system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15323250 # number of overall MSHR miss cycles
681system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8765750 # number of overall MSHR miss cycles
682system.cpu.l2cache.overall_mshr_miss_latency::total 24089000 # number of overall MSHR miss cycles
683system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for ReadReq accesses
684system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.985075 # mshr miss rate for ReadReq accesses
685system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994152 # mshr miss rate for ReadReq accesses
686system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
687system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
688system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for demand accesses
689system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for demand accesses
690system.cpu.l2cache.demand_mshr_miss_rate::total 0.995227 # mshr miss rate for demand accesses
691system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for overall accesses
692system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for overall accesses
693system.cpu.l2cache.overall_mshr_miss_rate::total 0.995227 # mshr miss rate for overall accesses
694system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55924.270073 # average ReadReq mshr miss latency
695system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64625 # average ReadReq mshr miss latency
696system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57613.235294 # average ReadReq mshr miss latency
697system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58448.051948 # average ReadExReq mshr miss latency
698system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58448.051948 # average ReadExReq mshr miss latency
699system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55924.270073 # average overall mshr miss latency
700system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency
701system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency
702system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55924.270073 # average overall mshr miss latency
703system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency
704system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency
705system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
706system.cpu.dcache.tags.replacements 0 # number of replacements
707system.cpu.dcache.tags.tagsinuse 82.722336 # Cycle average of tags in use
708system.cpu.dcache.tags.total_refs 2341 # Total number of references to valid blocks.
709system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks.
710system.cpu.dcache.tags.avg_refs 16.370629 # Average number of references to valid blocks.
711system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
712system.cpu.dcache.tags.occ_blocks::cpu.data 82.722336 # Average occupied blocks per requestor
713system.cpu.dcache.tags.occ_percent::cpu.data 0.020196 # Average percentage of cache occupancy
714system.cpu.dcache.tags.occ_percent::total 0.020196 # Average percentage of cache occupancy
715system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits
716system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits
717system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
718system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
719system.cpu.dcache.demand_hits::cpu.data 2341 # number of demand (read+write) hits
720system.cpu.dcache.demand_hits::total 2341 # number of demand (read+write) hits
721system.cpu.dcache.overall_hits::cpu.data 2341 # number of overall hits
722system.cpu.dcache.overall_hits::total 2341 # number of overall hits
723system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses
724system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses
725system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses
726system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses
727system.cpu.dcache.demand_misses::cpu.data 210 # number of demand (read+write) misses
728system.cpu.dcache.demand_misses::total 210 # number of demand (read+write) misses
729system.cpu.dcache.overall_misses::cpu.data 210 # number of overall misses
730system.cpu.dcache.overall_misses::total 210 # number of overall misses
731system.cpu.dcache.ReadReq_miss_latency::cpu.data 9610000 # number of ReadReq miss cycles
732system.cpu.dcache.ReadReq_miss_latency::total 9610000 # number of ReadReq miss cycles
733system.cpu.dcache.WriteReq_miss_latency::cpu.data 5723000 # number of WriteReq miss cycles
734system.cpu.dcache.WriteReq_miss_latency::total 5723000 # number of WriteReq miss cycles
735system.cpu.dcache.demand_miss_latency::cpu.data 15333000 # number of demand (read+write) miss cycles
736system.cpu.dcache.demand_miss_latency::total 15333000 # number of demand (read+write) miss cycles
737system.cpu.dcache.overall_miss_latency::cpu.data 15333000 # number of overall miss cycles
738system.cpu.dcache.overall_miss_latency::total 15333000 # number of overall miss cycles
739system.cpu.dcache.ReadReq_accesses::cpu.data 1616 # number of ReadReq accesses(hits+misses)
740system.cpu.dcache.ReadReq_accesses::total 1616 # number of ReadReq accesses(hits+misses)
741system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
742system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
743system.cpu.dcache.demand_accesses::cpu.data 2551 # number of demand (read+write) accesses
744system.cpu.dcache.demand_accesses::total 2551 # number of demand (read+write) accesses
745system.cpu.dcache.overall_accesses::cpu.data 2551 # number of overall (read+write) accesses
746system.cpu.dcache.overall_accesses::total 2551 # number of overall (read+write) accesses
747system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082302 # miss rate for ReadReq accesses
748system.cpu.dcache.ReadReq_miss_rate::total 0.082302 # miss rate for ReadReq accesses
749system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses
750system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses
751system.cpu.dcache.demand_miss_rate::cpu.data 0.082321 # miss rate for demand accesses
752system.cpu.dcache.demand_miss_rate::total 0.082321 # miss rate for demand accesses
753system.cpu.dcache.overall_miss_rate::cpu.data 0.082321 # miss rate for overall accesses
754system.cpu.dcache.overall_miss_rate::total 0.082321 # miss rate for overall accesses
755system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72255.639098 # average ReadReq miss latency
756system.cpu.dcache.ReadReq_avg_miss_latency::total 72255.639098 # average ReadReq miss latency
757system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74324.675325 # average WriteReq miss latency
758system.cpu.dcache.WriteReq_avg_miss_latency::total 74324.675325 # average WriteReq miss latency
759system.cpu.dcache.demand_avg_miss_latency::cpu.data 73014.285714 # average overall miss latency
760system.cpu.dcache.demand_avg_miss_latency::total 73014.285714 # average overall miss latency
761system.cpu.dcache.overall_avg_miss_latency::cpu.data 73014.285714 # average overall miss latency
762system.cpu.dcache.overall_avg_miss_latency::total 73014.285714 # average overall miss latency
763system.cpu.dcache.blocked_cycles::no_mshrs 163 # number of cycles access was blocked
764system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
765system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
766system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
767system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.333333 # average number of cycles each access was blocked
768system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
769system.cpu.dcache.fast_writes 0 # number of fast writes performed
770system.cpu.dcache.cache_copies 0 # number of cache copies performed
771system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits
772system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
773system.cpu.dcache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits
774system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits
775system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits
776system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits
777system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses
778system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses
779system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses
780system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses
781system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses
782system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses
783system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses
784system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses
785system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5151750 # number of ReadReq MSHR miss cycles
786system.cpu.dcache.ReadReq_mshr_miss_latency::total 5151750 # number of ReadReq MSHR miss cycles
787system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5538000 # number of WriteReq MSHR miss cycles
788system.cpu.dcache.WriteReq_mshr_miss_latency::total 5538000 # number of WriteReq MSHR miss cycles
789system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10689750 # number of demand (read+write) MSHR miss cycles
790system.cpu.dcache.demand_mshr_miss_latency::total 10689750 # number of demand (read+write) MSHR miss cycles
791system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10689750 # number of overall MSHR miss cycles
792system.cpu.dcache.overall_mshr_miss_latency::total 10689750 # number of overall MSHR miss cycles
793system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041460 # mshr miss rate for ReadReq accesses
794system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041460 # mshr miss rate for ReadReq accesses
795system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses
796system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses
797system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for demand accesses
798system.cpu.dcache.demand_mshr_miss_rate::total 0.056448 # mshr miss rate for demand accesses
799system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for overall accesses
800system.cpu.dcache.overall_mshr_miss_rate::total 0.056448 # mshr miss rate for overall accesses
801system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76891.791045 # average ReadReq mshr miss latency
802system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76891.791045 # average ReadReq mshr miss latency
803system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71922.077922 # average WriteReq mshr miss latency
804system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71922.077922 # average WriteReq mshr miss latency
805system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency
806system.cpu.dcache.demand_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency
807system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency
808system.cpu.dcache.overall_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency
809system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
810
811---------- End Simulation Statistics ----------
| 475system.cpu.misc_regfile_reads 7122 # number of misc regfile reads
476system.cpu.misc_regfile_writes 1 # number of misc regfile writes
477system.cpu.toL2Bus.throughput 1362152804 # Throughput (bytes/s)
478system.cpu.toL2Bus.trans_dist::ReadReq 342 # Transaction distribution
479system.cpu.toL2Bus.trans_dist::ReadResp 341 # Transaction distribution
480system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution
481system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution
482system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550 # Packet count per connected master and slave (bytes)
483system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes)
484system.cpu.toL2Bus.pkt_count::total 837 # Packet count per connected master and slave (bytes)
485system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes)
486system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes)
487system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
488system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes)
489system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
490system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks)
491system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
492system.cpu.toL2Bus.respLayer0.occupancy 463250 # Layer occupancy (ticks)
493system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
494system.cpu.toL2Bus.respLayer1.occupancy 239750 # Layer occupancy (ticks)
495system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
496system.cpu.icache.tags.replacements 0 # number of replacements
497system.cpu.icache.tags.tagsinuse 130.740950 # Cycle average of tags in use
498system.cpu.icache.tags.total_refs 1608 # Total number of references to valid blocks.
499system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks.
500system.cpu.icache.tags.avg_refs 5.847273 # Average number of references to valid blocks.
501system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
502system.cpu.icache.tags.occ_blocks::cpu.inst 130.740950 # Average occupied blocks per requestor
503system.cpu.icache.tags.occ_percent::cpu.inst 0.063838 # Average percentage of cache occupancy
504system.cpu.icache.tags.occ_percent::total 0.063838 # Average percentage of cache occupancy
505system.cpu.icache.ReadReq_hits::cpu.inst 1608 # number of ReadReq hits
506system.cpu.icache.ReadReq_hits::total 1608 # number of ReadReq hits
507system.cpu.icache.demand_hits::cpu.inst 1608 # number of demand (read+write) hits
508system.cpu.icache.demand_hits::total 1608 # number of demand (read+write) hits
509system.cpu.icache.overall_hits::cpu.inst 1608 # number of overall hits
510system.cpu.icache.overall_hits::total 1608 # number of overall hits
511system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses
512system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses
513system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses
514system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses
515system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses
516system.cpu.icache.overall_misses::total 369 # number of overall misses
517system.cpu.icache.ReadReq_miss_latency::cpu.inst 24439500 # number of ReadReq miss cycles
518system.cpu.icache.ReadReq_miss_latency::total 24439500 # number of ReadReq miss cycles
519system.cpu.icache.demand_miss_latency::cpu.inst 24439500 # number of demand (read+write) miss cycles
520system.cpu.icache.demand_miss_latency::total 24439500 # number of demand (read+write) miss cycles
521system.cpu.icache.overall_miss_latency::cpu.inst 24439500 # number of overall miss cycles
522system.cpu.icache.overall_miss_latency::total 24439500 # number of overall miss cycles
523system.cpu.icache.ReadReq_accesses::cpu.inst 1977 # number of ReadReq accesses(hits+misses)
524system.cpu.icache.ReadReq_accesses::total 1977 # number of ReadReq accesses(hits+misses)
525system.cpu.icache.demand_accesses::cpu.inst 1977 # number of demand (read+write) accesses
526system.cpu.icache.demand_accesses::total 1977 # number of demand (read+write) accesses
527system.cpu.icache.overall_accesses::cpu.inst 1977 # number of overall (read+write) accesses
528system.cpu.icache.overall_accesses::total 1977 # number of overall (read+write) accesses
529system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186646 # miss rate for ReadReq accesses
530system.cpu.icache.ReadReq_miss_rate::total 0.186646 # miss rate for ReadReq accesses
531system.cpu.icache.demand_miss_rate::cpu.inst 0.186646 # miss rate for demand accesses
532system.cpu.icache.demand_miss_rate::total 0.186646 # miss rate for demand accesses
533system.cpu.icache.overall_miss_rate::cpu.inst 0.186646 # miss rate for overall accesses
534system.cpu.icache.overall_miss_rate::total 0.186646 # miss rate for overall accesses
535system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66231.707317 # average ReadReq miss latency
536system.cpu.icache.ReadReq_avg_miss_latency::total 66231.707317 # average ReadReq miss latency
537system.cpu.icache.demand_avg_miss_latency::cpu.inst 66231.707317 # average overall miss latency
538system.cpu.icache.demand_avg_miss_latency::total 66231.707317 # average overall miss latency
539system.cpu.icache.overall_avg_miss_latency::cpu.inst 66231.707317 # average overall miss latency
540system.cpu.icache.overall_avg_miss_latency::total 66231.707317 # average overall miss latency
541system.cpu.icache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked
542system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
543system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
544system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
545system.cpu.icache.avg_blocked_cycles::no_mshrs 70 # average number of cycles each access was blocked
546system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
547system.cpu.icache.fast_writes 0 # number of fast writes performed
548system.cpu.icache.cache_copies 0 # number of cache copies performed
549system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits
550system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits
551system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits
552system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits
553system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits
554system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits
555system.cpu.icache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses
556system.cpu.icache.ReadReq_mshr_misses::total 275 # number of ReadReq MSHR misses
557system.cpu.icache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses
558system.cpu.icache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses
559system.cpu.icache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses
560system.cpu.icache.overall_mshr_misses::total 275 # number of overall MSHR misses
561system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19054250 # number of ReadReq MSHR miss cycles
562system.cpu.icache.ReadReq_mshr_miss_latency::total 19054250 # number of ReadReq MSHR miss cycles
563system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19054250 # number of demand (read+write) MSHR miss cycles
564system.cpu.icache.demand_mshr_miss_latency::total 19054250 # number of demand (read+write) MSHR miss cycles
565system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19054250 # number of overall MSHR miss cycles
566system.cpu.icache.overall_mshr_miss_latency::total 19054250 # number of overall MSHR miss cycles
567system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.139100 # mshr miss rate for ReadReq accesses
568system.cpu.icache.ReadReq_mshr_miss_rate::total 0.139100 # mshr miss rate for ReadReq accesses
569system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.139100 # mshr miss rate for demand accesses
570system.cpu.icache.demand_mshr_miss_rate::total 0.139100 # mshr miss rate for demand accesses
571system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.139100 # mshr miss rate for overall accesses
572system.cpu.icache.overall_mshr_miss_rate::total 0.139100 # mshr miss rate for overall accesses
573system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69288.181818 # average ReadReq mshr miss latency
574system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69288.181818 # average ReadReq mshr miss latency
575system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69288.181818 # average overall mshr miss latency
576system.cpu.icache.demand_avg_mshr_miss_latency::total 69288.181818 # average overall mshr miss latency
577system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69288.181818 # average overall mshr miss latency
578system.cpu.icache.overall_avg_mshr_miss_latency::total 69288.181818 # average overall mshr miss latency
579system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
580system.cpu.l2cache.tags.replacements 0 # number of replacements
581system.cpu.l2cache.tags.tagsinuse 163.561658 # Cycle average of tags in use
582system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
583system.cpu.l2cache.tags.sampled_refs 339 # Sample count of references to valid blocks.
584system.cpu.l2cache.tags.avg_refs 0.005900 # Average number of references to valid blocks.
585system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
586system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.812999 # Average occupied blocks per requestor
587system.cpu.l2cache.tags.occ_blocks::cpu.data 32.748659 # Average occupied blocks per requestor
588system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003992 # Average percentage of cache occupancy
589system.cpu.l2cache.tags.occ_percent::cpu.data 0.000999 # Average percentage of cache occupancy
590system.cpu.l2cache.tags.occ_percent::total 0.004992 # Average percentage of cache occupancy
591system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
592system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
593system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
594system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
595system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
596system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
597system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
598system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
599system.cpu.l2cache.overall_hits::total 2 # number of overall hits
600system.cpu.l2cache.ReadReq_misses::cpu.inst 274 # number of ReadReq misses
601system.cpu.l2cache.ReadReq_misses::cpu.data 66 # number of ReadReq misses
602system.cpu.l2cache.ReadReq_misses::total 340 # number of ReadReq misses
603system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses
604system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses
605system.cpu.l2cache.demand_misses::cpu.inst 274 # number of demand (read+write) misses
606system.cpu.l2cache.demand_misses::cpu.data 143 # number of demand (read+write) misses
607system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses
608system.cpu.l2cache.overall_misses::cpu.inst 274 # number of overall misses
609system.cpu.l2cache.overall_misses::cpu.data 143 # number of overall misses
610system.cpu.l2cache.overall_misses::total 417 # number of overall misses
611system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18767750 # number of ReadReq miss cycles
612system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5075750 # number of ReadReq miss cycles
613system.cpu.l2cache.ReadReq_miss_latency::total 23843500 # number of ReadReq miss cycles
614system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5461000 # number of ReadExReq miss cycles
615system.cpu.l2cache.ReadExReq_miss_latency::total 5461000 # number of ReadExReq miss cycles
616system.cpu.l2cache.demand_miss_latency::cpu.inst 18767750 # number of demand (read+write) miss cycles
617system.cpu.l2cache.demand_miss_latency::cpu.data 10536750 # number of demand (read+write) miss cycles
618system.cpu.l2cache.demand_miss_latency::total 29304500 # number of demand (read+write) miss cycles
619system.cpu.l2cache.overall_miss_latency::cpu.inst 18767750 # number of overall miss cycles
620system.cpu.l2cache.overall_miss_latency::cpu.data 10536750 # number of overall miss cycles
621system.cpu.l2cache.overall_miss_latency::total 29304500 # number of overall miss cycles
622system.cpu.l2cache.ReadReq_accesses::cpu.inst 275 # number of ReadReq accesses(hits+misses)
623system.cpu.l2cache.ReadReq_accesses::cpu.data 67 # number of ReadReq accesses(hits+misses)
624system.cpu.l2cache.ReadReq_accesses::total 342 # number of ReadReq accesses(hits+misses)
625system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses)
626system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses)
627system.cpu.l2cache.demand_accesses::cpu.inst 275 # number of demand (read+write) accesses
628system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses
629system.cpu.l2cache.demand_accesses::total 419 # number of demand (read+write) accesses
630system.cpu.l2cache.overall_accesses::cpu.inst 275 # number of overall (read+write) accesses
631system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses
632system.cpu.l2cache.overall_accesses::total 419 # number of overall (read+write) accesses
633system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996364 # miss rate for ReadReq accesses
634system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.985075 # miss rate for ReadReq accesses
635system.cpu.l2cache.ReadReq_miss_rate::total 0.994152 # miss rate for ReadReq accesses
636system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
637system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
638system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996364 # miss rate for demand accesses
639system.cpu.l2cache.demand_miss_rate::cpu.data 0.993056 # miss rate for demand accesses
640system.cpu.l2cache.demand_miss_rate::total 0.995227 # miss rate for demand accesses
641system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996364 # miss rate for overall accesses
642system.cpu.l2cache.overall_miss_rate::cpu.data 0.993056 # miss rate for overall accesses
643system.cpu.l2cache.overall_miss_rate::total 0.995227 # miss rate for overall accesses
644system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68495.437956 # average ReadReq miss latency
645system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76905.303030 # average ReadReq miss latency
646system.cpu.l2cache.ReadReq_avg_miss_latency::total 70127.941176 # average ReadReq miss latency
647system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70922.077922 # average ReadExReq miss latency
648system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70922.077922 # average ReadExReq miss latency
649system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68495.437956 # average overall miss latency
650system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73683.566434 # average overall miss latency
651system.cpu.l2cache.demand_avg_miss_latency::total 70274.580336 # average overall miss latency
652system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68495.437956 # average overall miss latency
653system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73683.566434 # average overall miss latency
654system.cpu.l2cache.overall_avg_miss_latency::total 70274.580336 # average overall miss latency
655system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
656system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
657system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
658system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
659system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
660system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
661system.cpu.l2cache.fast_writes 0 # number of fast writes performed
662system.cpu.l2cache.cache_copies 0 # number of cache copies performed
663system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses
664system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses
665system.cpu.l2cache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses
666system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses
667system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses
668system.cpu.l2cache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses
669system.cpu.l2cache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses
670system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses
671system.cpu.l2cache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses
672system.cpu.l2cache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses
673system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses
674system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15323250 # number of ReadReq MSHR miss cycles
675system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4265250 # number of ReadReq MSHR miss cycles
676system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19588500 # number of ReadReq MSHR miss cycles
677system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4500500 # number of ReadExReq MSHR miss cycles
678system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4500500 # number of ReadExReq MSHR miss cycles
679system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15323250 # number of demand (read+write) MSHR miss cycles
680system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8765750 # number of demand (read+write) MSHR miss cycles
681system.cpu.l2cache.demand_mshr_miss_latency::total 24089000 # number of demand (read+write) MSHR miss cycles
682system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15323250 # number of overall MSHR miss cycles
683system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8765750 # number of overall MSHR miss cycles
684system.cpu.l2cache.overall_mshr_miss_latency::total 24089000 # number of overall MSHR miss cycles
685system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for ReadReq accesses
686system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.985075 # mshr miss rate for ReadReq accesses
687system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994152 # mshr miss rate for ReadReq accesses
688system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
689system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
690system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for demand accesses
691system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for demand accesses
692system.cpu.l2cache.demand_mshr_miss_rate::total 0.995227 # mshr miss rate for demand accesses
693system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for overall accesses
694system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for overall accesses
695system.cpu.l2cache.overall_mshr_miss_rate::total 0.995227 # mshr miss rate for overall accesses
696system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55924.270073 # average ReadReq mshr miss latency
697system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64625 # average ReadReq mshr miss latency
698system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57613.235294 # average ReadReq mshr miss latency
699system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58448.051948 # average ReadExReq mshr miss latency
700system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58448.051948 # average ReadExReq mshr miss latency
701system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55924.270073 # average overall mshr miss latency
702system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency
703system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency
704system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55924.270073 # average overall mshr miss latency
705system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency
706system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency
707system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
708system.cpu.dcache.tags.replacements 0 # number of replacements
709system.cpu.dcache.tags.tagsinuse 82.722336 # Cycle average of tags in use
710system.cpu.dcache.tags.total_refs 2341 # Total number of references to valid blocks.
711system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks.
712system.cpu.dcache.tags.avg_refs 16.370629 # Average number of references to valid blocks.
713system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
714system.cpu.dcache.tags.occ_blocks::cpu.data 82.722336 # Average occupied blocks per requestor
715system.cpu.dcache.tags.occ_percent::cpu.data 0.020196 # Average percentage of cache occupancy
716system.cpu.dcache.tags.occ_percent::total 0.020196 # Average percentage of cache occupancy
717system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits
718system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits
719system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
720system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
721system.cpu.dcache.demand_hits::cpu.data 2341 # number of demand (read+write) hits
722system.cpu.dcache.demand_hits::total 2341 # number of demand (read+write) hits
723system.cpu.dcache.overall_hits::cpu.data 2341 # number of overall hits
724system.cpu.dcache.overall_hits::total 2341 # number of overall hits
725system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses
726system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses
727system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses
728system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses
729system.cpu.dcache.demand_misses::cpu.data 210 # number of demand (read+write) misses
730system.cpu.dcache.demand_misses::total 210 # number of demand (read+write) misses
731system.cpu.dcache.overall_misses::cpu.data 210 # number of overall misses
732system.cpu.dcache.overall_misses::total 210 # number of overall misses
733system.cpu.dcache.ReadReq_miss_latency::cpu.data 9610000 # number of ReadReq miss cycles
734system.cpu.dcache.ReadReq_miss_latency::total 9610000 # number of ReadReq miss cycles
735system.cpu.dcache.WriteReq_miss_latency::cpu.data 5723000 # number of WriteReq miss cycles
736system.cpu.dcache.WriteReq_miss_latency::total 5723000 # number of WriteReq miss cycles
737system.cpu.dcache.demand_miss_latency::cpu.data 15333000 # number of demand (read+write) miss cycles
738system.cpu.dcache.demand_miss_latency::total 15333000 # number of demand (read+write) miss cycles
739system.cpu.dcache.overall_miss_latency::cpu.data 15333000 # number of overall miss cycles
740system.cpu.dcache.overall_miss_latency::total 15333000 # number of overall miss cycles
741system.cpu.dcache.ReadReq_accesses::cpu.data 1616 # number of ReadReq accesses(hits+misses)
742system.cpu.dcache.ReadReq_accesses::total 1616 # number of ReadReq accesses(hits+misses)
743system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
744system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
745system.cpu.dcache.demand_accesses::cpu.data 2551 # number of demand (read+write) accesses
746system.cpu.dcache.demand_accesses::total 2551 # number of demand (read+write) accesses
747system.cpu.dcache.overall_accesses::cpu.data 2551 # number of overall (read+write) accesses
748system.cpu.dcache.overall_accesses::total 2551 # number of overall (read+write) accesses
749system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082302 # miss rate for ReadReq accesses
750system.cpu.dcache.ReadReq_miss_rate::total 0.082302 # miss rate for ReadReq accesses
751system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses
752system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses
753system.cpu.dcache.demand_miss_rate::cpu.data 0.082321 # miss rate for demand accesses
754system.cpu.dcache.demand_miss_rate::total 0.082321 # miss rate for demand accesses
755system.cpu.dcache.overall_miss_rate::cpu.data 0.082321 # miss rate for overall accesses
756system.cpu.dcache.overall_miss_rate::total 0.082321 # miss rate for overall accesses
757system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72255.639098 # average ReadReq miss latency
758system.cpu.dcache.ReadReq_avg_miss_latency::total 72255.639098 # average ReadReq miss latency
759system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74324.675325 # average WriteReq miss latency
760system.cpu.dcache.WriteReq_avg_miss_latency::total 74324.675325 # average WriteReq miss latency
761system.cpu.dcache.demand_avg_miss_latency::cpu.data 73014.285714 # average overall miss latency
762system.cpu.dcache.demand_avg_miss_latency::total 73014.285714 # average overall miss latency
763system.cpu.dcache.overall_avg_miss_latency::cpu.data 73014.285714 # average overall miss latency
764system.cpu.dcache.overall_avg_miss_latency::total 73014.285714 # average overall miss latency
765system.cpu.dcache.blocked_cycles::no_mshrs 163 # number of cycles access was blocked
766system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
767system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
768system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
769system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.333333 # average number of cycles each access was blocked
770system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
771system.cpu.dcache.fast_writes 0 # number of fast writes performed
772system.cpu.dcache.cache_copies 0 # number of cache copies performed
773system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits
774system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
775system.cpu.dcache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits
776system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits
777system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits
778system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits
779system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses
780system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses
781system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses
782system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses
783system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses
784system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses
785system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses
786system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses
787system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5151750 # number of ReadReq MSHR miss cycles
788system.cpu.dcache.ReadReq_mshr_miss_latency::total 5151750 # number of ReadReq MSHR miss cycles
789system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5538000 # number of WriteReq MSHR miss cycles
790system.cpu.dcache.WriteReq_mshr_miss_latency::total 5538000 # number of WriteReq MSHR miss cycles
791system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10689750 # number of demand (read+write) MSHR miss cycles
792system.cpu.dcache.demand_mshr_miss_latency::total 10689750 # number of demand (read+write) MSHR miss cycles
793system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10689750 # number of overall MSHR miss cycles
794system.cpu.dcache.overall_mshr_miss_latency::total 10689750 # number of overall MSHR miss cycles
795system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041460 # mshr miss rate for ReadReq accesses
796system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041460 # mshr miss rate for ReadReq accesses
797system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses
798system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses
799system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for demand accesses
800system.cpu.dcache.demand_mshr_miss_rate::total 0.056448 # mshr miss rate for demand accesses
801system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for overall accesses
802system.cpu.dcache.overall_mshr_miss_rate::total 0.056448 # mshr miss rate for overall accesses
803system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76891.791045 # average ReadReq mshr miss latency
804system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76891.791045 # average ReadReq mshr miss latency
805system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71922.077922 # average WriteReq mshr miss latency
806system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71922.077922 # average WriteReq mshr miss latency
807system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency
808system.cpu.dcache.demand_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency
809system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency
810system.cpu.dcache.overall_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency
811system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
812
813---------- End Simulation Statistics ----------
|