1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000022 # Number of seconds simulated
4sim_ticks 22466500 # Number of ticks simulated
5final_tick 22466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000022 # Number of seconds simulated
4sim_ticks 22466500 # Number of ticks simulated
5final_tick 22466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 32079 # Simulator instruction rate (inst/s)
8host_op_rate 58113 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 133941475 # Simulator tick rate (ticks/s)
10host_mem_usage 269032 # Number of bytes of host memory used
11host_seconds 0.17 # Real time elapsed on the host
| 7host_inst_rate 70304 # Simulator instruction rate (inst/s)
8host_op_rate 127350 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 293494415 # Simulator tick rate (ticks/s)
10host_mem_usage 271256 # Number of bytes of host memory used
11host_seconds 0.08 # Real time elapsed on the host
|
12sim_insts 5380 # Number of instructions simulated
13sim_ops 9747 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
19system.physmem.bytes_read::total 26752 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 418 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 789085972 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 401664701 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 1190750673 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 789085972 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 789085972 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 789085972 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 401664701 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 1190750673 # Total bandwidth to/from this memory (bytes/s)
33system.physmem.readReqs 418 # Number of read requests accepted
34system.physmem.writeReqs 0 # Number of write requests accepted
35system.physmem.readBursts 418 # Number of DRAM read bursts, including those serviced by the write queue
36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
37system.physmem.bytesReadDRAM 26752 # Total number of bytes read from DRAM
38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
40system.physmem.bytesReadSys 26752 # Total read bytes from the system interface side
41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
45system.physmem.perBankRdBursts::0 32 # Per bank write bursts
46system.physmem.perBankRdBursts::1 1 # Per bank write bursts
47system.physmem.perBankRdBursts::2 5 # Per bank write bursts
48system.physmem.perBankRdBursts::3 8 # Per bank write bursts
49system.physmem.perBankRdBursts::4 50 # Per bank write bursts
50system.physmem.perBankRdBursts::5 44 # Per bank write bursts
51system.physmem.perBankRdBursts::6 21 # Per bank write bursts
52system.physmem.perBankRdBursts::7 37 # Per bank write bursts
53system.physmem.perBankRdBursts::8 24 # Per bank write bursts
54system.physmem.perBankRdBursts::9 71 # Per bank write bursts
55system.physmem.perBankRdBursts::10 64 # Per bank write bursts
56system.physmem.perBankRdBursts::11 16 # Per bank write bursts
57system.physmem.perBankRdBursts::12 2 # Per bank write bursts
58system.physmem.perBankRdBursts::13 20 # Per bank write bursts
59system.physmem.perBankRdBursts::14 6 # Per bank write bursts
60system.physmem.perBankRdBursts::15 17 # Per bank write bursts
61system.physmem.perBankWrBursts::0 0 # Per bank write bursts
62system.physmem.perBankWrBursts::1 0 # Per bank write bursts
63system.physmem.perBankWrBursts::2 0 # Per bank write bursts
64system.physmem.perBankWrBursts::3 0 # Per bank write bursts
65system.physmem.perBankWrBursts::4 0 # Per bank write bursts
66system.physmem.perBankWrBursts::5 0 # Per bank write bursts
67system.physmem.perBankWrBursts::6 0 # Per bank write bursts
68system.physmem.perBankWrBursts::7 0 # Per bank write bursts
69system.physmem.perBankWrBursts::8 0 # Per bank write bursts
70system.physmem.perBankWrBursts::9 0 # Per bank write bursts
71system.physmem.perBankWrBursts::10 0 # Per bank write bursts
72system.physmem.perBankWrBursts::11 0 # Per bank write bursts
73system.physmem.perBankWrBursts::12 0 # Per bank write bursts
74system.physmem.perBankWrBursts::13 0 # Per bank write bursts
75system.physmem.perBankWrBursts::14 0 # Per bank write bursts
76system.physmem.perBankWrBursts::15 0 # Per bank write bursts
77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
79system.physmem.totGap 22337000 # Total gap between requests
80system.physmem.readPktSize::0 0 # Read request sizes (log2)
81system.physmem.readPktSize::1 0 # Read request sizes (log2)
82system.physmem.readPktSize::2 0 # Read request sizes (log2)
83system.physmem.readPktSize::3 0 # Read request sizes (log2)
84system.physmem.readPktSize::4 0 # Read request sizes (log2)
85system.physmem.readPktSize::5 0 # Read request sizes (log2)
86system.physmem.readPktSize::6 418 # Read request sizes (log2)
87system.physmem.writePktSize::0 0 # Write request sizes (log2)
88system.physmem.writePktSize::1 0 # Write request sizes (log2)
89system.physmem.writePktSize::2 0 # Write request sizes (log2)
90system.physmem.writePktSize::3 0 # Write request sizes (log2)
91system.physmem.writePktSize::4 0 # Write request sizes (log2)
92system.physmem.writePktSize::5 0 # Write request sizes (log2)
93system.physmem.writePktSize::6 0 # Write request sizes (log2)
94system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
190system.physmem.bytesPerActivate::samples 95 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::mean 246.568421 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::gmean 159.892164 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::stdev 259.040400 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::0-127 37 38.95% 38.95% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::128-255 23 24.21% 63.16% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::256-383 16 16.84% 80.00% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::384-511 6 6.32% 86.32% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::512-639 2 2.11% 88.42% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::640-767 3 3.16% 91.58% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::768-895 2 2.11% 93.68% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::896-1023 2 2.11% 95.79% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1024-1151 4 4.21% 100.00% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::total 95 # Bytes accessed per row activation
204system.physmem.totQLat 6803250 # Total ticks spent queuing
205system.physmem.totMemAccLat 14640750 # Total ticks spent from burst creation until serviced by the DRAM
206system.physmem.totBusLat 2090000 # Total ticks spent in databus transfers
207system.physmem.avgQLat 16275.72 # Average queueing delay per DRAM burst
208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
209system.physmem.avgMemAccLat 35025.72 # Average memory access latency per DRAM burst
210system.physmem.avgRdBW 1190.75 # Average DRAM read bandwidth in MiByte/s
211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
212system.physmem.avgRdBWSys 1190.75 # Average system read bandwidth in MiByte/s
213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
215system.physmem.busUtil 9.30 # Data bus utilization in percentage
216system.physmem.busUtilRead 9.30 # Data bus utilization in percentage for reads
217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
218system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing
219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
220system.physmem.readRowHits 310 # Number of row buffer hits during reads
221system.physmem.writeRowHits 0 # Number of row buffer hits during writes
222system.physmem.readRowHitRate 74.16 # Row buffer hit rate for reads
223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
224system.physmem.avgGap 53437.80 # Average gap between requests
225system.physmem.pageHitRate 74.16 # Row buffer hit rate, read and write combined
226system.physmem_0.actEnergy 285600 # Energy for activate commands per rank (pJ)
227system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ)
228system.physmem_0.readEnergy 1413720 # Energy for read commands per rank (pJ)
229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
230system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
231system.physmem_0.actBackEnergy 2399130 # Energy for active background per rank (pJ)
232system.physmem_0.preBackEnergy 30240 # Energy for precharge background per rank (pJ)
233system.physmem_0.actPowerDownEnergy 7645980 # Energy for active power-down per rank (pJ)
234system.physmem_0.prePowerDownEnergy 138240 # Energy for precharge power-down per rank (pJ)
235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
236system.physmem_0.totalEnergy 13267425 # Total energy per rank (pJ)
237system.physmem_0.averagePower 590.516301 # Core power per rank (mW)
238system.physmem_0.totalIdleTime 17035500 # Total Idle time Per DRAM Rank
239system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states
240system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
242system.physmem_0.memoryStateTime::PRE_PDN 359250 # Time in different power states
243system.physmem_0.memoryStateTime::ACT 4794250 # Time in different power states
244system.physmem_0.memoryStateTime::ACT_PDN 16769500 # Time in different power states
245system.physmem_1.actEnergy 485520 # Energy for activate commands per rank (pJ)
246system.physmem_1.preEnergy 235290 # Energy for precharge commands per rank (pJ)
247system.physmem_1.readEnergy 1570800 # Energy for read commands per rank (pJ)
248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
249system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
250system.physmem_1.actBackEnergy 2963430 # Energy for active background per rank (pJ)
251system.physmem_1.preBackEnergy 82560 # Energy for precharge background per rank (pJ)
252system.physmem_1.actPowerDownEnergy 7182000 # Energy for active power-down per rank (pJ)
253system.physmem_1.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ)
254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
255system.physmem_1.totalEnergy 13750320 # Total energy per rank (pJ)
256system.physmem_1.averagePower 612.009347 # Core power per rank (mW)
257system.physmem_1.totalIdleTime 14672000 # Total Idle time Per DRAM Rank
258system.physmem_1.memoryStateTime::IDLE 109000 # Time in different power states
259system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
261system.physmem_1.memoryStateTime::PRE_PDN 3500 # Time in different power states
262system.physmem_1.memoryStateTime::ACT 6091750 # Time in different power states
263system.physmem_1.memoryStateTime::ACT_PDN 15742250 # Time in different power states
264system.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
265system.cpu.branchPred.lookups 3488 # Number of BP lookups
266system.cpu.branchPred.condPredicted 3488 # Number of conditional branches predicted
267system.cpu.branchPred.condIncorrect 571 # Number of conditional branches incorrect
268system.cpu.branchPred.BTBLookups 2960 # Number of BTB lookups
269system.cpu.branchPred.BTBHits 0 # Number of BTB hits
270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
271system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
272system.cpu.branchPred.usedRAS 360 # Number of times the RAS was used to get a target.
273system.cpu.branchPred.RASInCorrect 94 # Number of incorrect RAS predictions.
274system.cpu.branchPred.indirectLookups 2960 # Number of indirect predictor lookups.
275system.cpu.branchPred.indirectHits 483 # Number of indirect target hits.
276system.cpu.branchPred.indirectMisses 2477 # Number of indirect misses.
277system.cpu.branchPredindirectMispredicted 410 # Number of mispredicted indirect branches.
278system.cpu_clk_domain.clock 500 # Clock period in ticks
279system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
280system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
281system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
282system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
283system.cpu.workload.num_syscalls 11 # Number of system calls
284system.cpu.pwrStateResidencyTicks::ON 22466500 # Cumulative time (in ticks) in various power states
285system.cpu.numCycles 44934 # number of cpu cycles simulated
286system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
287system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
288system.cpu.fetch.icacheStallCycles 12177 # Number of cycles fetch is stalled on an Icache miss
289system.cpu.fetch.Insts 15717 # Number of instructions fetch has processed
290system.cpu.fetch.Branches 3488 # Number of branches that fetch encountered
291system.cpu.fetch.predictedBranches 843 # Number of branches that fetch has predicted taken
292system.cpu.fetch.Cycles 10477 # Number of cycles fetch has run and was not squashing or blocked
293system.cpu.fetch.SquashCycles 1321 # Number of cycles fetch has spent squashing
294system.cpu.fetch.MiscStallCycles 78 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
295system.cpu.fetch.PendingTrapStallCycles 1414 # Number of stall cycles due to pending traps
296system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions
297system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR
298system.cpu.fetch.CacheLines 2026 # Number of cache lines fetched
299system.cpu.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed
300system.cpu.fetch.rateDist::samples 24836 # Number of instructions fetched each cycle (Total)
301system.cpu.fetch.rateDist::mean 1.141770 # Number of instructions fetched each cycle (Total)
302system.cpu.fetch.rateDist::stdev 2.668775 # Number of instructions fetched each cycle (Total)
303system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
304system.cpu.fetch.rateDist::0 20599 82.94% 82.94% # Number of instructions fetched each cycle (Total)
305system.cpu.fetch.rateDist::1 175 0.70% 83.64% # Number of instructions fetched each cycle (Total)
306system.cpu.fetch.rateDist::2 165 0.66% 84.31% # Number of instructions fetched each cycle (Total)
307system.cpu.fetch.rateDist::3 225 0.91% 85.22% # Number of instructions fetched each cycle (Total)
308system.cpu.fetch.rateDist::4 209 0.84% 86.06% # Number of instructions fetched each cycle (Total)
309system.cpu.fetch.rateDist::5 222 0.89% 86.95% # Number of instructions fetched each cycle (Total)
310system.cpu.fetch.rateDist::6 269 1.08% 88.03% # Number of instructions fetched each cycle (Total)
311system.cpu.fetch.rateDist::7 159 0.64% 88.67% # Number of instructions fetched each cycle (Total)
312system.cpu.fetch.rateDist::8 2813 11.33% 100.00% # Number of instructions fetched each cycle (Total)
313system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
314system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
315system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
316system.cpu.fetch.rateDist::total 24836 # Number of instructions fetched each cycle (Total)
317system.cpu.fetch.branchRate 0.077625 # Number of branch fetches per cycle
318system.cpu.fetch.rate 0.349780 # Number of inst fetches per cycle
319system.cpu.decode.IdleCycles 12221 # Number of cycles decode is idle
320system.cpu.decode.BlockedCycles 8128 # Number of cycles decode is blocked
321system.cpu.decode.RunCycles 3370 # Number of cycles decode is running
322system.cpu.decode.UnblockCycles 457 # Number of cycles decode is unblocking
323system.cpu.decode.SquashCycles 660 # Number of cycles decode is squashing
324system.cpu.decode.DecodedInsts 26405 # Number of instructions handled by decode
325system.cpu.rename.SquashCycles 660 # Number of cycles rename is squashing
326system.cpu.rename.IdleCycles 12481 # Number of cycles rename is idle
327system.cpu.rename.BlockCycles 1971 # Number of cycles rename is blocking
328system.cpu.rename.serializeStallCycles 1213 # count of cycles rename stalled for serializing inst
329system.cpu.rename.RunCycles 3524 # Number of cycles rename is running
330system.cpu.rename.UnblockCycles 4987 # Number of cycles rename is unblocking
331system.cpu.rename.RenamedInsts 24875 # Number of instructions processed by rename
332system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full
333system.cpu.rename.IQFullEvents 82 # Number of times rename has blocked due to IQ full
334system.cpu.rename.SQFullEvents 4849 # Number of times rename has blocked due to SQ full
335system.cpu.rename.RenamedOperands 27762 # Number of destination operands rename has renamed
336system.cpu.rename.RenameLookups 60616 # Number of register rename lookups that rename has made
337system.cpu.rename.int_rename_lookups 34638 # Number of integer rename lookups
338system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
339system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed
340system.cpu.rename.UndoneMaps 16699 # Number of HB maps that are undone due to squashing
341system.cpu.rename.serializingInsts 25 # count of serializing insts renamed
342system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed
343system.cpu.rename.skidInsts 1436 # count of insts added to the skid buffer
344system.cpu.memDep0.insertedLoads 2622 # Number of loads inserted to the mem dependence unit.
345system.cpu.memDep0.insertedStores 1598 # Number of stores inserted to the mem dependence unit.
346system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads.
347system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores.
348system.cpu.iq.iqInstsAdded 21775 # Number of instructions added to the IQ (excludes non-spec)
349system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
350system.cpu.iq.iqInstsIssued 18112 # Number of instructions issued
351system.cpu.iq.iqSquashedInstsIssued 144 # Number of squashed instructions issued
352system.cpu.iq.iqSquashedInstsExamined 12051 # Number of squashed instructions iterated over during squash; mainly for profiling
353system.cpu.iq.iqSquashedOperandsExamined 16553 # Number of squashed operands that are examined and possibly removed from graph
354system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
355system.cpu.iq.issued_per_cycle::samples 24836 # Number of insts issued each cycle
356system.cpu.iq.issued_per_cycle::mean 0.729264 # Number of insts issued each cycle
357system.cpu.iq.issued_per_cycle::stdev 1.710819 # Number of insts issued each cycle
358system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
359system.cpu.iq.issued_per_cycle::0 19691 79.28% 79.28% # Number of insts issued each cycle
360system.cpu.iq.issued_per_cycle::1 1200 4.83% 84.12% # Number of insts issued each cycle
361system.cpu.iq.issued_per_cycle::2 866 3.49% 87.60% # Number of insts issued each cycle
362system.cpu.iq.issued_per_cycle::3 575 2.32% 89.92% # Number of insts issued each cycle
363system.cpu.iq.issued_per_cycle::4 815 3.28% 93.20% # Number of insts issued each cycle
364system.cpu.iq.issued_per_cycle::5 575 2.32% 95.51% # Number of insts issued each cycle
365system.cpu.iq.issued_per_cycle::6 614 2.47% 97.99% # Number of insts issued each cycle
366system.cpu.iq.issued_per_cycle::7 364 1.47% 99.45% # Number of insts issued each cycle
367system.cpu.iq.issued_per_cycle::8 136 0.55% 100.00% # Number of insts issued each cycle
368system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
369system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
370system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
371system.cpu.iq.issued_per_cycle::total 24836 # Number of insts issued each cycle
372system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
373system.cpu.iq.fu_full::IntAlu 223 79.93% 79.93% # attempts to use FU when none available
374system.cpu.iq.fu_full::IntMult 0 0.00% 79.93% # attempts to use FU when none available
375system.cpu.iq.fu_full::IntDiv 0 0.00% 79.93% # attempts to use FU when none available
376system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.93% # attempts to use FU when none available
377system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.93% # attempts to use FU when none available
378system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.93% # attempts to use FU when none available
379system.cpu.iq.fu_full::FloatMult 0 0.00% 79.93% # attempts to use FU when none available
| 12sim_insts 5380 # Number of instructions simulated
13sim_ops 9747 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
19system.physmem.bytes_read::total 26752 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 418 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 789085972 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 401664701 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 1190750673 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 789085972 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 789085972 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 789085972 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 401664701 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 1190750673 # Total bandwidth to/from this memory (bytes/s)
33system.physmem.readReqs 418 # Number of read requests accepted
34system.physmem.writeReqs 0 # Number of write requests accepted
35system.physmem.readBursts 418 # Number of DRAM read bursts, including those serviced by the write queue
36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
37system.physmem.bytesReadDRAM 26752 # Total number of bytes read from DRAM
38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
40system.physmem.bytesReadSys 26752 # Total read bytes from the system interface side
41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
45system.physmem.perBankRdBursts::0 32 # Per bank write bursts
46system.physmem.perBankRdBursts::1 1 # Per bank write bursts
47system.physmem.perBankRdBursts::2 5 # Per bank write bursts
48system.physmem.perBankRdBursts::3 8 # Per bank write bursts
49system.physmem.perBankRdBursts::4 50 # Per bank write bursts
50system.physmem.perBankRdBursts::5 44 # Per bank write bursts
51system.physmem.perBankRdBursts::6 21 # Per bank write bursts
52system.physmem.perBankRdBursts::7 37 # Per bank write bursts
53system.physmem.perBankRdBursts::8 24 # Per bank write bursts
54system.physmem.perBankRdBursts::9 71 # Per bank write bursts
55system.physmem.perBankRdBursts::10 64 # Per bank write bursts
56system.physmem.perBankRdBursts::11 16 # Per bank write bursts
57system.physmem.perBankRdBursts::12 2 # Per bank write bursts
58system.physmem.perBankRdBursts::13 20 # Per bank write bursts
59system.physmem.perBankRdBursts::14 6 # Per bank write bursts
60system.physmem.perBankRdBursts::15 17 # Per bank write bursts
61system.physmem.perBankWrBursts::0 0 # Per bank write bursts
62system.physmem.perBankWrBursts::1 0 # Per bank write bursts
63system.physmem.perBankWrBursts::2 0 # Per bank write bursts
64system.physmem.perBankWrBursts::3 0 # Per bank write bursts
65system.physmem.perBankWrBursts::4 0 # Per bank write bursts
66system.physmem.perBankWrBursts::5 0 # Per bank write bursts
67system.physmem.perBankWrBursts::6 0 # Per bank write bursts
68system.physmem.perBankWrBursts::7 0 # Per bank write bursts
69system.physmem.perBankWrBursts::8 0 # Per bank write bursts
70system.physmem.perBankWrBursts::9 0 # Per bank write bursts
71system.physmem.perBankWrBursts::10 0 # Per bank write bursts
72system.physmem.perBankWrBursts::11 0 # Per bank write bursts
73system.physmem.perBankWrBursts::12 0 # Per bank write bursts
74system.physmem.perBankWrBursts::13 0 # Per bank write bursts
75system.physmem.perBankWrBursts::14 0 # Per bank write bursts
76system.physmem.perBankWrBursts::15 0 # Per bank write bursts
77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
79system.physmem.totGap 22337000 # Total gap between requests
80system.physmem.readPktSize::0 0 # Read request sizes (log2)
81system.physmem.readPktSize::1 0 # Read request sizes (log2)
82system.physmem.readPktSize::2 0 # Read request sizes (log2)
83system.physmem.readPktSize::3 0 # Read request sizes (log2)
84system.physmem.readPktSize::4 0 # Read request sizes (log2)
85system.physmem.readPktSize::5 0 # Read request sizes (log2)
86system.physmem.readPktSize::6 418 # Read request sizes (log2)
87system.physmem.writePktSize::0 0 # Write request sizes (log2)
88system.physmem.writePktSize::1 0 # Write request sizes (log2)
89system.physmem.writePktSize::2 0 # Write request sizes (log2)
90system.physmem.writePktSize::3 0 # Write request sizes (log2)
91system.physmem.writePktSize::4 0 # Write request sizes (log2)
92system.physmem.writePktSize::5 0 # Write request sizes (log2)
93system.physmem.writePktSize::6 0 # Write request sizes (log2)
94system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
190system.physmem.bytesPerActivate::samples 95 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::mean 246.568421 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::gmean 159.892164 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::stdev 259.040400 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::0-127 37 38.95% 38.95% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::128-255 23 24.21% 63.16% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::256-383 16 16.84% 80.00% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::384-511 6 6.32% 86.32% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::512-639 2 2.11% 88.42% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::640-767 3 3.16% 91.58% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::768-895 2 2.11% 93.68% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::896-1023 2 2.11% 95.79% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1024-1151 4 4.21% 100.00% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::total 95 # Bytes accessed per row activation
204system.physmem.totQLat 6803250 # Total ticks spent queuing
205system.physmem.totMemAccLat 14640750 # Total ticks spent from burst creation until serviced by the DRAM
206system.physmem.totBusLat 2090000 # Total ticks spent in databus transfers
207system.physmem.avgQLat 16275.72 # Average queueing delay per DRAM burst
208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
209system.physmem.avgMemAccLat 35025.72 # Average memory access latency per DRAM burst
210system.physmem.avgRdBW 1190.75 # Average DRAM read bandwidth in MiByte/s
211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
212system.physmem.avgRdBWSys 1190.75 # Average system read bandwidth in MiByte/s
213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
215system.physmem.busUtil 9.30 # Data bus utilization in percentage
216system.physmem.busUtilRead 9.30 # Data bus utilization in percentage for reads
217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
218system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing
219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
220system.physmem.readRowHits 310 # Number of row buffer hits during reads
221system.physmem.writeRowHits 0 # Number of row buffer hits during writes
222system.physmem.readRowHitRate 74.16 # Row buffer hit rate for reads
223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
224system.physmem.avgGap 53437.80 # Average gap between requests
225system.physmem.pageHitRate 74.16 # Row buffer hit rate, read and write combined
226system.physmem_0.actEnergy 285600 # Energy for activate commands per rank (pJ)
227system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ)
228system.physmem_0.readEnergy 1413720 # Energy for read commands per rank (pJ)
229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
230system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
231system.physmem_0.actBackEnergy 2399130 # Energy for active background per rank (pJ)
232system.physmem_0.preBackEnergy 30240 # Energy for precharge background per rank (pJ)
233system.physmem_0.actPowerDownEnergy 7645980 # Energy for active power-down per rank (pJ)
234system.physmem_0.prePowerDownEnergy 138240 # Energy for precharge power-down per rank (pJ)
235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
236system.physmem_0.totalEnergy 13267425 # Total energy per rank (pJ)
237system.physmem_0.averagePower 590.516301 # Core power per rank (mW)
238system.physmem_0.totalIdleTime 17035500 # Total Idle time Per DRAM Rank
239system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states
240system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
242system.physmem_0.memoryStateTime::PRE_PDN 359250 # Time in different power states
243system.physmem_0.memoryStateTime::ACT 4794250 # Time in different power states
244system.physmem_0.memoryStateTime::ACT_PDN 16769500 # Time in different power states
245system.physmem_1.actEnergy 485520 # Energy for activate commands per rank (pJ)
246system.physmem_1.preEnergy 235290 # Energy for precharge commands per rank (pJ)
247system.physmem_1.readEnergy 1570800 # Energy for read commands per rank (pJ)
248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
249system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
250system.physmem_1.actBackEnergy 2963430 # Energy for active background per rank (pJ)
251system.physmem_1.preBackEnergy 82560 # Energy for precharge background per rank (pJ)
252system.physmem_1.actPowerDownEnergy 7182000 # Energy for active power-down per rank (pJ)
253system.physmem_1.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ)
254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
255system.physmem_1.totalEnergy 13750320 # Total energy per rank (pJ)
256system.physmem_1.averagePower 612.009347 # Core power per rank (mW)
257system.physmem_1.totalIdleTime 14672000 # Total Idle time Per DRAM Rank
258system.physmem_1.memoryStateTime::IDLE 109000 # Time in different power states
259system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
261system.physmem_1.memoryStateTime::PRE_PDN 3500 # Time in different power states
262system.physmem_1.memoryStateTime::ACT 6091750 # Time in different power states
263system.physmem_1.memoryStateTime::ACT_PDN 15742250 # Time in different power states
264system.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
265system.cpu.branchPred.lookups 3488 # Number of BP lookups
266system.cpu.branchPred.condPredicted 3488 # Number of conditional branches predicted
267system.cpu.branchPred.condIncorrect 571 # Number of conditional branches incorrect
268system.cpu.branchPred.BTBLookups 2960 # Number of BTB lookups
269system.cpu.branchPred.BTBHits 0 # Number of BTB hits
270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
271system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
272system.cpu.branchPred.usedRAS 360 # Number of times the RAS was used to get a target.
273system.cpu.branchPred.RASInCorrect 94 # Number of incorrect RAS predictions.
274system.cpu.branchPred.indirectLookups 2960 # Number of indirect predictor lookups.
275system.cpu.branchPred.indirectHits 483 # Number of indirect target hits.
276system.cpu.branchPred.indirectMisses 2477 # Number of indirect misses.
277system.cpu.branchPredindirectMispredicted 410 # Number of mispredicted indirect branches.
278system.cpu_clk_domain.clock 500 # Clock period in ticks
279system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
280system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
281system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
282system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
283system.cpu.workload.num_syscalls 11 # Number of system calls
284system.cpu.pwrStateResidencyTicks::ON 22466500 # Cumulative time (in ticks) in various power states
285system.cpu.numCycles 44934 # number of cpu cycles simulated
286system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
287system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
288system.cpu.fetch.icacheStallCycles 12177 # Number of cycles fetch is stalled on an Icache miss
289system.cpu.fetch.Insts 15717 # Number of instructions fetch has processed
290system.cpu.fetch.Branches 3488 # Number of branches that fetch encountered
291system.cpu.fetch.predictedBranches 843 # Number of branches that fetch has predicted taken
292system.cpu.fetch.Cycles 10477 # Number of cycles fetch has run and was not squashing or blocked
293system.cpu.fetch.SquashCycles 1321 # Number of cycles fetch has spent squashing
294system.cpu.fetch.MiscStallCycles 78 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
295system.cpu.fetch.PendingTrapStallCycles 1414 # Number of stall cycles due to pending traps
296system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions
297system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR
298system.cpu.fetch.CacheLines 2026 # Number of cache lines fetched
299system.cpu.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed
300system.cpu.fetch.rateDist::samples 24836 # Number of instructions fetched each cycle (Total)
301system.cpu.fetch.rateDist::mean 1.141770 # Number of instructions fetched each cycle (Total)
302system.cpu.fetch.rateDist::stdev 2.668775 # Number of instructions fetched each cycle (Total)
303system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
304system.cpu.fetch.rateDist::0 20599 82.94% 82.94% # Number of instructions fetched each cycle (Total)
305system.cpu.fetch.rateDist::1 175 0.70% 83.64% # Number of instructions fetched each cycle (Total)
306system.cpu.fetch.rateDist::2 165 0.66% 84.31% # Number of instructions fetched each cycle (Total)
307system.cpu.fetch.rateDist::3 225 0.91% 85.22% # Number of instructions fetched each cycle (Total)
308system.cpu.fetch.rateDist::4 209 0.84% 86.06% # Number of instructions fetched each cycle (Total)
309system.cpu.fetch.rateDist::5 222 0.89% 86.95% # Number of instructions fetched each cycle (Total)
310system.cpu.fetch.rateDist::6 269 1.08% 88.03% # Number of instructions fetched each cycle (Total)
311system.cpu.fetch.rateDist::7 159 0.64% 88.67% # Number of instructions fetched each cycle (Total)
312system.cpu.fetch.rateDist::8 2813 11.33% 100.00% # Number of instructions fetched each cycle (Total)
313system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
314system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
315system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
316system.cpu.fetch.rateDist::total 24836 # Number of instructions fetched each cycle (Total)
317system.cpu.fetch.branchRate 0.077625 # Number of branch fetches per cycle
318system.cpu.fetch.rate 0.349780 # Number of inst fetches per cycle
319system.cpu.decode.IdleCycles 12221 # Number of cycles decode is idle
320system.cpu.decode.BlockedCycles 8128 # Number of cycles decode is blocked
321system.cpu.decode.RunCycles 3370 # Number of cycles decode is running
322system.cpu.decode.UnblockCycles 457 # Number of cycles decode is unblocking
323system.cpu.decode.SquashCycles 660 # Number of cycles decode is squashing
324system.cpu.decode.DecodedInsts 26405 # Number of instructions handled by decode
325system.cpu.rename.SquashCycles 660 # Number of cycles rename is squashing
326system.cpu.rename.IdleCycles 12481 # Number of cycles rename is idle
327system.cpu.rename.BlockCycles 1971 # Number of cycles rename is blocking
328system.cpu.rename.serializeStallCycles 1213 # count of cycles rename stalled for serializing inst
329system.cpu.rename.RunCycles 3524 # Number of cycles rename is running
330system.cpu.rename.UnblockCycles 4987 # Number of cycles rename is unblocking
331system.cpu.rename.RenamedInsts 24875 # Number of instructions processed by rename
332system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full
333system.cpu.rename.IQFullEvents 82 # Number of times rename has blocked due to IQ full
334system.cpu.rename.SQFullEvents 4849 # Number of times rename has blocked due to SQ full
335system.cpu.rename.RenamedOperands 27762 # Number of destination operands rename has renamed
336system.cpu.rename.RenameLookups 60616 # Number of register rename lookups that rename has made
337system.cpu.rename.int_rename_lookups 34638 # Number of integer rename lookups
338system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
339system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed
340system.cpu.rename.UndoneMaps 16699 # Number of HB maps that are undone due to squashing
341system.cpu.rename.serializingInsts 25 # count of serializing insts renamed
342system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed
343system.cpu.rename.skidInsts 1436 # count of insts added to the skid buffer
344system.cpu.memDep0.insertedLoads 2622 # Number of loads inserted to the mem dependence unit.
345system.cpu.memDep0.insertedStores 1598 # Number of stores inserted to the mem dependence unit.
346system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads.
347system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores.
348system.cpu.iq.iqInstsAdded 21775 # Number of instructions added to the IQ (excludes non-spec)
349system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
350system.cpu.iq.iqInstsIssued 18112 # Number of instructions issued
351system.cpu.iq.iqSquashedInstsIssued 144 # Number of squashed instructions issued
352system.cpu.iq.iqSquashedInstsExamined 12051 # Number of squashed instructions iterated over during squash; mainly for profiling
353system.cpu.iq.iqSquashedOperandsExamined 16553 # Number of squashed operands that are examined and possibly removed from graph
354system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
355system.cpu.iq.issued_per_cycle::samples 24836 # Number of insts issued each cycle
356system.cpu.iq.issued_per_cycle::mean 0.729264 # Number of insts issued each cycle
357system.cpu.iq.issued_per_cycle::stdev 1.710819 # Number of insts issued each cycle
358system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
359system.cpu.iq.issued_per_cycle::0 19691 79.28% 79.28% # Number of insts issued each cycle
360system.cpu.iq.issued_per_cycle::1 1200 4.83% 84.12% # Number of insts issued each cycle
361system.cpu.iq.issued_per_cycle::2 866 3.49% 87.60% # Number of insts issued each cycle
362system.cpu.iq.issued_per_cycle::3 575 2.32% 89.92% # Number of insts issued each cycle
363system.cpu.iq.issued_per_cycle::4 815 3.28% 93.20% # Number of insts issued each cycle
364system.cpu.iq.issued_per_cycle::5 575 2.32% 95.51% # Number of insts issued each cycle
365system.cpu.iq.issued_per_cycle::6 614 2.47% 97.99% # Number of insts issued each cycle
366system.cpu.iq.issued_per_cycle::7 364 1.47% 99.45% # Number of insts issued each cycle
367system.cpu.iq.issued_per_cycle::8 136 0.55% 100.00% # Number of insts issued each cycle
368system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
369system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
370system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
371system.cpu.iq.issued_per_cycle::total 24836 # Number of insts issued each cycle
372system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
373system.cpu.iq.fu_full::IntAlu 223 79.93% 79.93% # attempts to use FU when none available
374system.cpu.iq.fu_full::IntMult 0 0.00% 79.93% # attempts to use FU when none available
375system.cpu.iq.fu_full::IntDiv 0 0.00% 79.93% # attempts to use FU when none available
376system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.93% # attempts to use FU when none available
377system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.93% # attempts to use FU when none available
378system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.93% # attempts to use FU when none available
379system.cpu.iq.fu_full::FloatMult 0 0.00% 79.93% # attempts to use FU when none available
|
| 380system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 79.93% # attempts to use FU when none available
|
380system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.93% # attempts to use FU when none available
| 381system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.93% # attempts to use FU when none available
|
| 382system.cpu.iq.fu_full::FloatMisc 0 0.00% 79.93% # attempts to use FU when none available
|
381system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.93% # attempts to use FU when none available
382system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.93% # attempts to use FU when none available
383system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.93% # attempts to use FU when none available
384system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.93% # attempts to use FU when none available
385system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.93% # attempts to use FU when none available
386system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.93% # attempts to use FU when none available
387system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.93% # attempts to use FU when none available
388system.cpu.iq.fu_full::SimdMult 0 0.00% 79.93% # attempts to use FU when none available
389system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.93% # attempts to use FU when none available
390system.cpu.iq.fu_full::SimdShift 0 0.00% 79.93% # attempts to use FU when none available
391system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.93% # attempts to use FU when none available
392system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.93% # attempts to use FU when none available
393system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.93% # attempts to use FU when none available
394system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.93% # attempts to use FU when none available
395system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.93% # attempts to use FU when none available
396system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.93% # attempts to use FU when none available
397system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.93% # attempts to use FU when none available
398system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.93% # attempts to use FU when none available
399system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.93% # attempts to use FU when none available
400system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.93% # attempts to use FU when none available
401system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.93% # attempts to use FU when none available
402system.cpu.iq.fu_full::MemRead 41 14.70% 94.62% # attempts to use FU when none available
403system.cpu.iq.fu_full::MemWrite 15 5.38% 100.00% # attempts to use FU when none available
| 383system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.93% # attempts to use FU when none available
384system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.93% # attempts to use FU when none available
385system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.93% # attempts to use FU when none available
386system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.93% # attempts to use FU when none available
387system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.93% # attempts to use FU when none available
388system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.93% # attempts to use FU when none available
389system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.93% # attempts to use FU when none available
390system.cpu.iq.fu_full::SimdMult 0 0.00% 79.93% # attempts to use FU when none available
391system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.93% # attempts to use FU when none available
392system.cpu.iq.fu_full::SimdShift 0 0.00% 79.93% # attempts to use FU when none available
393system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.93% # attempts to use FU when none available
394system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.93% # attempts to use FU when none available
395system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.93% # attempts to use FU when none available
396system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.93% # attempts to use FU when none available
397system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.93% # attempts to use FU when none available
398system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.93% # attempts to use FU when none available
399system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.93% # attempts to use FU when none available
400system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.93% # attempts to use FU when none available
401system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.93% # attempts to use FU when none available
402system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.93% # attempts to use FU when none available
403system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.93% # attempts to use FU when none available
404system.cpu.iq.fu_full::MemRead 41 14.70% 94.62% # attempts to use FU when none available
405system.cpu.iq.fu_full::MemWrite 15 5.38% 100.00% # attempts to use FU when none available
|
| 406system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available
407system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available
|
404system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
405system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
406system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued
407system.cpu.iq.FU_type_0::IntAlu 14478 79.94% 79.95% # Type of FU issued
408system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.98% # Type of FU issued
409system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.02% # Type of FU issued
410system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.02% # Type of FU issued
411system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.02% # Type of FU issued
412system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.02% # Type of FU issued
413system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.02% # Type of FU issued
| 408system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
409system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
410system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued
411system.cpu.iq.FU_type_0::IntAlu 14478 79.94% 79.95% # Type of FU issued
412system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.98% # Type of FU issued
413system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.02% # Type of FU issued
414system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.02% # Type of FU issued
415system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.02% # Type of FU issued
416system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.02% # Type of FU issued
417system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.02% # Type of FU issued
|
| 418system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 80.02% # Type of FU issued
|
414system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.02% # Type of FU issued
| 419system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.02% # Type of FU issued
|
| 420system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 80.02% # Type of FU issued
|
415system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.02% # Type of FU issued
416system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.02% # Type of FU issued
417system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.02% # Type of FU issued
418system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.02% # Type of FU issued
419system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.02% # Type of FU issued
420system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.02% # Type of FU issued
421system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.02% # Type of FU issued
422system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.02% # Type of FU issued
423system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.02% # Type of FU issued
424system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.02% # Type of FU issued
425system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.02% # Type of FU issued
426system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.02% # Type of FU issued
427system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.02% # Type of FU issued
428system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.02% # Type of FU issued
429system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.02% # Type of FU issued
430system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.02% # Type of FU issued
431system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.02% # Type of FU issued
432system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.02% # Type of FU issued
433system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.02% # Type of FU issued
434system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.02% # Type of FU issued
435system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.02% # Type of FU issued
436system.cpu.iq.FU_type_0::MemRead 2258 12.47% 92.49% # Type of FU issued
| 421system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.02% # Type of FU issued
422system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.02% # Type of FU issued
423system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.02% # Type of FU issued
424system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.02% # Type of FU issued
425system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.02% # Type of FU issued
426system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.02% # Type of FU issued
427system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.02% # Type of FU issued
428system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.02% # Type of FU issued
429system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.02% # Type of FU issued
430system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.02% # Type of FU issued
431system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.02% # Type of FU issued
432system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.02% # Type of FU issued
433system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.02% # Type of FU issued
434system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.02% # Type of FU issued
435system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.02% # Type of FU issued
436system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.02% # Type of FU issued
437system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.02% # Type of FU issued
438system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.02% # Type of FU issued
439system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.02% # Type of FU issued
440system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.02% # Type of FU issued
441system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.02% # Type of FU issued
442system.cpu.iq.FU_type_0::MemRead 2258 12.47% 92.49% # Type of FU issued
|
437system.cpu.iq.FU_type_0::MemWrite 1361 7.51% 100.00% # Type of FU issued
| 443system.cpu.iq.FU_type_0::MemWrite 1357 7.49% 99.98% # Type of FU issued
444system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.98% # Type of FU issued
445system.cpu.iq.FU_type_0::FloatMemWrite 4 0.02% 100.00% # Type of FU issued
|
438system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
439system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
440system.cpu.iq.FU_type_0::total 18112 # Type of FU issued
441system.cpu.iq.rate 0.403080 # Inst issue rate
442system.cpu.iq.fu_busy_cnt 279 # FU busy when requested
443system.cpu.iq.fu_busy_rate 0.015404 # FU busy rate (busy events/executed inst)
444system.cpu.iq.int_inst_queue_reads 61475 # Number of integer instruction queue reads
445system.cpu.iq.int_inst_queue_writes 33854 # Number of integer instruction queue writes
446system.cpu.iq.int_inst_queue_wakeup_accesses 16418 # Number of integer instruction queue wakeup accesses
447system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
448system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes
449system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
450system.cpu.iq.int_alu_accesses 18385 # Number of integer alu accesses
451system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
452system.cpu.iew.lsq.thread0.forwLoads 215 # Number of loads that had data forwarded from stores
453system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
454system.cpu.iew.lsq.thread0.squashedLoads 1569 # Number of loads squashed
455system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed
456system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations
457system.cpu.iew.lsq.thread0.squashedStores 663 # Number of stores squashed
458system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
459system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
460system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
461system.cpu.iew.lsq.thread0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked
462system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
463system.cpu.iew.iewSquashCycles 660 # Number of cycles IEW is squashing
464system.cpu.iew.iewBlockCycles 1482 # Number of cycles IEW is blocking
465system.cpu.iew.iewUnblockCycles 153 # Number of cycles IEW is unblocking
466system.cpu.iew.iewDispatchedInsts 21798 # Number of instructions dispatched to IQ
467system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch
468system.cpu.iew.iewDispLoadInsts 2622 # Number of dispatched load instructions
469system.cpu.iew.iewDispStoreInsts 1598 # Number of dispatched store instructions
470system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
471system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
472system.cpu.iew.iewLSQFullEvents 152 # Number of times the LSQ has become full, causing a stall
473system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations
474system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly
475system.cpu.iew.predictedNotTakenIncorrect 680 # Number of branches that were predicted not taken incorrectly
476system.cpu.iew.branchMispredicts 798 # Number of branch mispredicts detected at execute
477system.cpu.iew.iewExecutedInsts 17038 # Number of executed instructions
478system.cpu.iew.iewExecLoadInsts 2047 # Number of load instructions executed
479system.cpu.iew.iewExecSquashedInsts 1074 # Number of squashed instructions skipped in execute
480system.cpu.iew.exec_swp 0 # number of swp insts executed
481system.cpu.iew.exec_nop 0 # number of nop insts executed
482system.cpu.iew.exec_refs 3306 # number of memory reference insts executed
483system.cpu.iew.exec_branches 1731 # Number of branches executed
484system.cpu.iew.exec_stores 1259 # Number of stores executed
485system.cpu.iew.exec_rate 0.379178 # Inst execution rate
486system.cpu.iew.wb_sent 16737 # cumulative count of insts sent to commit
487system.cpu.iew.wb_count 16422 # cumulative count of insts written-back
488system.cpu.iew.wb_producers 11019 # num instructions producing a value
489system.cpu.iew.wb_consumers 17148 # num instructions consuming a value
490system.cpu.iew.wb_rate 0.365469 # insts written-back per cycle
491system.cpu.iew.wb_fanout 0.642582 # average fanout of values written-back
492system.cpu.commit.commitSquashedInsts 12050 # The number of squashed insts skipped by commit
493system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
494system.cpu.commit.branchMispredicts 648 # The number of times a branch was mispredicted
495system.cpu.commit.committed_per_cycle::samples 22793 # Number of insts commited each cycle
496system.cpu.commit.committed_per_cycle::mean 0.427631 # Number of insts commited each cycle
497system.cpu.commit.committed_per_cycle::stdev 1.307645 # Number of insts commited each cycle
498system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
499system.cpu.commit.committed_per_cycle::0 19538 85.72% 85.72% # Number of insts commited each cycle
500system.cpu.commit.committed_per_cycle::1 1001 4.39% 90.11% # Number of insts commited each cycle
501system.cpu.commit.committed_per_cycle::2 566 2.48% 92.59% # Number of insts commited each cycle
502system.cpu.commit.committed_per_cycle::3 727 3.19% 95.78% # Number of insts commited each cycle
503system.cpu.commit.committed_per_cycle::4 384 1.68% 97.47% # Number of insts commited each cycle
504system.cpu.commit.committed_per_cycle::5 133 0.58% 98.05% # Number of insts commited each cycle
505system.cpu.commit.committed_per_cycle::6 124 0.54% 98.60% # Number of insts commited each cycle
506system.cpu.commit.committed_per_cycle::7 72 0.32% 98.91% # Number of insts commited each cycle
507system.cpu.commit.committed_per_cycle::8 248 1.09% 100.00% # Number of insts commited each cycle
508system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
509system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
510system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
511system.cpu.commit.committed_per_cycle::total 22793 # Number of insts commited each cycle
512system.cpu.commit.committedInsts 5380 # Number of instructions committed
513system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed
514system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
515system.cpu.commit.refs 1988 # Number of memory references committed
516system.cpu.commit.loads 1053 # Number of loads committed
517system.cpu.commit.membars 0 # Number of memory barriers committed
518system.cpu.commit.branches 1208 # Number of branches committed
519system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
520system.cpu.commit.int_insts 9653 # Number of committed integer instructions.
521system.cpu.commit.function_calls 106 # Number of function calls committed.
522system.cpu.commit.op_class_0::No_OpClass 1 0.01% 0.01% # Class of committed instruction
523system.cpu.commit.op_class_0::IntAlu 7748 79.49% 79.50% # Class of committed instruction
524system.cpu.commit.op_class_0::IntMult 3 0.03% 79.53% # Class of committed instruction
525system.cpu.commit.op_class_0::IntDiv 7 0.07% 79.60% # Class of committed instruction
526system.cpu.commit.op_class_0::FloatAdd 0 0.00% 79.60% # Class of committed instruction
527system.cpu.commit.op_class_0::FloatCmp 0 0.00% 79.60% # Class of committed instruction
528system.cpu.commit.op_class_0::FloatCvt 0 0.00% 79.60% # Class of committed instruction
529system.cpu.commit.op_class_0::FloatMult 0 0.00% 79.60% # Class of committed instruction
| 446system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
447system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
448system.cpu.iq.FU_type_0::total 18112 # Type of FU issued
449system.cpu.iq.rate 0.403080 # Inst issue rate
450system.cpu.iq.fu_busy_cnt 279 # FU busy when requested
451system.cpu.iq.fu_busy_rate 0.015404 # FU busy rate (busy events/executed inst)
452system.cpu.iq.int_inst_queue_reads 61475 # Number of integer instruction queue reads
453system.cpu.iq.int_inst_queue_writes 33854 # Number of integer instruction queue writes
454system.cpu.iq.int_inst_queue_wakeup_accesses 16418 # Number of integer instruction queue wakeup accesses
455system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
456system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes
457system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
458system.cpu.iq.int_alu_accesses 18385 # Number of integer alu accesses
459system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
460system.cpu.iew.lsq.thread0.forwLoads 215 # Number of loads that had data forwarded from stores
461system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
462system.cpu.iew.lsq.thread0.squashedLoads 1569 # Number of loads squashed
463system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed
464system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations
465system.cpu.iew.lsq.thread0.squashedStores 663 # Number of stores squashed
466system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
467system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
468system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
469system.cpu.iew.lsq.thread0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked
470system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
471system.cpu.iew.iewSquashCycles 660 # Number of cycles IEW is squashing
472system.cpu.iew.iewBlockCycles 1482 # Number of cycles IEW is blocking
473system.cpu.iew.iewUnblockCycles 153 # Number of cycles IEW is unblocking
474system.cpu.iew.iewDispatchedInsts 21798 # Number of instructions dispatched to IQ
475system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch
476system.cpu.iew.iewDispLoadInsts 2622 # Number of dispatched load instructions
477system.cpu.iew.iewDispStoreInsts 1598 # Number of dispatched store instructions
478system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
479system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
480system.cpu.iew.iewLSQFullEvents 152 # Number of times the LSQ has become full, causing a stall
481system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations
482system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly
483system.cpu.iew.predictedNotTakenIncorrect 680 # Number of branches that were predicted not taken incorrectly
484system.cpu.iew.branchMispredicts 798 # Number of branch mispredicts detected at execute
485system.cpu.iew.iewExecutedInsts 17038 # Number of executed instructions
486system.cpu.iew.iewExecLoadInsts 2047 # Number of load instructions executed
487system.cpu.iew.iewExecSquashedInsts 1074 # Number of squashed instructions skipped in execute
488system.cpu.iew.exec_swp 0 # number of swp insts executed
489system.cpu.iew.exec_nop 0 # number of nop insts executed
490system.cpu.iew.exec_refs 3306 # number of memory reference insts executed
491system.cpu.iew.exec_branches 1731 # Number of branches executed
492system.cpu.iew.exec_stores 1259 # Number of stores executed
493system.cpu.iew.exec_rate 0.379178 # Inst execution rate
494system.cpu.iew.wb_sent 16737 # cumulative count of insts sent to commit
495system.cpu.iew.wb_count 16422 # cumulative count of insts written-back
496system.cpu.iew.wb_producers 11019 # num instructions producing a value
497system.cpu.iew.wb_consumers 17148 # num instructions consuming a value
498system.cpu.iew.wb_rate 0.365469 # insts written-back per cycle
499system.cpu.iew.wb_fanout 0.642582 # average fanout of values written-back
500system.cpu.commit.commitSquashedInsts 12050 # The number of squashed insts skipped by commit
501system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
502system.cpu.commit.branchMispredicts 648 # The number of times a branch was mispredicted
503system.cpu.commit.committed_per_cycle::samples 22793 # Number of insts commited each cycle
504system.cpu.commit.committed_per_cycle::mean 0.427631 # Number of insts commited each cycle
505system.cpu.commit.committed_per_cycle::stdev 1.307645 # Number of insts commited each cycle
506system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
507system.cpu.commit.committed_per_cycle::0 19538 85.72% 85.72% # Number of insts commited each cycle
508system.cpu.commit.committed_per_cycle::1 1001 4.39% 90.11% # Number of insts commited each cycle
509system.cpu.commit.committed_per_cycle::2 566 2.48% 92.59% # Number of insts commited each cycle
510system.cpu.commit.committed_per_cycle::3 727 3.19% 95.78% # Number of insts commited each cycle
511system.cpu.commit.committed_per_cycle::4 384 1.68% 97.47% # Number of insts commited each cycle
512system.cpu.commit.committed_per_cycle::5 133 0.58% 98.05% # Number of insts commited each cycle
513system.cpu.commit.committed_per_cycle::6 124 0.54% 98.60% # Number of insts commited each cycle
514system.cpu.commit.committed_per_cycle::7 72 0.32% 98.91% # Number of insts commited each cycle
515system.cpu.commit.committed_per_cycle::8 248 1.09% 100.00% # Number of insts commited each cycle
516system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
517system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
518system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
519system.cpu.commit.committed_per_cycle::total 22793 # Number of insts commited each cycle
520system.cpu.commit.committedInsts 5380 # Number of instructions committed
521system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed
522system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
523system.cpu.commit.refs 1988 # Number of memory references committed
524system.cpu.commit.loads 1053 # Number of loads committed
525system.cpu.commit.membars 0 # Number of memory barriers committed
526system.cpu.commit.branches 1208 # Number of branches committed
527system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
528system.cpu.commit.int_insts 9653 # Number of committed integer instructions.
529system.cpu.commit.function_calls 106 # Number of function calls committed.
530system.cpu.commit.op_class_0::No_OpClass 1 0.01% 0.01% # Class of committed instruction
531system.cpu.commit.op_class_0::IntAlu 7748 79.49% 79.50% # Class of committed instruction
532system.cpu.commit.op_class_0::IntMult 3 0.03% 79.53% # Class of committed instruction
533system.cpu.commit.op_class_0::IntDiv 7 0.07% 79.60% # Class of committed instruction
534system.cpu.commit.op_class_0::FloatAdd 0 0.00% 79.60% # Class of committed instruction
535system.cpu.commit.op_class_0::FloatCmp 0 0.00% 79.60% # Class of committed instruction
536system.cpu.commit.op_class_0::FloatCvt 0 0.00% 79.60% # Class of committed instruction
537system.cpu.commit.op_class_0::FloatMult 0 0.00% 79.60% # Class of committed instruction
|
| 538system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 79.60% # Class of committed instruction
|
530system.cpu.commit.op_class_0::FloatDiv 0 0.00% 79.60% # Class of committed instruction
| 539system.cpu.commit.op_class_0::FloatDiv 0 0.00% 79.60% # Class of committed instruction
|
| 540system.cpu.commit.op_class_0::FloatMisc 0 0.00% 79.60% # Class of committed instruction
|
531system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 79.60% # Class of committed instruction
532system.cpu.commit.op_class_0::SimdAdd 0 0.00% 79.60% # Class of committed instruction
533system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 79.60% # Class of committed instruction
534system.cpu.commit.op_class_0::SimdAlu 0 0.00% 79.60% # Class of committed instruction
535system.cpu.commit.op_class_0::SimdCmp 0 0.00% 79.60% # Class of committed instruction
536system.cpu.commit.op_class_0::SimdCvt 0 0.00% 79.60% # Class of committed instruction
537system.cpu.commit.op_class_0::SimdMisc 0 0.00% 79.60% # Class of committed instruction
538system.cpu.commit.op_class_0::SimdMult 0 0.00% 79.60% # Class of committed instruction
539system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 79.60% # Class of committed instruction
540system.cpu.commit.op_class_0::SimdShift 0 0.00% 79.60% # Class of committed instruction
541system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 79.60% # Class of committed instruction
542system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 79.60% # Class of committed instruction
543system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 79.60% # Class of committed instruction
544system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 79.60% # Class of committed instruction
545system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 79.60% # Class of committed instruction
546system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 79.60% # Class of committed instruction
547system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 79.60% # Class of committed instruction
548system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 79.60% # Class of committed instruction
549system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction
550system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction
551system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction
552system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction
553system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction
| 541system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 79.60% # Class of committed instruction
542system.cpu.commit.op_class_0::SimdAdd 0 0.00% 79.60% # Class of committed instruction
543system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 79.60% # Class of committed instruction
544system.cpu.commit.op_class_0::SimdAlu 0 0.00% 79.60% # Class of committed instruction
545system.cpu.commit.op_class_0::SimdCmp 0 0.00% 79.60% # Class of committed instruction
546system.cpu.commit.op_class_0::SimdCvt 0 0.00% 79.60% # Class of committed instruction
547system.cpu.commit.op_class_0::SimdMisc 0 0.00% 79.60% # Class of committed instruction
548system.cpu.commit.op_class_0::SimdMult 0 0.00% 79.60% # Class of committed instruction
549system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 79.60% # Class of committed instruction
550system.cpu.commit.op_class_0::SimdShift 0 0.00% 79.60% # Class of committed instruction
551system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 79.60% # Class of committed instruction
552system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 79.60% # Class of committed instruction
553system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 79.60% # Class of committed instruction
554system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 79.60% # Class of committed instruction
555system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 79.60% # Class of committed instruction
556system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 79.60% # Class of committed instruction
557system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 79.60% # Class of committed instruction
558system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 79.60% # Class of committed instruction
559system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction
560system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction
561system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction
562system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction
563system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction
|
| 564system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
565system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
|
554system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
555system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
556system.cpu.commit.op_class_0::total 9747 # Class of committed instruction
557system.cpu.commit.bw_lim_events 248 # number cycles where commit BW limit reached
558system.cpu.rob.rob_reads 44342 # The number of ROB reads
559system.cpu.rob.rob_writes 45672 # The number of ROB writes
560system.cpu.timesIdled 156 # Number of times that the entire CPU went into an idle state and unscheduled itself
561system.cpu.idleCycles 20098 # Total number of cycles that the CPU has spent unscheduled due to idling
562system.cpu.committedInsts 5380 # Number of Instructions Simulated
563system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
564system.cpu.cpi 8.352045 # CPI: Cycles Per Instruction
565system.cpu.cpi_total 8.352045 # CPI: Total CPI of All Threads
566system.cpu.ipc 0.119731 # IPC: Instructions Per Cycle
567system.cpu.ipc_total 0.119731 # IPC: Total IPC of All Threads
568system.cpu.int_regfile_reads 21663 # number of integer regfile reads
569system.cpu.int_regfile_writes 13219 # number of integer regfile writes
570system.cpu.fp_regfile_reads 4 # number of floating regfile reads
571system.cpu.cc_regfile_reads 8286 # number of cc regfile reads
572system.cpu.cc_regfile_writes 5066 # number of cc regfile writes
573system.cpu.misc_regfile_reads 7640 # number of misc regfile reads
574system.cpu.misc_regfile_writes 1 # number of misc regfile writes
575system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
576system.cpu.dcache.tags.replacements 0 # number of replacements
577system.cpu.dcache.tags.tagsinuse 81.537714 # Cycle average of tags in use
578system.cpu.dcache.tags.total_refs 2520 # Total number of references to valid blocks.
579system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
580system.cpu.dcache.tags.avg_refs 17.872340 # Average number of references to valid blocks.
581system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
582system.cpu.dcache.tags.occ_blocks::cpu.data 81.537714 # Average occupied blocks per requestor
583system.cpu.dcache.tags.occ_percent::cpu.data 0.019907 # Average percentage of cache occupancy
584system.cpu.dcache.tags.occ_percent::total 0.019907 # Average percentage of cache occupancy
585system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
586system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
587system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id
588system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
589system.cpu.dcache.tags.tag_accesses 5567 # Number of tag accesses
590system.cpu.dcache.tags.data_accesses 5567 # Number of data accesses
591system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
592system.cpu.dcache.ReadReq_hits::cpu.data 1661 # number of ReadReq hits
593system.cpu.dcache.ReadReq_hits::total 1661 # number of ReadReq hits
594system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits
595system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits
596system.cpu.dcache.demand_hits::cpu.data 2520 # number of demand (read+write) hits
597system.cpu.dcache.demand_hits::total 2520 # number of demand (read+write) hits
598system.cpu.dcache.overall_hits::cpu.data 2520 # number of overall hits
599system.cpu.dcache.overall_hits::total 2520 # number of overall hits
600system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses
601system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses
602system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
603system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
604system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses
605system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses
606system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses
607system.cpu.dcache.overall_misses::total 193 # number of overall misses
608system.cpu.dcache.ReadReq_miss_latency::cpu.data 10226000 # number of ReadReq miss cycles
609system.cpu.dcache.ReadReq_miss_latency::total 10226000 # number of ReadReq miss cycles
610system.cpu.dcache.WriteReq_miss_latency::cpu.data 7070500 # number of WriteReq miss cycles
611system.cpu.dcache.WriteReq_miss_latency::total 7070500 # number of WriteReq miss cycles
612system.cpu.dcache.demand_miss_latency::cpu.data 17296500 # number of demand (read+write) miss cycles
613system.cpu.dcache.demand_miss_latency::total 17296500 # number of demand (read+write) miss cycles
614system.cpu.dcache.overall_miss_latency::cpu.data 17296500 # number of overall miss cycles
615system.cpu.dcache.overall_miss_latency::total 17296500 # number of overall miss cycles
616system.cpu.dcache.ReadReq_accesses::cpu.data 1778 # number of ReadReq accesses(hits+misses)
617system.cpu.dcache.ReadReq_accesses::total 1778 # number of ReadReq accesses(hits+misses)
618system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
619system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
620system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses
621system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses
622system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses
623system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses
624system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065804 # miss rate for ReadReq accesses
625system.cpu.dcache.ReadReq_miss_rate::total 0.065804 # miss rate for ReadReq accesses
626system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses
627system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses
628system.cpu.dcache.demand_miss_rate::cpu.data 0.071139 # miss rate for demand accesses
629system.cpu.dcache.demand_miss_rate::total 0.071139 # miss rate for demand accesses
630system.cpu.dcache.overall_miss_rate::cpu.data 0.071139 # miss rate for overall accesses
631system.cpu.dcache.overall_miss_rate::total 0.071139 # miss rate for overall accesses
632system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87401.709402 # average ReadReq miss latency
633system.cpu.dcache.ReadReq_avg_miss_latency::total 87401.709402 # average ReadReq miss latency
634system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93032.894737 # average WriteReq miss latency
635system.cpu.dcache.WriteReq_avg_miss_latency::total 93032.894737 # average WriteReq miss latency
636system.cpu.dcache.demand_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency
637system.cpu.dcache.demand_avg_miss_latency::total 89619.170984 # average overall miss latency
638system.cpu.dcache.overall_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency
639system.cpu.dcache.overall_avg_miss_latency::total 89619.170984 # average overall miss latency
640system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked
641system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
642system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
643system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
644system.cpu.dcache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked
645system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
646system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits
647system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits
648system.cpu.dcache.demand_mshr_hits::cpu.data 52 # number of demand (read+write) MSHR hits
649system.cpu.dcache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits
650system.cpu.dcache.overall_mshr_hits::cpu.data 52 # number of overall MSHR hits
651system.cpu.dcache.overall_mshr_hits::total 52 # number of overall MSHR hits
652system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
653system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses
654system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
655system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
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657system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
658system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
659system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
660system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6448000 # number of ReadReq MSHR miss cycles
661system.cpu.dcache.ReadReq_mshr_miss_latency::total 6448000 # number of ReadReq MSHR miss cycles
662system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6994500 # number of WriteReq MSHR miss cycles
663system.cpu.dcache.WriteReq_mshr_miss_latency::total 6994500 # number of WriteReq MSHR miss cycles
664system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13442500 # number of demand (read+write) MSHR miss cycles
665system.cpu.dcache.demand_mshr_miss_latency::total 13442500 # number of demand (read+write) MSHR miss cycles
666system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13442500 # number of overall MSHR miss cycles
667system.cpu.dcache.overall_mshr_miss_latency::total 13442500 # number of overall MSHR miss cycles
668system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036558 # mshr miss rate for ReadReq accesses
669system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036558 # mshr miss rate for ReadReq accesses
670system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses
671system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses
672system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for demand accesses
673system.cpu.dcache.demand_mshr_miss_rate::total 0.051972 # mshr miss rate for demand accesses
674system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for overall accesses
675system.cpu.dcache.overall_mshr_miss_rate::total 0.051972 # mshr miss rate for overall accesses
676system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99200 # average ReadReq mshr miss latency
677system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99200 # average ReadReq mshr miss latency
678system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92032.894737 # average WriteReq mshr miss latency
679system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92032.894737 # average WriteReq mshr miss latency
680system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency
681system.cpu.dcache.demand_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency
682system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency
683system.cpu.dcache.overall_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency
684system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
685system.cpu.icache.tags.replacements 0 # number of replacements
686system.cpu.icache.tags.tagsinuse 130.260906 # Cycle average of tags in use
687system.cpu.icache.tags.total_refs 1641 # Total number of references to valid blocks.
688system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks.
689system.cpu.icache.tags.avg_refs 5.902878 # Average number of references to valid blocks.
690system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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693system.cpu.icache.tags.occ_percent::total 0.063604 # Average percentage of cache occupancy
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695system.cpu.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id
696system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
697system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id
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699system.cpu.icache.tags.data_accesses 4330 # Number of data accesses
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702system.cpu.icache.ReadReq_hits::total 1641 # number of ReadReq hits
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708system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses
709system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses
710system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses
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712system.cpu.icache.overall_misses::total 385 # number of overall misses
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714system.cpu.icache.ReadReq_miss_latency::total 30146000 # number of ReadReq miss cycles
715system.cpu.icache.demand_miss_latency::cpu.inst 30146000 # number of demand (read+write) miss cycles
716system.cpu.icache.demand_miss_latency::total 30146000 # number of demand (read+write) miss cycles
717system.cpu.icache.overall_miss_latency::cpu.inst 30146000 # number of overall miss cycles
718system.cpu.icache.overall_miss_latency::total 30146000 # number of overall miss cycles
719system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses)
720system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses)
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722system.cpu.icache.demand_accesses::total 2026 # number of demand (read+write) accesses
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724system.cpu.icache.overall_accesses::total 2026 # number of overall (read+write) accesses
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726system.cpu.icache.ReadReq_miss_rate::total 0.190030 # miss rate for ReadReq accesses
727system.cpu.icache.demand_miss_rate::cpu.inst 0.190030 # miss rate for demand accesses
728system.cpu.icache.demand_miss_rate::total 0.190030 # miss rate for demand accesses
729system.cpu.icache.overall_miss_rate::cpu.inst 0.190030 # miss rate for overall accesses
730system.cpu.icache.overall_miss_rate::total 0.190030 # miss rate for overall accesses
731system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78301.298701 # average ReadReq miss latency
732system.cpu.icache.ReadReq_avg_miss_latency::total 78301.298701 # average ReadReq miss latency
733system.cpu.icache.demand_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency
734system.cpu.icache.demand_avg_miss_latency::total 78301.298701 # average overall miss latency
735system.cpu.icache.overall_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency
736system.cpu.icache.overall_avg_miss_latency::total 78301.298701 # average overall miss latency
737system.cpu.icache.blocked_cycles::no_mshrs 171 # number of cycles access was blocked
738system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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742system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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744system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits
745system.cpu.icache.demand_mshr_hits::cpu.inst 107 # number of demand (read+write) MSHR hits
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748system.cpu.icache.overall_mshr_hits::total 107 # number of overall MSHR hits
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750system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses
751system.cpu.icache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
752system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses
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754system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses
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759system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23206500 # number of overall MSHR miss cycles
760system.cpu.icache.overall_mshr_miss_latency::total 23206500 # number of overall MSHR miss cycles
761system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for ReadReq accesses
762system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137216 # mshr miss rate for ReadReq accesses
763system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for demand accesses
764system.cpu.icache.demand_mshr_miss_rate::total 0.137216 # mshr miss rate for demand accesses
765system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for overall accesses
766system.cpu.icache.overall_mshr_miss_rate::total 0.137216 # mshr miss rate for overall accesses
767system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83476.618705 # average ReadReq mshr miss latency
768system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83476.618705 # average ReadReq mshr miss latency
769system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency
770system.cpu.icache.demand_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency
771system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency
772system.cpu.icache.overall_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency
773system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
774system.cpu.l2cache.tags.replacements 0 # number of replacements
775system.cpu.l2cache.tags.tagsinuse 211.897546 # Cycle average of tags in use
776system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
777system.cpu.l2cache.tags.sampled_refs 418 # Sample count of references to valid blocks.
778system.cpu.l2cache.tags.avg_refs 0.002392 # Average number of references to valid blocks.
779system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
780system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.293933 # Average occupied blocks per requestor
781system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603612 # Average occupied blocks per requestor
782system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003976 # Average percentage of cache occupancy
783system.cpu.l2cache.tags.occ_percent::cpu.data 0.002490 # Average percentage of cache occupancy
784system.cpu.l2cache.tags.occ_percent::total 0.006467 # Average percentage of cache occupancy
785system.cpu.l2cache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id
786system.cpu.l2cache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id
787system.cpu.l2cache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
788system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012756 # Percentage of cache occupancy per task id
789system.cpu.l2cache.tags.tag_accesses 3770 # Number of tag accesses
790system.cpu.l2cache.tags.data_accesses 3770 # Number of data accesses
791system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
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793system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
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799system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses
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801system.cpu.l2cache.ReadCleanReq_misses::total 277 # number of ReadCleanReq misses
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803system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses
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855system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency
856system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency
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863system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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867system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses
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871system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
872system.cpu.l2cache.demand_mshr_misses::total 418 # number of demand (read+write) MSHR misses
873system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses
874system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
875system.cpu.l2cache.overall_mshr_misses::total 418 # number of overall MSHR misses
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879system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20007500 # number of ReadCleanReq MSHR miss cycles
880system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5700000 # number of ReadSharedReq MSHR miss cycles
881system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5700000 # number of ReadSharedReq MSHR miss cycles
882system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20007500 # number of demand (read+write) MSHR miss cycles
883system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11820500 # number of demand (read+write) MSHR miss cycles
884system.cpu.l2cache.demand_mshr_miss_latency::total 31828000 # number of demand (read+write) MSHR miss cycles
885system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20007500 # number of overall MSHR miss cycles
886system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11820500 # number of overall MSHR miss cycles
887system.cpu.l2cache.overall_mshr_miss_latency::total 31828000 # number of overall MSHR miss cycles
888system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
889system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
890system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses
891system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996403 # mshr miss rate for ReadCleanReq accesses
892system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
893system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
894system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses
895system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
896system.cpu.l2cache.demand_mshr_miss_rate::total 0.997613 # mshr miss rate for demand accesses
897system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses
898system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
899system.cpu.l2cache.overall_mshr_miss_rate::total 0.997613 # mshr miss rate for overall accesses
900system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80532.894737 # average ReadExReq mshr miss latency
901system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80532.894737 # average ReadExReq mshr miss latency
902system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72229.241877 # average ReadCleanReq mshr miss latency
903system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72229.241877 # average ReadCleanReq mshr miss latency
904system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87692.307692 # average ReadSharedReq mshr miss latency
905system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87692.307692 # average ReadSharedReq mshr miss latency
906system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency
907system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency
908system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency
909system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency
910system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency
911system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency
912system.cpu.toL2Bus.snoop_filter.tot_requests 419 # Total number of requests made to the snoop filter.
913system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
914system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
915system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
916system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
917system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
918system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
919system.cpu.toL2Bus.trans_dist::ReadResp 343 # Transaction distribution
920system.cpu.toL2Bus.trans_dist::ReadExReq 76 # Transaction distribution
921system.cpu.toL2Bus.trans_dist::ReadExResp 76 # Transaction distribution
922system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution
923system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution
924system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes)
925system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
926system.cpu.toL2Bus.pkt_count::total 838 # Packet count per connected master and slave (bytes)
927system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes)
928system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
929system.cpu.toL2Bus.pkt_size::total 26816 # Cumulative packet size per connected master and slave (bytes)
930system.cpu.toL2Bus.snoops 0 # Total snoops (count)
931system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
932system.cpu.toL2Bus.snoop_fanout::samples 419 # Request fanout histogram
933system.cpu.toL2Bus.snoop_fanout::mean 0.002387 # Request fanout histogram
934system.cpu.toL2Bus.snoop_fanout::stdev 0.048853 # Request fanout histogram
935system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
936system.cpu.toL2Bus.snoop_fanout::0 418 99.76% 99.76% # Request fanout histogram
937system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram
938system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
939system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
940system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
941system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
942system.cpu.toL2Bus.snoop_fanout::total 419 # Request fanout histogram
943system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks)
944system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
945system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks)
946system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
947system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
948system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
949system.membus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter.
950system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
951system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
952system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
953system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
954system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
955system.membus.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
956system.membus.trans_dist::ReadResp 342 # Transaction distribution
957system.membus.trans_dist::ReadExReq 76 # Transaction distribution
958system.membus.trans_dist::ReadExResp 76 # Transaction distribution
959system.membus.trans_dist::ReadSharedReq 342 # Transaction distribution
960system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836 # Packet count per connected master and slave (bytes)
961system.membus.pkt_count_system.cpu.l2cache.mem_side::total 836 # Packet count per connected master and slave (bytes)
962system.membus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
963system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26752 # Cumulative packet size per connected master and slave (bytes)
964system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26752 # Cumulative packet size per connected master and slave (bytes)
965system.membus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
966system.membus.snoops 0 # Total snoops (count)
967system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
968system.membus.snoop_fanout::samples 418 # Request fanout histogram
969system.membus.snoop_fanout::mean 0 # Request fanout histogram
970system.membus.snoop_fanout::stdev 0 # Request fanout histogram
971system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
972system.membus.snoop_fanout::0 418 100.00% 100.00% # Request fanout histogram
973system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
974system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
975system.membus.snoop_fanout::min_value 0 # Request fanout histogram
976system.membus.snoop_fanout::max_value 0 # Request fanout histogram
977system.membus.snoop_fanout::total 418 # Request fanout histogram
978system.membus.reqLayer0.occupancy 506000 # Layer occupancy (ticks)
979system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
980system.membus.respLayer1.occupancy 2231250 # Layer occupancy (ticks)
981system.membus.respLayer1.utilization 9.9 # Layer utilization (%)
982
983---------- End Simulation Statistics ----------
| 566system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
567system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
568system.cpu.commit.op_class_0::total 9747 # Class of committed instruction
569system.cpu.commit.bw_lim_events 248 # number cycles where commit BW limit reached
570system.cpu.rob.rob_reads 44342 # The number of ROB reads
571system.cpu.rob.rob_writes 45672 # The number of ROB writes
572system.cpu.timesIdled 156 # Number of times that the entire CPU went into an idle state and unscheduled itself
573system.cpu.idleCycles 20098 # Total number of cycles that the CPU has spent unscheduled due to idling
574system.cpu.committedInsts 5380 # Number of Instructions Simulated
575system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
576system.cpu.cpi 8.352045 # CPI: Cycles Per Instruction
577system.cpu.cpi_total 8.352045 # CPI: Total CPI of All Threads
578system.cpu.ipc 0.119731 # IPC: Instructions Per Cycle
579system.cpu.ipc_total 0.119731 # IPC: Total IPC of All Threads
580system.cpu.int_regfile_reads 21663 # number of integer regfile reads
581system.cpu.int_regfile_writes 13219 # number of integer regfile writes
582system.cpu.fp_regfile_reads 4 # number of floating regfile reads
583system.cpu.cc_regfile_reads 8286 # number of cc regfile reads
584system.cpu.cc_regfile_writes 5066 # number of cc regfile writes
585system.cpu.misc_regfile_reads 7640 # number of misc regfile reads
586system.cpu.misc_regfile_writes 1 # number of misc regfile writes
587system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
588system.cpu.dcache.tags.replacements 0 # number of replacements
589system.cpu.dcache.tags.tagsinuse 81.537714 # Cycle average of tags in use
590system.cpu.dcache.tags.total_refs 2520 # Total number of references to valid blocks.
591system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
592system.cpu.dcache.tags.avg_refs 17.872340 # Average number of references to valid blocks.
593system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
594system.cpu.dcache.tags.occ_blocks::cpu.data 81.537714 # Average occupied blocks per requestor
595system.cpu.dcache.tags.occ_percent::cpu.data 0.019907 # Average percentage of cache occupancy
596system.cpu.dcache.tags.occ_percent::total 0.019907 # Average percentage of cache occupancy
597system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
598system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
599system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id
600system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
601system.cpu.dcache.tags.tag_accesses 5567 # Number of tag accesses
602system.cpu.dcache.tags.data_accesses 5567 # Number of data accesses
603system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
604system.cpu.dcache.ReadReq_hits::cpu.data 1661 # number of ReadReq hits
605system.cpu.dcache.ReadReq_hits::total 1661 # number of ReadReq hits
606system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits
607system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits
608system.cpu.dcache.demand_hits::cpu.data 2520 # number of demand (read+write) hits
609system.cpu.dcache.demand_hits::total 2520 # number of demand (read+write) hits
610system.cpu.dcache.overall_hits::cpu.data 2520 # number of overall hits
611system.cpu.dcache.overall_hits::total 2520 # number of overall hits
612system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses
613system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses
614system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
615system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
616system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses
617system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses
618system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses
619system.cpu.dcache.overall_misses::total 193 # number of overall misses
620system.cpu.dcache.ReadReq_miss_latency::cpu.data 10226000 # number of ReadReq miss cycles
621system.cpu.dcache.ReadReq_miss_latency::total 10226000 # number of ReadReq miss cycles
622system.cpu.dcache.WriteReq_miss_latency::cpu.data 7070500 # number of WriteReq miss cycles
623system.cpu.dcache.WriteReq_miss_latency::total 7070500 # number of WriteReq miss cycles
624system.cpu.dcache.demand_miss_latency::cpu.data 17296500 # number of demand (read+write) miss cycles
625system.cpu.dcache.demand_miss_latency::total 17296500 # number of demand (read+write) miss cycles
626system.cpu.dcache.overall_miss_latency::cpu.data 17296500 # number of overall miss cycles
627system.cpu.dcache.overall_miss_latency::total 17296500 # number of overall miss cycles
628system.cpu.dcache.ReadReq_accesses::cpu.data 1778 # number of ReadReq accesses(hits+misses)
629system.cpu.dcache.ReadReq_accesses::total 1778 # number of ReadReq accesses(hits+misses)
630system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
631system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
632system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses
633system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses
634system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses
635system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses
636system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065804 # miss rate for ReadReq accesses
637system.cpu.dcache.ReadReq_miss_rate::total 0.065804 # miss rate for ReadReq accesses
638system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses
639system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses
640system.cpu.dcache.demand_miss_rate::cpu.data 0.071139 # miss rate for demand accesses
641system.cpu.dcache.demand_miss_rate::total 0.071139 # miss rate for demand accesses
642system.cpu.dcache.overall_miss_rate::cpu.data 0.071139 # miss rate for overall accesses
643system.cpu.dcache.overall_miss_rate::total 0.071139 # miss rate for overall accesses
644system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87401.709402 # average ReadReq miss latency
645system.cpu.dcache.ReadReq_avg_miss_latency::total 87401.709402 # average ReadReq miss latency
646system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93032.894737 # average WriteReq miss latency
647system.cpu.dcache.WriteReq_avg_miss_latency::total 93032.894737 # average WriteReq miss latency
648system.cpu.dcache.demand_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency
649system.cpu.dcache.demand_avg_miss_latency::total 89619.170984 # average overall miss latency
650system.cpu.dcache.overall_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency
651system.cpu.dcache.overall_avg_miss_latency::total 89619.170984 # average overall miss latency
652system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked
653system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
654system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
655system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
656system.cpu.dcache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked
657system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
658system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits
659system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits
660system.cpu.dcache.demand_mshr_hits::cpu.data 52 # number of demand (read+write) MSHR hits
661system.cpu.dcache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits
662system.cpu.dcache.overall_mshr_hits::cpu.data 52 # number of overall MSHR hits
663system.cpu.dcache.overall_mshr_hits::total 52 # number of overall MSHR hits
664system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
665system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses
666system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
667system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
668system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
669system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
670system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
671system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
672system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6448000 # number of ReadReq MSHR miss cycles
673system.cpu.dcache.ReadReq_mshr_miss_latency::total 6448000 # number of ReadReq MSHR miss cycles
674system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6994500 # number of WriteReq MSHR miss cycles
675system.cpu.dcache.WriteReq_mshr_miss_latency::total 6994500 # number of WriteReq MSHR miss cycles
676system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13442500 # number of demand (read+write) MSHR miss cycles
677system.cpu.dcache.demand_mshr_miss_latency::total 13442500 # number of demand (read+write) MSHR miss cycles
678system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13442500 # number of overall MSHR miss cycles
679system.cpu.dcache.overall_mshr_miss_latency::total 13442500 # number of overall MSHR miss cycles
680system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036558 # mshr miss rate for ReadReq accesses
681system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036558 # mshr miss rate for ReadReq accesses
682system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses
683system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses
684system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for demand accesses
685system.cpu.dcache.demand_mshr_miss_rate::total 0.051972 # mshr miss rate for demand accesses
686system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for overall accesses
687system.cpu.dcache.overall_mshr_miss_rate::total 0.051972 # mshr miss rate for overall accesses
688system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99200 # average ReadReq mshr miss latency
689system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99200 # average ReadReq mshr miss latency
690system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92032.894737 # average WriteReq mshr miss latency
691system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92032.894737 # average WriteReq mshr miss latency
692system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency
693system.cpu.dcache.demand_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency
694system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency
695system.cpu.dcache.overall_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency
696system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
697system.cpu.icache.tags.replacements 0 # number of replacements
698system.cpu.icache.tags.tagsinuse 130.260906 # Cycle average of tags in use
699system.cpu.icache.tags.total_refs 1641 # Total number of references to valid blocks.
700system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks.
701system.cpu.icache.tags.avg_refs 5.902878 # Average number of references to valid blocks.
702system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
703system.cpu.icache.tags.occ_blocks::cpu.inst 130.260906 # Average occupied blocks per requestor
704system.cpu.icache.tags.occ_percent::cpu.inst 0.063604 # Average percentage of cache occupancy
705system.cpu.icache.tags.occ_percent::total 0.063604 # Average percentage of cache occupancy
706system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id
707system.cpu.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id
708system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
709system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id
710system.cpu.icache.tags.tag_accesses 4330 # Number of tag accesses
711system.cpu.icache.tags.data_accesses 4330 # Number of data accesses
712system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
713system.cpu.icache.ReadReq_hits::cpu.inst 1641 # number of ReadReq hits
714system.cpu.icache.ReadReq_hits::total 1641 # number of ReadReq hits
715system.cpu.icache.demand_hits::cpu.inst 1641 # number of demand (read+write) hits
716system.cpu.icache.demand_hits::total 1641 # number of demand (read+write) hits
717system.cpu.icache.overall_hits::cpu.inst 1641 # number of overall hits
718system.cpu.icache.overall_hits::total 1641 # number of overall hits
719system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses
720system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses
721system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses
722system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses
723system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses
724system.cpu.icache.overall_misses::total 385 # number of overall misses
725system.cpu.icache.ReadReq_miss_latency::cpu.inst 30146000 # number of ReadReq miss cycles
726system.cpu.icache.ReadReq_miss_latency::total 30146000 # number of ReadReq miss cycles
727system.cpu.icache.demand_miss_latency::cpu.inst 30146000 # number of demand (read+write) miss cycles
728system.cpu.icache.demand_miss_latency::total 30146000 # number of demand (read+write) miss cycles
729system.cpu.icache.overall_miss_latency::cpu.inst 30146000 # number of overall miss cycles
730system.cpu.icache.overall_miss_latency::total 30146000 # number of overall miss cycles
731system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses)
732system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses)
733system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses
734system.cpu.icache.demand_accesses::total 2026 # number of demand (read+write) accesses
735system.cpu.icache.overall_accesses::cpu.inst 2026 # number of overall (read+write) accesses
736system.cpu.icache.overall_accesses::total 2026 # number of overall (read+write) accesses
737system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190030 # miss rate for ReadReq accesses
738system.cpu.icache.ReadReq_miss_rate::total 0.190030 # miss rate for ReadReq accesses
739system.cpu.icache.demand_miss_rate::cpu.inst 0.190030 # miss rate for demand accesses
740system.cpu.icache.demand_miss_rate::total 0.190030 # miss rate for demand accesses
741system.cpu.icache.overall_miss_rate::cpu.inst 0.190030 # miss rate for overall accesses
742system.cpu.icache.overall_miss_rate::total 0.190030 # miss rate for overall accesses
743system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78301.298701 # average ReadReq miss latency
744system.cpu.icache.ReadReq_avg_miss_latency::total 78301.298701 # average ReadReq miss latency
745system.cpu.icache.demand_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency
746system.cpu.icache.demand_avg_miss_latency::total 78301.298701 # average overall miss latency
747system.cpu.icache.overall_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency
748system.cpu.icache.overall_avg_miss_latency::total 78301.298701 # average overall miss latency
749system.cpu.icache.blocked_cycles::no_mshrs 171 # number of cycles access was blocked
750system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
751system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
752system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
753system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked
754system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
755system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # number of ReadReq MSHR hits
756system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits
757system.cpu.icache.demand_mshr_hits::cpu.inst 107 # number of demand (read+write) MSHR hits
758system.cpu.icache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits
759system.cpu.icache.overall_mshr_hits::cpu.inst 107 # number of overall MSHR hits
760system.cpu.icache.overall_mshr_hits::total 107 # number of overall MSHR hits
761system.cpu.icache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
762system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses
763system.cpu.icache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
764system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses
765system.cpu.icache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
766system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses
767system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23206500 # number of ReadReq MSHR miss cycles
768system.cpu.icache.ReadReq_mshr_miss_latency::total 23206500 # number of ReadReq MSHR miss cycles
769system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23206500 # number of demand (read+write) MSHR miss cycles
770system.cpu.icache.demand_mshr_miss_latency::total 23206500 # number of demand (read+write) MSHR miss cycles
771system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23206500 # number of overall MSHR miss cycles
772system.cpu.icache.overall_mshr_miss_latency::total 23206500 # number of overall MSHR miss cycles
773system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for ReadReq accesses
774system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137216 # mshr miss rate for ReadReq accesses
775system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for demand accesses
776system.cpu.icache.demand_mshr_miss_rate::total 0.137216 # mshr miss rate for demand accesses
777system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for overall accesses
778system.cpu.icache.overall_mshr_miss_rate::total 0.137216 # mshr miss rate for overall accesses
779system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83476.618705 # average ReadReq mshr miss latency
780system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83476.618705 # average ReadReq mshr miss latency
781system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency
782system.cpu.icache.demand_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency
783system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency
784system.cpu.icache.overall_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency
785system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
786system.cpu.l2cache.tags.replacements 0 # number of replacements
787system.cpu.l2cache.tags.tagsinuse 211.897546 # Cycle average of tags in use
788system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
789system.cpu.l2cache.tags.sampled_refs 418 # Sample count of references to valid blocks.
790system.cpu.l2cache.tags.avg_refs 0.002392 # Average number of references to valid blocks.
791system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
792system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.293933 # Average occupied blocks per requestor
793system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603612 # Average occupied blocks per requestor
794system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003976 # Average percentage of cache occupancy
795system.cpu.l2cache.tags.occ_percent::cpu.data 0.002490 # Average percentage of cache occupancy
796system.cpu.l2cache.tags.occ_percent::total 0.006467 # Average percentage of cache occupancy
797system.cpu.l2cache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id
798system.cpu.l2cache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id
799system.cpu.l2cache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
800system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012756 # Percentage of cache occupancy per task id
801system.cpu.l2cache.tags.tag_accesses 3770 # Number of tag accesses
802system.cpu.l2cache.tags.data_accesses 3770 # Number of data accesses
803system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
804system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
805system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
806system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
807system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
808system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
809system.cpu.l2cache.overall_hits::total 1 # number of overall hits
810system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses
811system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses
812system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 277 # number of ReadCleanReq misses
813system.cpu.l2cache.ReadCleanReq_misses::total 277 # number of ReadCleanReq misses
814system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses
815system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses
816system.cpu.l2cache.demand_misses::cpu.inst 277 # number of demand (read+write) misses
817system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses
818system.cpu.l2cache.demand_misses::total 418 # number of demand (read+write) misses
819system.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses
820system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses
821system.cpu.l2cache.overall_misses::total 418 # number of overall misses
822system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6880500 # number of ReadExReq miss cycles
823system.cpu.l2cache.ReadExReq_miss_latency::total 6880500 # number of ReadExReq miss cycles
824system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22777500 # number of ReadCleanReq miss cycles
825system.cpu.l2cache.ReadCleanReq_miss_latency::total 22777500 # number of ReadCleanReq miss cycles
826system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6350000 # number of ReadSharedReq miss cycles
827system.cpu.l2cache.ReadSharedReq_miss_latency::total 6350000 # number of ReadSharedReq miss cycles
828system.cpu.l2cache.demand_miss_latency::cpu.inst 22777500 # number of demand (read+write) miss cycles
829system.cpu.l2cache.demand_miss_latency::cpu.data 13230500 # number of demand (read+write) miss cycles
830system.cpu.l2cache.demand_miss_latency::total 36008000 # number of demand (read+write) miss cycles
831system.cpu.l2cache.overall_miss_latency::cpu.inst 22777500 # number of overall miss cycles
832system.cpu.l2cache.overall_miss_latency::cpu.data 13230500 # number of overall miss cycles
833system.cpu.l2cache.overall_miss_latency::total 36008000 # number of overall miss cycles
834system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses)
835system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses)
836system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 278 # number of ReadCleanReq accesses(hits+misses)
837system.cpu.l2cache.ReadCleanReq_accesses::total 278 # number of ReadCleanReq accesses(hits+misses)
838system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses)
839system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses)
840system.cpu.l2cache.demand_accesses::cpu.inst 278 # number of demand (read+write) accesses
841system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
842system.cpu.l2cache.demand_accesses::total 419 # number of demand (read+write) accesses
843system.cpu.l2cache.overall_accesses::cpu.inst 278 # number of overall (read+write) accesses
844system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
845system.cpu.l2cache.overall_accesses::total 419 # number of overall (read+write) accesses
846system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
847system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
848system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996403 # miss rate for ReadCleanReq accesses
849system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996403 # miss rate for ReadCleanReq accesses
850system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
851system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
852system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996403 # miss rate for demand accesses
853system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
854system.cpu.l2cache.demand_miss_rate::total 0.997613 # miss rate for demand accesses
855system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996403 # miss rate for overall accesses
856system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
857system.cpu.l2cache.overall_miss_rate::total 0.997613 # miss rate for overall accesses
858system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90532.894737 # average ReadExReq miss latency
859system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90532.894737 # average ReadExReq miss latency
860system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82229.241877 # average ReadCleanReq miss latency
861system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82229.241877 # average ReadCleanReq miss latency
862system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97692.307692 # average ReadSharedReq miss latency
863system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 97692.307692 # average ReadSharedReq miss latency
864system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency
865system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency
866system.cpu.l2cache.demand_avg_miss_latency::total 86143.540670 # average overall miss latency
867system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency
868system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency
869system.cpu.l2cache.overall_avg_miss_latency::total 86143.540670 # average overall miss latency
870system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
871system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
872system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
873system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
874system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
875system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
876system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses
877system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses
878system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses
879system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses
880system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses
881system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses
882system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses
883system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
884system.cpu.l2cache.demand_mshr_misses::total 418 # number of demand (read+write) MSHR misses
885system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses
886system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
887system.cpu.l2cache.overall_mshr_misses::total 418 # number of overall MSHR misses
888system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6120500 # number of ReadExReq MSHR miss cycles
889system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6120500 # number of ReadExReq MSHR miss cycles
890system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20007500 # number of ReadCleanReq MSHR miss cycles
891system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20007500 # number of ReadCleanReq MSHR miss cycles
892system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5700000 # number of ReadSharedReq MSHR miss cycles
893system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5700000 # number of ReadSharedReq MSHR miss cycles
894system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20007500 # number of demand (read+write) MSHR miss cycles
895system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11820500 # number of demand (read+write) MSHR miss cycles
896system.cpu.l2cache.demand_mshr_miss_latency::total 31828000 # number of demand (read+write) MSHR miss cycles
897system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20007500 # number of overall MSHR miss cycles
898system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11820500 # number of overall MSHR miss cycles
899system.cpu.l2cache.overall_mshr_miss_latency::total 31828000 # number of overall MSHR miss cycles
900system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
901system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
902system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses
903system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996403 # mshr miss rate for ReadCleanReq accesses
904system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
905system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
906system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses
907system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
908system.cpu.l2cache.demand_mshr_miss_rate::total 0.997613 # mshr miss rate for demand accesses
909system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses
910system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
911system.cpu.l2cache.overall_mshr_miss_rate::total 0.997613 # mshr miss rate for overall accesses
912system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80532.894737 # average ReadExReq mshr miss latency
913system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80532.894737 # average ReadExReq mshr miss latency
914system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72229.241877 # average ReadCleanReq mshr miss latency
915system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72229.241877 # average ReadCleanReq mshr miss latency
916system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87692.307692 # average ReadSharedReq mshr miss latency
917system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87692.307692 # average ReadSharedReq mshr miss latency
918system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency
919system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency
920system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency
921system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency
922system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency
923system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency
924system.cpu.toL2Bus.snoop_filter.tot_requests 419 # Total number of requests made to the snoop filter.
925system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
926system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
927system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
928system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
929system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
930system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
931system.cpu.toL2Bus.trans_dist::ReadResp 343 # Transaction distribution
932system.cpu.toL2Bus.trans_dist::ReadExReq 76 # Transaction distribution
933system.cpu.toL2Bus.trans_dist::ReadExResp 76 # Transaction distribution
934system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution
935system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution
936system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes)
937system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
938system.cpu.toL2Bus.pkt_count::total 838 # Packet count per connected master and slave (bytes)
939system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes)
940system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
941system.cpu.toL2Bus.pkt_size::total 26816 # Cumulative packet size per connected master and slave (bytes)
942system.cpu.toL2Bus.snoops 0 # Total snoops (count)
943system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
944system.cpu.toL2Bus.snoop_fanout::samples 419 # Request fanout histogram
945system.cpu.toL2Bus.snoop_fanout::mean 0.002387 # Request fanout histogram
946system.cpu.toL2Bus.snoop_fanout::stdev 0.048853 # Request fanout histogram
947system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
948system.cpu.toL2Bus.snoop_fanout::0 418 99.76% 99.76% # Request fanout histogram
949system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram
950system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
951system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
952system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
953system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
954system.cpu.toL2Bus.snoop_fanout::total 419 # Request fanout histogram
955system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks)
956system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
957system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks)
958system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
959system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
960system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
961system.membus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter.
962system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
963system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
964system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
965system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
966system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
967system.membus.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
968system.membus.trans_dist::ReadResp 342 # Transaction distribution
969system.membus.trans_dist::ReadExReq 76 # Transaction distribution
970system.membus.trans_dist::ReadExResp 76 # Transaction distribution
971system.membus.trans_dist::ReadSharedReq 342 # Transaction distribution
972system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836 # Packet count per connected master and slave (bytes)
973system.membus.pkt_count_system.cpu.l2cache.mem_side::total 836 # Packet count per connected master and slave (bytes)
974system.membus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
975system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26752 # Cumulative packet size per connected master and slave (bytes)
976system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26752 # Cumulative packet size per connected master and slave (bytes)
977system.membus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
978system.membus.snoops 0 # Total snoops (count)
979system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
980system.membus.snoop_fanout::samples 418 # Request fanout histogram
981system.membus.snoop_fanout::mean 0 # Request fanout histogram
982system.membus.snoop_fanout::stdev 0 # Request fanout histogram
983system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
984system.membus.snoop_fanout::0 418 100.00% 100.00% # Request fanout histogram
985system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
986system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
987system.membus.snoop_fanout::min_value 0 # Request fanout histogram
988system.membus.snoop_fanout::max_value 0 # Request fanout histogram
989system.membus.snoop_fanout::total 418 # Request fanout histogram
990system.membus.reqLayer0.occupancy 506000 # Layer occupancy (ticks)
991system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
992system.membus.respLayer1.occupancy 2231250 # Layer occupancy (ticks)
993system.membus.respLayer1.utilization 9.9 # Layer utilization (%)
994
995---------- End Simulation Statistics ----------
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