1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000015 # Number of seconds simulated
4sim_ticks 15014000 # Number of ticks simulated
5final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 32657 # Simulator instruction rate (inst/s)
8host_op_rate 59148 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 91121721 # Simulator tick rate (ticks/s)
10host_mem_usage 223384 # Number of bytes of host memory used
11host_seconds 0.16 # Real time elapsed on the host
12sim_insts 5380 # Number of instructions simulated
13sim_ops 9745 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
16system.physmem.bytes_read::total 28736 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 19392 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 19392 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 449 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1291594512 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 622352471 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 1913946983 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1291594512 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1291594512 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1291594512 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 622352471 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 1913946983 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 450 # Total number of read requests seen
31system.physmem.writeReqs 0 # Total number of write requests seen
32system.physmem.cpureqs 450 # Reqs generatd by CPU via cache - shady
33system.physmem.bytesRead 28736 # Total number of bytes read from memory
34system.physmem.bytesWritten 0 # Total number of bytes written to memory
35system.physmem.bytesConsumedRd 28736 # bytesRead derated as per pkt->getSize()
36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
39system.physmem.perBankRdReqs::0 41 # Track reads on a per bank basis
40system.physmem.perBankRdReqs::1 20 # Track reads on a per bank basis
41system.physmem.perBankRdReqs::2 55 # Track reads on a per bank basis
42system.physmem.perBankRdReqs::3 23 # Track reads on a per bank basis
43system.physmem.perBankRdReqs::4 52 # Track reads on a per bank basis
44system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis
45system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis
46system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::10 29 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::11 39 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis
55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis

--- 6 unchanged lines hidden (view full) ---

65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
73system.physmem.totGap 14992500 # Total gap between requests
74system.physmem.readPktSize::0 0 # Categorize read packet sizes
75system.physmem.readPktSize::1 0 # Categorize read packet sizes
76system.physmem.readPktSize::2 0 # Categorize read packet sizes
77system.physmem.readPktSize::3 0 # Categorize read packet sizes
78system.physmem.readPktSize::4 0 # Categorize read packet sizes
79system.physmem.readPktSize::5 0 # Categorize read packet sizes
80system.physmem.readPktSize::6 450 # Categorize read packet sizes
81system.physmem.readPktSize::7 0 # Categorize read packet sizes
82system.physmem.readPktSize::8 0 # Categorize read packet sizes
83system.physmem.writePktSize::0 0 # categorize write packet sizes
84system.physmem.writePktSize::1 0 # categorize write packet sizes
85system.physmem.writePktSize::2 0 # categorize write packet sizes
86system.physmem.writePktSize::3 0 # categorize write packet sizes
87system.physmem.writePktSize::4 0 # categorize write packet sizes
88system.physmem.writePktSize::5 0 # categorize write packet sizes

--- 5 unchanged lines hidden (view full) ---

94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
101system.physmem.rdQLenPdf::0 230 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see

--- 47 unchanged lines hidden (view full) ---

159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
167system.physmem.totQLat 1656450 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 12024450 # Sum of mem lat for all requests
169system.physmem.totBusLat 1800000 # Total cycles spent in databus access
170system.physmem.totBankLat 8568000 # Total cycles spent in bank access
171system.physmem.avgQLat 3681.00 # Average queueing delay per request
172system.physmem.avgBankLat 19040.00 # Average bank access latency per request
173system.physmem.avgBusLat 4000.00 # Average bus latency per request
174system.physmem.avgMemAccLat 26721.00 # Average memory access latency
175system.physmem.avgRdBW 1913.95 # Average achieved read bandwidth in MB/s
176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
177system.physmem.avgConsumedRdBW 1913.95 # Average consumed read bandwidth in MB/s
178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
180system.physmem.busUtil 11.96 # Data bus utilization in percentage
181system.physmem.avgRdQLen 0.80 # Average read queue length over time
182system.physmem.avgWrQLen 0.00 # Average write queue length over time
183system.physmem.readRowHits 352 # Number of row buffer hits during reads
184system.physmem.writeRowHits 0 # Number of row buffer hits during writes
185system.physmem.readRowHitRate 78.22 # Row buffer hit rate for reads
186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
187system.physmem.avgGap 33316.67 # Average gap between requests
188system.cpu.workload.num_syscalls 11 # Number of system calls
189system.cpu.numCycles 30029 # number of cpu cycles simulated
190system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
191system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
192system.cpu.BPredUnit.lookups 3018 # Number of BP lookups
193system.cpu.BPredUnit.condPredicted 3018 # Number of conditional branches predicted
194system.cpu.BPredUnit.condIncorrect 546 # Number of conditional branches incorrect
195system.cpu.BPredUnit.BTBLookups 2500 # Number of BTB lookups
196system.cpu.BPredUnit.BTBHits 796 # Number of BTB hits
197system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
198system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
199system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
200system.cpu.fetch.icacheStallCycles 8962 # Number of cycles fetch is stalled on an Icache miss
201system.cpu.fetch.Insts 14512 # Number of instructions fetch has processed
202system.cpu.fetch.Branches 3018 # Number of branches that fetch encountered
203system.cpu.fetch.predictedBranches 796 # Number of branches that fetch has predicted taken
204system.cpu.fetch.Cycles 3937 # Number of cycles fetch has run and was not squashing or blocked
205system.cpu.fetch.SquashCycles 2417 # Number of cycles fetch has spent squashing
206system.cpu.fetch.BlockedCycles 3663 # Number of cycles fetch has spent blocked
207system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
208system.cpu.fetch.PendingTrapStallCycles 144 # Number of stall cycles due to pending traps
209system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
210system.cpu.fetch.CacheLines 1880 # Number of cache lines fetched
211system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed
212system.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total)
213system.cpu.fetch.rateDist::mean 1.378572 # Number of instructions fetched each cycle (Total)
214system.cpu.fetch.rateDist::stdev 2.879282 # Number of instructions fetched each cycle (Total)
215system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
216system.cpu.fetch.rateDist::0 14745 79.35% 79.35% # Number of instructions fetched each cycle (Total)
217system.cpu.fetch.rateDist::1 189 1.02% 80.36% # Number of instructions fetched each cycle (Total)
218system.cpu.fetch.rateDist::2 157 0.84% 81.21% # Number of instructions fetched each cycle (Total)
219system.cpu.fetch.rateDist::3 193 1.04% 82.25% # Number of instructions fetched each cycle (Total)
220system.cpu.fetch.rateDist::4 162 0.87% 83.12% # Number of instructions fetched each cycle (Total)
221system.cpu.fetch.rateDist::5 175 0.94% 84.06% # Number of instructions fetched each cycle (Total)
222system.cpu.fetch.rateDist::6 261 1.40% 85.47% # Number of instructions fetched each cycle (Total)
223system.cpu.fetch.rateDist::7 161 0.87% 86.33% # Number of instructions fetched each cycle (Total)
224system.cpu.fetch.rateDist::8 2540 13.67% 100.00% # Number of instructions fetched each cycle (Total)
225system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
226system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
227system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
228system.cpu.fetch.rateDist::total 18583 # Number of instructions fetched each cycle (Total)
229system.cpu.fetch.branchRate 0.100503 # Number of branch fetches per cycle
230system.cpu.fetch.rate 0.483266 # Number of inst fetches per cycle
231system.cpu.decode.IdleCycles 9455 # Number of cycles decode is idle
232system.cpu.decode.BlockedCycles 3616 # Number of cycles decode is blocked
233system.cpu.decode.RunCycles 3547 # Number of cycles decode is running
234system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking
235system.cpu.decode.SquashCycles 1830 # Number of cycles decode is squashing
236system.cpu.decode.DecodedInsts 24449 # Number of instructions handled by decode
237system.cpu.rename.SquashCycles 1830 # Number of cycles rename is squashing
238system.cpu.rename.IdleCycles 9798 # Number of cycles rename is idle
239system.cpu.rename.BlockCycles 2386 # Number of cycles rename is blocking
240system.cpu.rename.serializeStallCycles 485 # count of cycles rename stalled for serializing inst
241system.cpu.rename.RunCycles 3325 # Number of cycles rename is running
242system.cpu.rename.UnblockCycles 759 # Number of cycles rename is unblocking
243system.cpu.rename.RenamedInsts 22967 # Number of instructions processed by rename
244system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
245system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full
246system.cpu.rename.LSQFullEvents 640 # Number of times rename has blocked due to LSQ full
247system.cpu.rename.RenamedOperands 25104 # Number of destination operands rename has renamed
248system.cpu.rename.RenameLookups 55188 # Number of register rename lookups that rename has made
249system.cpu.rename.int_rename_lookups 55172 # Number of integer rename lookups
250system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
251system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed
252system.cpu.rename.UndoneMaps 14044 # Number of HB maps that are undone due to squashing
253system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
254system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed
255system.cpu.rename.skidInsts 2021 # count of insts added to the skid buffer
256system.cpu.memDep0.insertedLoads 2205 # Number of loads inserted to the mem dependence unit.
257system.cpu.memDep0.insertedStores 1755 # Number of stores inserted to the mem dependence unit.
258system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
259system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores.
260system.cpu.iq.iqInstsAdded 20454 # Number of instructions added to the IQ (excludes non-spec)
261system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ
262system.cpu.iq.iqInstsIssued 17349 # Number of instructions issued
263system.cpu.iq.iqSquashedInstsIssued 213 # Number of squashed instructions issued
264system.cpu.iq.iqSquashedInstsExamined 9974 # Number of squashed instructions iterated over during squash; mainly for profiling
265system.cpu.iq.iqSquashedOperandsExamined 13873 # Number of squashed operands that are examined and possibly removed from graph
266system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
267system.cpu.iq.issued_per_cycle::samples 18583 # Number of insts issued each cycle
268system.cpu.iq.issued_per_cycle::mean 0.933595 # Number of insts issued each cycle
269system.cpu.iq.issued_per_cycle::stdev 1.794406 # Number of insts issued each cycle
270system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
271system.cpu.iq.issued_per_cycle::0 13202 71.04% 71.04% # Number of insts issued each cycle
272system.cpu.iq.issued_per_cycle::1 1386 7.46% 78.50% # Number of insts issued each cycle
273system.cpu.iq.issued_per_cycle::2 1042 5.61% 84.11% # Number of insts issued each cycle
274system.cpu.iq.issued_per_cycle::3 691 3.72% 87.83% # Number of insts issued each cycle
275system.cpu.iq.issued_per_cycle::4 742 3.99% 91.82% # Number of insts issued each cycle
276system.cpu.iq.issued_per_cycle::5 623 3.35% 95.17% # Number of insts issued each cycle
277system.cpu.iq.issued_per_cycle::6 598 3.22% 98.39% # Number of insts issued each cycle
278system.cpu.iq.issued_per_cycle::7 257 1.38% 99.77% # Number of insts issued each cycle
279system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle
280system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
281system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
282system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
283system.cpu.iq.issued_per_cycle::total 18583 # Number of insts issued each cycle
284system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
285system.cpu.iq.fu_full::IntAlu 138 77.53% 77.53% # attempts to use FU when none available
286system.cpu.iq.fu_full::IntMult 0 0.00% 77.53% # attempts to use FU when none available
287system.cpu.iq.fu_full::IntDiv 0 0.00% 77.53% # attempts to use FU when none available
288system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.53% # attempts to use FU when none available
289system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.53% # attempts to use FU when none available
290system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.53% # attempts to use FU when none available
291system.cpu.iq.fu_full::FloatMult 0 0.00% 77.53% # attempts to use FU when none available
292system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.53% # attempts to use FU when none available
293system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.53% # attempts to use FU when none available
294system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.53% # attempts to use FU when none available
295system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.53% # attempts to use FU when none available
296system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.53% # attempts to use FU when none available
297system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.53% # attempts to use FU when none available
298system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.53% # attempts to use FU when none available
299system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.53% # attempts to use FU when none available
300system.cpu.iq.fu_full::SimdMult 0 0.00% 77.53% # attempts to use FU when none available
301system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.53% # attempts to use FU when none available
302system.cpu.iq.fu_full::SimdShift 0 0.00% 77.53% # attempts to use FU when none available
303system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.53% # attempts to use FU when none available
304system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.53% # attempts to use FU when none available
305system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.53% # attempts to use FU when none available
306system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.53% # attempts to use FU when none available
307system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.53% # attempts to use FU when none available
308system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.53% # attempts to use FU when none available
309system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.53% # attempts to use FU when none available
310system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.53% # attempts to use FU when none available
311system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.53% # attempts to use FU when none available
312system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.53% # attempts to use FU when none available
313system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.53% # attempts to use FU when none available
314system.cpu.iq.fu_full::MemRead 19 10.67% 88.20% # attempts to use FU when none available
315system.cpu.iq.fu_full::MemWrite 21 11.80% 100.00% # attempts to use FU when none available
316system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
317system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
318system.cpu.iq.FU_type_0::No_OpClass 5 0.03% 0.03% # Type of FU issued
319system.cpu.iq.FU_type_0::IntAlu 13962 80.48% 80.51% # Type of FU issued
320system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.51% # Type of FU issued
321system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.51% # Type of FU issued
322system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.51% # Type of FU issued
323system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.51% # Type of FU issued
324system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.51% # Type of FU issued
325system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.51% # Type of FU issued
326system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.51% # Type of FU issued
327system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.51% # Type of FU issued
328system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.51% # Type of FU issued
329system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.51% # Type of FU issued
330system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.51% # Type of FU issued
331system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.51% # Type of FU issued
332system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.51% # Type of FU issued
333system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.51% # Type of FU issued
334system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.51% # Type of FU issued
335system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.51% # Type of FU issued
336system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.51% # Type of FU issued
337system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.51% # Type of FU issued
338system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.51% # Type of FU issued
339system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.51% # Type of FU issued
340system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.51% # Type of FU issued
341system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.51% # Type of FU issued
342system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.51% # Type of FU issued
343system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.51% # Type of FU issued
344system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.51% # Type of FU issued
345system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.51% # Type of FU issued
346system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.51% # Type of FU issued
347system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.51% # Type of FU issued
348system.cpu.iq.FU_type_0::MemRead 1900 10.95% 91.46% # Type of FU issued
349system.cpu.iq.FU_type_0::MemWrite 1482 8.54% 100.00% # Type of FU issued
350system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
351system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
352system.cpu.iq.FU_type_0::total 17349 # Type of FU issued
353system.cpu.iq.rate 0.577742 # Inst issue rate
354system.cpu.iq.fu_busy_cnt 178 # FU busy when requested
355system.cpu.iq.fu_busy_rate 0.010260 # FU busy rate (busy events/executed inst)
356system.cpu.iq.int_inst_queue_reads 53664 # Number of integer instruction queue reads
357system.cpu.iq.int_inst_queue_writes 30472 # Number of integer instruction queue writes
358system.cpu.iq.int_inst_queue_wakeup_accesses 16003 # Number of integer instruction queue wakeup accesses
359system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
360system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
361system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
362system.cpu.iq.int_alu_accesses 17518 # Number of integer alu accesses
363system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
364system.cpu.iew.lsq.thread0.forwLoads 157 # Number of loads that had data forwarded from stores
365system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
366system.cpu.iew.lsq.thread0.squashedLoads 1153 # Number of loads squashed
367system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed
368system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
369system.cpu.iew.lsq.thread0.squashedStores 821 # Number of stores squashed
370system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
371system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
372system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
373system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked
374system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
375system.cpu.iew.iewSquashCycles 1830 # Number of cycles IEW is squashing
376system.cpu.iew.iewBlockCycles 1703 # Number of cycles IEW is blocking
377system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking
378system.cpu.iew.iewDispatchedInsts 20491 # Number of instructions dispatched to IQ
379system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch
380system.cpu.iew.iewDispLoadInsts 2205 # Number of dispatched load instructions
381system.cpu.iew.iewDispStoreInsts 1755 # Number of dispatched store instructions
382system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions
383system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
384system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
385system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
386system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly
387system.cpu.iew.predictedNotTakenIncorrect 601 # Number of branches that were predicted not taken incorrectly
388system.cpu.iew.branchMispredicts 657 # Number of branch mispredicts detected at execute
389system.cpu.iew.iewExecutedInsts 16425 # Number of executed instructions
390system.cpu.iew.iewExecLoadInsts 1777 # Number of load instructions executed
391system.cpu.iew.iewExecSquashedInsts 924 # Number of squashed instructions skipped in execute
392system.cpu.iew.exec_swp 0 # number of swp insts executed
393system.cpu.iew.exec_nop 0 # number of nop insts executed
394system.cpu.iew.exec_refs 3140 # number of memory reference insts executed
395system.cpu.iew.exec_branches 1630 # Number of branches executed
396system.cpu.iew.exec_stores 1363 # Number of stores executed
397system.cpu.iew.exec_rate 0.546971 # Inst execution rate
398system.cpu.iew.wb_sent 16197 # cumulative count of insts sent to commit
399system.cpu.iew.wb_count 16007 # cumulative count of insts written-back
400system.cpu.iew.wb_producers 10178 # num instructions producing a value
401system.cpu.iew.wb_consumers 15727 # num instructions consuming a value
402system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
403system.cpu.iew.wb_rate 0.533051 # insts written-back per cycle
404system.cpu.iew.wb_fanout 0.647167 # average fanout of values written-back
405system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
406system.cpu.commit.commitSquashedInsts 10745 # The number of squashed insts skipped by commit
407system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
408system.cpu.commit.branchMispredicts 566 # The number of times a branch was mispredicted
409system.cpu.commit.committed_per_cycle::samples 16753 # Number of insts commited each cycle
410system.cpu.commit.committed_per_cycle::mean 0.581687 # Number of insts commited each cycle
411system.cpu.commit.committed_per_cycle::stdev 1.458321 # Number of insts commited each cycle
412system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
413system.cpu.commit.committed_per_cycle::0 13226 78.95% 78.95% # Number of insts commited each cycle
414system.cpu.commit.committed_per_cycle::1 1316 7.86% 86.80% # Number of insts commited each cycle
415system.cpu.commit.committed_per_cycle::2 596 3.56% 90.36% # Number of insts commited each cycle
416system.cpu.commit.committed_per_cycle::3 710 4.24% 94.60% # Number of insts commited each cycle
417system.cpu.commit.committed_per_cycle::4 351 2.10% 96.69% # Number of insts commited each cycle
418system.cpu.commit.committed_per_cycle::5 138 0.82% 97.52% # Number of insts commited each cycle
419system.cpu.commit.committed_per_cycle::6 120 0.72% 98.23% # Number of insts commited each cycle
420system.cpu.commit.committed_per_cycle::7 75 0.45% 98.68% # Number of insts commited each cycle
421system.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle
422system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
423system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
424system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
425system.cpu.commit.committed_per_cycle::total 16753 # Number of insts commited each cycle
426system.cpu.commit.committedInsts 5380 # Number of instructions committed
427system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed
428system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
429system.cpu.commit.refs 1986 # Number of memory references committed
430system.cpu.commit.loads 1052 # Number of loads committed
431system.cpu.commit.membars 0 # Number of memory barriers committed
432system.cpu.commit.branches 1208 # Number of branches committed
433system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
434system.cpu.commit.int_insts 9650 # Number of committed integer instructions.
435system.cpu.commit.function_calls 0 # Number of function calls committed.
436system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached
437system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
438system.cpu.rob.rob_reads 37022 # The number of ROB reads
439system.cpu.rob.rob_writes 42839 # The number of ROB writes
440system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself
441system.cpu.idleCycles 11446 # Total number of cycles that the CPU has spent unscheduled due to idling
442system.cpu.committedInsts 5380 # Number of Instructions Simulated
443system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated
444system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
445system.cpu.cpi 5.581599 # CPI: Cycles Per Instruction
446system.cpu.cpi_total 5.581599 # CPI: Total CPI of All Threads
447system.cpu.ipc 0.179160 # IPC: Instructions Per Cycle
448system.cpu.ipc_total 0.179160 # IPC: Total IPC of All Threads
449system.cpu.int_regfile_reads 28874 # number of integer regfile reads
450system.cpu.int_regfile_writes 17232 # number of integer regfile writes
451system.cpu.fp_regfile_reads 4 # number of floating regfile reads
452system.cpu.misc_regfile_reads 7155 # number of misc regfile reads
453system.cpu.icache.replacements 0 # number of replacements
454system.cpu.icache.tagsinuse 144.838361 # Cycle average of tags in use
455system.cpu.icache.total_refs 1482 # Total number of references to valid blocks.
456system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks.
457system.cpu.icache.avg_refs 4.875000 # Average number of references to valid blocks.
458system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
459system.cpu.icache.occ_blocks::cpu.inst 144.838361 # Average occupied blocks per requestor
460system.cpu.icache.occ_percent::cpu.inst 0.070722 # Average percentage of cache occupancy
461system.cpu.icache.occ_percent::total 0.070722 # Average percentage of cache occupancy
462system.cpu.icache.ReadReq_hits::cpu.inst 1482 # number of ReadReq hits
463system.cpu.icache.ReadReq_hits::total 1482 # number of ReadReq hits
464system.cpu.icache.demand_hits::cpu.inst 1482 # number of demand (read+write) hits
465system.cpu.icache.demand_hits::total 1482 # number of demand (read+write) hits
466system.cpu.icache.overall_hits::cpu.inst 1482 # number of overall hits
467system.cpu.icache.overall_hits::total 1482 # number of overall hits
468system.cpu.icache.ReadReq_misses::cpu.inst 398 # number of ReadReq misses
469system.cpu.icache.ReadReq_misses::total 398 # number of ReadReq misses
470system.cpu.icache.demand_misses::cpu.inst 398 # number of demand (read+write) misses
471system.cpu.icache.demand_misses::total 398 # number of demand (read+write) misses
472system.cpu.icache.overall_misses::cpu.inst 398 # number of overall misses
473system.cpu.icache.overall_misses::total 398 # number of overall misses
474system.cpu.icache.ReadReq_miss_latency::cpu.inst 19300000 # number of ReadReq miss cycles
475system.cpu.icache.ReadReq_miss_latency::total 19300000 # number of ReadReq miss cycles
476system.cpu.icache.demand_miss_latency::cpu.inst 19300000 # number of demand (read+write) miss cycles
477system.cpu.icache.demand_miss_latency::total 19300000 # number of demand (read+write) miss cycles
478system.cpu.icache.overall_miss_latency::cpu.inst 19300000 # number of overall miss cycles
479system.cpu.icache.overall_miss_latency::total 19300000 # number of overall miss cycles
480system.cpu.icache.ReadReq_accesses::cpu.inst 1880 # number of ReadReq accesses(hits+misses)
481system.cpu.icache.ReadReq_accesses::total 1880 # number of ReadReq accesses(hits+misses)
482system.cpu.icache.demand_accesses::cpu.inst 1880 # number of demand (read+write) accesses
483system.cpu.icache.demand_accesses::total 1880 # number of demand (read+write) accesses
484system.cpu.icache.overall_accesses::cpu.inst 1880 # number of overall (read+write) accesses
485system.cpu.icache.overall_accesses::total 1880 # number of overall (read+write) accesses
486system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.211702 # miss rate for ReadReq accesses
487system.cpu.icache.ReadReq_miss_rate::total 0.211702 # miss rate for ReadReq accesses
488system.cpu.icache.demand_miss_rate::cpu.inst 0.211702 # miss rate for demand accesses
489system.cpu.icache.demand_miss_rate::total 0.211702 # miss rate for demand accesses
490system.cpu.icache.overall_miss_rate::cpu.inst 0.211702 # miss rate for overall accesses
491system.cpu.icache.overall_miss_rate::total 0.211702 # miss rate for overall accesses
492system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48492.462312 # average ReadReq miss latency
493system.cpu.icache.ReadReq_avg_miss_latency::total 48492.462312 # average ReadReq miss latency
494system.cpu.icache.demand_avg_miss_latency::cpu.inst 48492.462312 # average overall miss latency
495system.cpu.icache.demand_avg_miss_latency::total 48492.462312 # average overall miss latency
496system.cpu.icache.overall_avg_miss_latency::cpu.inst 48492.462312 # average overall miss latency
497system.cpu.icache.overall_avg_miss_latency::total 48492.462312 # average overall miss latency
498system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
499system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
500system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
501system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
502system.cpu.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked
503system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
504system.cpu.icache.fast_writes 0 # number of fast writes performed
505system.cpu.icache.cache_copies 0 # number of cache copies performed
506system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits
507system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits
508system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits
509system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits
510system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits
511system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits
512system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses
513system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses
514system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses
515system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses
516system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses
517system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses
518system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15461500 # number of ReadReq MSHR miss cycles
519system.cpu.icache.ReadReq_mshr_miss_latency::total 15461500 # number of ReadReq MSHR miss cycles
520system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15461500 # number of demand (read+write) MSHR miss cycles
521system.cpu.icache.demand_mshr_miss_latency::total 15461500 # number of demand (read+write) MSHR miss cycles
522system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15461500 # number of overall MSHR miss cycles
523system.cpu.icache.overall_mshr_miss_latency::total 15461500 # number of overall MSHR miss cycles
524system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for ReadReq accesses
525system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161702 # mshr miss rate for ReadReq accesses
526system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for demand accesses
527system.cpu.icache.demand_mshr_miss_rate::total 0.161702 # mshr miss rate for demand accesses
528system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for overall accesses
529system.cpu.icache.overall_mshr_miss_rate::total 0.161702 # mshr miss rate for overall accesses
530system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50860.197368 # average ReadReq mshr miss latency
531system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50860.197368 # average ReadReq mshr miss latency
532system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency
533system.cpu.icache.demand_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency
534system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency
535system.cpu.icache.overall_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency
536system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
537system.cpu.l2cache.replacements 0 # number of replacements
538system.cpu.l2cache.tagsinuse 178.021325 # Cycle average of tags in use
539system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
540system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
541system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
542system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
543system.cpu.l2cache.occ_blocks::cpu.inst 144.985294 # Average occupied blocks per requestor
544system.cpu.l2cache.occ_blocks::cpu.data 33.036031 # Average occupied blocks per requestor
545system.cpu.l2cache.occ_percent::cpu.inst 0.004425 # Average percentage of cache occupancy
546system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy
547system.cpu.l2cache.occ_percent::total 0.005433 # Average percentage of cache occupancy
548system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
549system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
550system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
551system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
552system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
553system.cpu.l2cache.overall_hits::total 1 # number of overall hits
554system.cpu.l2cache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses
555system.cpu.l2cache.ReadReq_misses::cpu.data 71 # number of ReadReq misses
556system.cpu.l2cache.ReadReq_misses::total 374 # number of ReadReq misses
557system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses
558system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses
559system.cpu.l2cache.demand_misses::cpu.inst 303 # number of demand (read+write) misses
560system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses
561system.cpu.l2cache.demand_misses::total 450 # number of demand (read+write) misses
562system.cpu.l2cache.overall_misses::cpu.inst 303 # number of overall misses
563system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses
564system.cpu.l2cache.overall_misses::total 450 # number of overall misses
565system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15146500 # number of ReadReq miss cycles
566system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3811000 # number of ReadReq miss cycles
567system.cpu.l2cache.ReadReq_miss_latency::total 18957500 # number of ReadReq miss cycles
568system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3992500 # number of ReadExReq miss cycles
569system.cpu.l2cache.ReadExReq_miss_latency::total 3992500 # number of ReadExReq miss cycles
570system.cpu.l2cache.demand_miss_latency::cpu.inst 15146500 # number of demand (read+write) miss cycles
571system.cpu.l2cache.demand_miss_latency::cpu.data 7803500 # number of demand (read+write) miss cycles
572system.cpu.l2cache.demand_miss_latency::total 22950000 # number of demand (read+write) miss cycles
573system.cpu.l2cache.overall_miss_latency::cpu.inst 15146500 # number of overall miss cycles
574system.cpu.l2cache.overall_miss_latency::cpu.data 7803500 # number of overall miss cycles
575system.cpu.l2cache.overall_miss_latency::total 22950000 # number of overall miss cycles
576system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses)
577system.cpu.l2cache.ReadReq_accesses::cpu.data 71 # number of ReadReq accesses(hits+misses)
578system.cpu.l2cache.ReadReq_accesses::total 375 # number of ReadReq accesses(hits+misses)
579system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses)
580system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses)
581system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses
582system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
583system.cpu.l2cache.demand_accesses::total 451 # number of demand (read+write) accesses
584system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses
585system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
586system.cpu.l2cache.overall_accesses::total 451 # number of overall (read+write) accesses
587system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996711 # miss rate for ReadReq accesses
588system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
589system.cpu.l2cache.ReadReq_miss_rate::total 0.997333 # miss rate for ReadReq accesses
590system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
591system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
592system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996711 # miss rate for demand accesses
593system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
594system.cpu.l2cache.demand_miss_rate::total 0.997783 # miss rate for demand accesses
595system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996711 # miss rate for overall accesses
596system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
597system.cpu.l2cache.overall_miss_rate::total 0.997783 # miss rate for overall accesses
598system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49988.448845 # average ReadReq miss latency
599system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53676.056338 # average ReadReq miss latency
600system.cpu.l2cache.ReadReq_avg_miss_latency::total 50688.502674 # average ReadReq miss latency
601system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52532.894737 # average ReadExReq miss latency
602system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52532.894737 # average ReadExReq miss latency
603system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency
604system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53085.034014 # average overall miss latency
605system.cpu.l2cache.demand_avg_miss_latency::total 51000 # average overall miss latency
606system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency
607system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53085.034014 # average overall miss latency
608system.cpu.l2cache.overall_avg_miss_latency::total 51000 # average overall miss latency
609system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
610system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
611system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
612system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
613system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
614system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
615system.cpu.l2cache.fast_writes 0 # number of fast writes performed
616system.cpu.l2cache.cache_copies 0 # number of cache copies performed
617system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses
618system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses
619system.cpu.l2cache.ReadReq_mshr_misses::total 374 # number of ReadReq MSHR misses
620system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses
621system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses
622system.cpu.l2cache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses
623system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
624system.cpu.l2cache.demand_mshr_misses::total 450 # number of demand (read+write) MSHR misses
625system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses
626system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
627system.cpu.l2cache.overall_mshr_misses::total 450 # number of overall MSHR misses
628system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11336452 # number of ReadReq MSHR miss cycles
629system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2944072 # number of ReadReq MSHR miss cycles
630system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14280524 # number of ReadReq MSHR miss cycles
631system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3029110 # number of ReadExReq MSHR miss cycles
632system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3029110 # number of ReadExReq MSHR miss cycles
633system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11336452 # number of demand (read+write) MSHR miss cycles
634system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5973182 # number of demand (read+write) MSHR miss cycles
635system.cpu.l2cache.demand_mshr_miss_latency::total 17309634 # number of demand (read+write) MSHR miss cycles
636system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11336452 # number of overall MSHR miss cycles
637system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5973182 # number of overall MSHR miss cycles
638system.cpu.l2cache.overall_mshr_miss_latency::total 17309634 # number of overall MSHR miss cycles
639system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses
640system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
641system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997333 # mshr miss rate for ReadReq accesses
642system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
643system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
644system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for demand accesses
645system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
646system.cpu.l2cache.demand_mshr_miss_rate::total 0.997783 # mshr miss rate for demand accesses
647system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses
648system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
649system.cpu.l2cache.overall_mshr_miss_rate::total 0.997783 # mshr miss rate for overall accesses
650system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37414.033003 # average ReadReq mshr miss latency
651system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41465.802817 # average ReadReq mshr miss latency
652system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38183.219251 # average ReadReq mshr miss latency
653system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39856.710526 # average ReadExReq mshr miss latency
654system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39856.710526 # average ReadExReq mshr miss latency
655system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency
656system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency
657system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency
658system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency
659system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency
660system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency
661system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
662system.cpu.dcache.replacements 0 # number of replacements
663system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use
664system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks.
665system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks.
666system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks.
667system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
668system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor
669system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy
670system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy
671system.cpu.dcache.ReadReq_hits::cpu.data 1426 # number of ReadReq hits
672system.cpu.dcache.ReadReq_hits::total 1426 # number of ReadReq hits
673system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
674system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
675system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits
676system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits
677system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits
678system.cpu.dcache.overall_hits::total 2284 # number of overall hits
679system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses
680system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses
681system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
682system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
683system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses
684system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses
685system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses
686system.cpu.dcache.overall_misses::total 202 # number of overall misses
687system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336000 # number of ReadReq miss cycles
688system.cpu.dcache.ReadReq_miss_latency::total 6336000 # number of ReadReq miss cycles
689system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles
690system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles
691system.cpu.dcache.demand_miss_latency::cpu.data 10556500 # number of demand (read+write) miss cycles
692system.cpu.dcache.demand_miss_latency::total 10556500 # number of demand (read+write) miss cycles
693system.cpu.dcache.overall_miss_latency::cpu.data 10556500 # number of overall miss cycles
694system.cpu.dcache.overall_miss_latency::total 10556500 # number of overall miss cycles
695system.cpu.dcache.ReadReq_accesses::cpu.data 1552 # number of ReadReq accesses(hits+misses)
696system.cpu.dcache.ReadReq_accesses::total 1552 # number of ReadReq accesses(hits+misses)
697system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
698system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
699system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses
700system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses
701system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses
702system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses
703system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081186 # miss rate for ReadReq accesses
704system.cpu.dcache.ReadReq_miss_rate::total 0.081186 # miss rate for ReadReq accesses
705system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses
706system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses
707system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses
708system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses
709system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses
710system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses
711system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50285.714286 # average ReadReq miss latency
712system.cpu.dcache.ReadReq_avg_miss_latency::total 50285.714286 # average ReadReq miss latency
713system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency
714system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency
715system.cpu.dcache.demand_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency
716system.cpu.dcache.demand_avg_miss_latency::total 52259.900990 # average overall miss latency
717system.cpu.dcache.overall_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency
718system.cpu.dcache.overall_avg_miss_latency::total 52259.900990 # average overall miss latency
719system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked
720system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
721system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
722system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
723system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked
724system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
725system.cpu.dcache.fast_writes 0 # number of fast writes performed
726system.cpu.dcache.cache_copies 0 # number of cache copies performed
727system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits
728system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits
729system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits
730system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits
731system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits
732system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits
733system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses
734system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses
735system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
736system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
737system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
738system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
739system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
740system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
741system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735000 # number of ReadReq MSHR miss cycles
742system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735000 # number of ReadReq MSHR miss cycles
743system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles
744system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles
745system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7803500 # number of demand (read+write) MSHR miss cycles
746system.cpu.dcache.demand_mshr_miss_latency::total 7803500 # number of demand (read+write) MSHR miss cycles
747system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7803500 # number of overall MSHR miss cycles
748system.cpu.dcache.overall_mshr_miss_latency::total 7803500 # number of overall MSHR miss cycles
749system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045747 # mshr miss rate for ReadReq accesses
750system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045747 # mshr miss rate for ReadReq accesses
751system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses
752system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses
753system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses
754system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses
755system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses
756system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses
757system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.633803 # average ReadReq mshr miss latency
758system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.633803 # average ReadReq mshr miss latency
759system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency
760system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency
761system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency
762system.cpu.dcache.demand_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency
763system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency
764system.cpu.dcache.overall_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency
765system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
766
767---------- End Simulation Statistics ----------