1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000020 # Number of seconds simulated
4sim_ticks 19678000 # Number of ticks simulated
5final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 48979 # Simulator instruction rate (inst/s)
8host_op_rate 88725 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 179100946 # Simulator tick rate (ticks/s)
10host_mem_usage 305852 # Number of bytes of host memory used
11host_seconds 0.11 # Real time elapsed on the host
12sim_insts 5380 # Number of instructions simulated
13sim_ops 9747 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 894399837 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 458583189 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 1352983027 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 894399837 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 894399837 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 894399837 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 458583189 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 1352983027 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.readReqs 417 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side
--- 30 unchanged lines hidden (view full) ---
70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78system.physmem.totGap 19629500 # Total gap between requests
79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 417 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)
87system.physmem.writePktSize::1 0 # Write request sizes (log2)
88system.physmem.writePktSize::2 0 # Write request sizes (log2)
89system.physmem.writePktSize::3 0 # Write request sizes (log2)
90system.physmem.writePktSize::4 0 # Write request sizes (log2)
91system.physmem.writePktSize::5 0 # Write request sizes (log2)
92system.physmem.writePktSize::6 0 # Write request sizes (log2)
93system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
--- 79 unchanged lines hidden (view full) ---
183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation
190system.physmem.bytesPerActivate::mean 242.285714 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::gmean 158.475642 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::stdev 257.521253 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::0-127 36 36.73% 36.73% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 30 30.61% 67.35% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::256-383 13 13.27% 80.61% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 6 6.12% 86.73% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::640-767 6 6.12% 92.86% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::896-1023 4 4.08% 96.94% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::1024-1151 3 3.06% 100.00% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation
201system.physmem.totQLat 4347000 # Total ticks spent queuing
202system.physmem.totMemAccLat 12165750 # Total ticks spent from burst creation until serviced by the DRAM
203system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers
204system.physmem.avgQLat 10424.46 # Average queueing delay per DRAM burst
205system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
206system.physmem.avgMemAccLat 29174.46 # Average memory access latency per DRAM burst
207system.physmem.avgRdBW 1356.24 # Average DRAM read bandwidth in MiByte/s
208system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
209system.physmem.avgRdBWSys 1356.24 # Average system read bandwidth in MiByte/s
210system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
211system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
212system.physmem.busUtil 10.60 # Data bus utilization in percentage
213system.physmem.busUtilRead 10.60 # Data bus utilization in percentage for reads
214system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
215system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing
216system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
217system.physmem.readRowHits 309 # Number of row buffer hits during reads
218system.physmem.writeRowHits 0 # Number of row buffer hits during writes
219system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads
220system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
221system.physmem.avgGap 47073.14 # Average gap between requests
222system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined
223system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
224system.physmem.memoryStateTime::REF 520000 # Time in different power states
225system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
226system.physmem.memoryStateTime::ACT 15318250 # Time in different power states
227system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
228system.membus.trans_dist::ReadReq 339 # Transaction distribution
229system.membus.trans_dist::ReadResp 338 # Transaction distribution
230system.membus.trans_dist::ReadExReq 78 # Transaction distribution
231system.membus.trans_dist::ReadExResp 78 # Transaction distribution
232system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes)
233system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes)
234system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes)
235system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
236system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
237system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
238system.membus.snoops 0 # Total snoops (count)
239system.membus.snoop_fanout::samples 417 # Request fanout histogram
240system.membus.snoop_fanout::mean 0 # Request fanout histogram
241system.membus.snoop_fanout::stdev 0 # Request fanout histogram
242system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
243system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram
244system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
245system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
246system.membus.snoop_fanout::min_value 0 # Request fanout histogram
247system.membus.snoop_fanout::max_value 0 # Request fanout histogram
248system.membus.snoop_fanout::total 417 # Request fanout histogram
249system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks)
250system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
251system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks)
252system.membus.respLayer1.utilization 19.8 # Layer utilization (%)
253system.cpu_clk_domain.clock 500 # Clock period in ticks
254system.cpu.branchPred.lookups 3423 # Number of BP lookups
255system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted
256system.cpu.branchPred.condIncorrect 535 # Number of conditional branches incorrect
257system.cpu.branchPred.BTBLookups 2544 # Number of BTB lookups
258system.cpu.branchPred.BTBHits 864 # Number of BTB hits
259system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
260system.cpu.branchPred.BTBHitPct 33.962264 # BTB Hit Percentage
261system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target.
262system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions.
263system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
264system.cpu.workload.num_syscalls 11 # Number of system calls
265system.cpu.numCycles 39357 # number of cpu cycles simulated
266system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
267system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
268system.cpu.fetch.icacheStallCycles 10915 # Number of cycles fetch is stalled on an Icache miss
269system.cpu.fetch.Insts 15528 # Number of instructions fetch has processed
270system.cpu.fetch.Branches 3423 # Number of branches that fetch encountered
271system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken
272system.cpu.fetch.Cycles 9222 # Number of cycles fetch has run and was not squashing or blocked
273system.cpu.fetch.SquashCycles 1202 # Number of cycles fetch has spent squashing
--- 14 unchanged lines hidden (view full) ---
288system.cpu.fetch.rateDist::5 227 1.04% 85.52% # Number of instructions fetched each cycle (Total)
289system.cpu.fetch.rateDist::6 339 1.55% 87.06% # Number of instructions fetched each cycle (Total)
290system.cpu.fetch.rateDist::7 205 0.94% 88.00% # Number of instructions fetched each cycle (Total)
291system.cpu.fetch.rateDist::8 2627 12.00% 100.00% # Number of instructions fetched each cycle (Total)
292system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
293system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
294system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
295system.cpu.fetch.rateDist::total 21893 # Number of instructions fetched each cycle (Total)
296system.cpu.fetch.branchRate 0.086973 # Number of branch fetches per cycle
297system.cpu.fetch.rate 0.394542 # Number of inst fetches per cycle
298system.cpu.decode.IdleCycles 10660 # Number of cycles decode is idle
299system.cpu.decode.BlockedCycles 6840 # Number of cycles decode is blocked
300system.cpu.decode.RunCycles 3336 # Number of cycles decode is running
301system.cpu.decode.UnblockCycles 456 # Number of cycles decode is unblocking
302system.cpu.decode.SquashCycles 601 # Number of cycles decode is squashing
303system.cpu.decode.DecodedInsts 25755 # Number of instructions handled by decode
304system.cpu.rename.SquashCycles 601 # Number of cycles rename is squashing
305system.cpu.rename.IdleCycles 10929 # Number of cycles rename is idle
--- 106 unchanged lines hidden (view full) ---
412system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.44% # Type of FU issued
413system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.44% # Type of FU issued
414system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.44% # Type of FU issued
415system.cpu.iq.FU_type_0::MemRead 2122 11.86% 92.29% # Type of FU issued
416system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Type of FU issued
417system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
418system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
419system.cpu.iq.FU_type_0::total 17897 # Type of FU issued
420system.cpu.iq.rate 0.454735 # Inst issue rate
421system.cpu.iq.fu_busy_cnt 224 # FU busy when requested
422system.cpu.iq.fu_busy_rate 0.012516 # FU busy rate (busy events/executed inst)
423system.cpu.iq.int_inst_queue_reads 57983 # Number of integer instruction queue reads
424system.cpu.iq.int_inst_queue_writes 32531 # Number of integer instruction queue writes
425system.cpu.iq.int_inst_queue_wakeup_accesses 16370 # Number of integer instruction queue wakeup accesses
426system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
427system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
428system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
--- 27 unchanged lines hidden (view full) ---
456system.cpu.iew.iewExecutedInsts 16926 # Number of executed instructions
457system.cpu.iew.iewExecLoadInsts 1969 # Number of load instructions executed
458system.cpu.iew.iewExecSquashedInsts 971 # Number of squashed instructions skipped in execute
459system.cpu.iew.exec_swp 0 # number of swp insts executed
460system.cpu.iew.exec_nop 0 # number of nop insts executed
461system.cpu.iew.exec_refs 3251 # number of memory reference insts executed
462system.cpu.iew.exec_branches 1662 # Number of branches executed
463system.cpu.iew.exec_stores 1282 # Number of stores executed
464system.cpu.iew.exec_rate 0.430063 # Inst execution rate
465system.cpu.iew.wb_sent 16636 # cumulative count of insts sent to commit
466system.cpu.iew.wb_count 16374 # cumulative count of insts written-back
467system.cpu.iew.wb_producers 11006 # num instructions producing a value
468system.cpu.iew.wb_consumers 17135 # num instructions consuming a value
469system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
470system.cpu.iew.wb_rate 0.416038 # insts written-back per cycle
471system.cpu.iew.wb_fanout 0.642311 # average fanout of values written-back
472system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
473system.cpu.commit.commitSquashedInsts 11720 # The number of squashed insts skipped by commit
474system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
475system.cpu.commit.branchMispredicts 588 # The number of times a branch was mispredicted
476system.cpu.commit.committed_per_cycle::samples 19925 # Number of insts commited each cycle
477system.cpu.commit.committed_per_cycle::mean 0.489184 # Number of insts commited each cycle
478system.cpu.commit.committed_per_cycle::stdev 1.394250 # Number of insts commited each cycle
--- 56 unchanged lines hidden (view full) ---
535system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
536system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
537system.cpu.commit.op_class_0::total 9747 # Class of committed instruction
538system.cpu.commit.bw_lim_events 260 # number cycles where commit BW limit reached
539system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
540system.cpu.rob.rob_reads 41132 # The number of ROB reads
541system.cpu.rob.rob_writes 44928 # The number of ROB writes
542system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself
543system.cpu.idleCycles 17464 # Total number of cycles that the CPU has spent unscheduled due to idling
544system.cpu.committedInsts 5380 # Number of Instructions Simulated
545system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
546system.cpu.cpi 7.315428 # CPI: Cycles Per Instruction
547system.cpu.cpi_total 7.315428 # CPI: Total CPI of All Threads
548system.cpu.ipc 0.136697 # IPC: Instructions Per Cycle
549system.cpu.ipc_total 0.136697 # IPC: Total IPC of All Threads
550system.cpu.int_regfile_reads 21340 # number of integer regfile reads
551system.cpu.int_regfile_writes 13120 # number of integer regfile writes
552system.cpu.fp_regfile_reads 4 # number of floating regfile reads
553system.cpu.cc_regfile_reads 8069 # number of cc regfile reads
554system.cpu.cc_regfile_writes 5036 # number of cc regfile writes
555system.cpu.misc_regfile_reads 7491 # number of misc regfile reads
556system.cpu.misc_regfile_writes 1 # number of misc regfile writes
557system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution
558system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
559system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution
560system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution
561system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes)
562system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes)
563system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes)
564system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes)
565system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
566system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes)
567system.cpu.toL2Bus.snoops 0 # Total snoops (count)
568system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
569system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
570system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
571system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
572system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
573system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
574system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
575system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram
576system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
577system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
578system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
579system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
580system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
581system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
582system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
583system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks)
584system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
585system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks)
586system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
587system.cpu.icache.tags.replacements 0 # number of replacements
588system.cpu.icache.tags.tagsinuse 131.539722 # Cycle average of tags in use
589system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks.
590system.cpu.icache.tags.sampled_refs 276 # Sample count of references to valid blocks.
591system.cpu.icache.tags.avg_refs 6.521739 # Average number of references to valid blocks.
592system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
593system.cpu.icache.tags.occ_blocks::cpu.inst 131.539722 # Average occupied blocks per requestor
594system.cpu.icache.tags.occ_percent::cpu.inst 0.064228 # Average percentage of cache occupancy
595system.cpu.icache.tags.occ_percent::total 0.064228 # Average percentage of cache occupancy
596system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id
597system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
598system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id
599system.cpu.icache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id
600system.cpu.icache.tags.tag_accesses 4612 # Number of tag accesses
601system.cpu.icache.tags.data_accesses 4612 # Number of data accesses
602system.cpu.icache.ReadReq_hits::cpu.inst 1800 # number of ReadReq hits
603system.cpu.icache.ReadReq_hits::total 1800 # number of ReadReq hits
604system.cpu.icache.demand_hits::cpu.inst 1800 # number of demand (read+write) hits
605system.cpu.icache.demand_hits::total 1800 # number of demand (read+write) hits
606system.cpu.icache.overall_hits::cpu.inst 1800 # number of overall hits
607system.cpu.icache.overall_hits::total 1800 # number of overall hits
608system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses
609system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses
610system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses
611system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses
612system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses
613system.cpu.icache.overall_misses::total 368 # number of overall misses
614system.cpu.icache.ReadReq_miss_latency::cpu.inst 25557250 # number of ReadReq miss cycles
615system.cpu.icache.ReadReq_miss_latency::total 25557250 # number of ReadReq miss cycles
616system.cpu.icache.demand_miss_latency::cpu.inst 25557250 # number of demand (read+write) miss cycles
617system.cpu.icache.demand_miss_latency::total 25557250 # number of demand (read+write) miss cycles
618system.cpu.icache.overall_miss_latency::cpu.inst 25557250 # number of overall miss cycles
619system.cpu.icache.overall_miss_latency::total 25557250 # number of overall miss cycles
620system.cpu.icache.ReadReq_accesses::cpu.inst 2168 # number of ReadReq accesses(hits+misses)
621system.cpu.icache.ReadReq_accesses::total 2168 # number of ReadReq accesses(hits+misses)
622system.cpu.icache.demand_accesses::cpu.inst 2168 # number of demand (read+write) accesses
623system.cpu.icache.demand_accesses::total 2168 # number of demand (read+write) accesses
624system.cpu.icache.overall_accesses::cpu.inst 2168 # number of overall (read+write) accesses
625system.cpu.icache.overall_accesses::total 2168 # number of overall (read+write) accesses
626system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169742 # miss rate for ReadReq accesses
627system.cpu.icache.ReadReq_miss_rate::total 0.169742 # miss rate for ReadReq accesses
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--- 4 unchanged lines hidden (view full) ---
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663system.cpu.icache.overall_mshr_miss_latency::total 20059000 # number of overall MSHR miss cycles
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--- 7 unchanged lines hidden (view full) ---
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--- 6 unchanged lines hidden (view full) ---
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--- 8 unchanged lines hidden (view full) ---
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--- 8 unchanged lines hidden (view full) ---
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909system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency
910system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency
911system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency
912system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency
913system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency
914system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency
915system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency
916system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency
917system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
918
919---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000020 # Number of seconds simulated
4sim_ticks 19678000 # Number of ticks simulated
5final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 48979 # Simulator instruction rate (inst/s)
8host_op_rate 88725 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 179100946 # Simulator tick rate (ticks/s)
10host_mem_usage 305852 # Number of bytes of host memory used
11host_seconds 0.11 # Real time elapsed on the host
12sim_insts 5380 # Number of instructions simulated
13sim_ops 9747 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 894399837 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 458583189 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 1352983027 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 894399837 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 894399837 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 894399837 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 458583189 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 1352983027 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.readReqs 417 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side
--- 30 unchanged lines hidden (view full) ---
70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78system.physmem.totGap 19629500 # Total gap between requests
79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 417 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)
87system.physmem.writePktSize::1 0 # Write request sizes (log2)
88system.physmem.writePktSize::2 0 # Write request sizes (log2)
89system.physmem.writePktSize::3 0 # Write request sizes (log2)
90system.physmem.writePktSize::4 0 # Write request sizes (log2)
91system.physmem.writePktSize::5 0 # Write request sizes (log2)
92system.physmem.writePktSize::6 0 # Write request sizes (log2)
93system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
--- 79 unchanged lines hidden (view full) ---
183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation
190system.physmem.bytesPerActivate::mean 242.285714 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::gmean 158.475642 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::stdev 257.521253 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::0-127 36 36.73% 36.73% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 30 30.61% 67.35% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::256-383 13 13.27% 80.61% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 6 6.12% 86.73% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::640-767 6 6.12% 92.86% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::896-1023 4 4.08% 96.94% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::1024-1151 3 3.06% 100.00% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation
201system.physmem.totQLat 4347000 # Total ticks spent queuing
202system.physmem.totMemAccLat 12165750 # Total ticks spent from burst creation until serviced by the DRAM
203system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers
204system.physmem.avgQLat 10424.46 # Average queueing delay per DRAM burst
205system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
206system.physmem.avgMemAccLat 29174.46 # Average memory access latency per DRAM burst
207system.physmem.avgRdBW 1356.24 # Average DRAM read bandwidth in MiByte/s
208system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
209system.physmem.avgRdBWSys 1356.24 # Average system read bandwidth in MiByte/s
210system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
211system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
212system.physmem.busUtil 10.60 # Data bus utilization in percentage
213system.physmem.busUtilRead 10.60 # Data bus utilization in percentage for reads
214system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
215system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing
216system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
217system.physmem.readRowHits 309 # Number of row buffer hits during reads
218system.physmem.writeRowHits 0 # Number of row buffer hits during writes
219system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads
220system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
221system.physmem.avgGap 47073.14 # Average gap between requests
222system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined
223system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
224system.physmem.memoryStateTime::REF 520000 # Time in different power states
225system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
226system.physmem.memoryStateTime::ACT 15318250 # Time in different power states
227system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
228system.membus.trans_dist::ReadReq 339 # Transaction distribution
229system.membus.trans_dist::ReadResp 338 # Transaction distribution
230system.membus.trans_dist::ReadExReq 78 # Transaction distribution
231system.membus.trans_dist::ReadExResp 78 # Transaction distribution
232system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes)
233system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes)
234system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes)
235system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
236system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
237system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
238system.membus.snoops 0 # Total snoops (count)
239system.membus.snoop_fanout::samples 417 # Request fanout histogram
240system.membus.snoop_fanout::mean 0 # Request fanout histogram
241system.membus.snoop_fanout::stdev 0 # Request fanout histogram
242system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
243system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram
244system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
245system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
246system.membus.snoop_fanout::min_value 0 # Request fanout histogram
247system.membus.snoop_fanout::max_value 0 # Request fanout histogram
248system.membus.snoop_fanout::total 417 # Request fanout histogram
249system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks)
250system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
251system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks)
252system.membus.respLayer1.utilization 19.8 # Layer utilization (%)
253system.cpu_clk_domain.clock 500 # Clock period in ticks
254system.cpu.branchPred.lookups 3423 # Number of BP lookups
255system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted
256system.cpu.branchPred.condIncorrect 535 # Number of conditional branches incorrect
257system.cpu.branchPred.BTBLookups 2544 # Number of BTB lookups
258system.cpu.branchPred.BTBHits 864 # Number of BTB hits
259system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
260system.cpu.branchPred.BTBHitPct 33.962264 # BTB Hit Percentage
261system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target.
262system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions.
263system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
264system.cpu.workload.num_syscalls 11 # Number of system calls
265system.cpu.numCycles 39357 # number of cpu cycles simulated
266system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
267system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
268system.cpu.fetch.icacheStallCycles 10915 # Number of cycles fetch is stalled on an Icache miss
269system.cpu.fetch.Insts 15528 # Number of instructions fetch has processed
270system.cpu.fetch.Branches 3423 # Number of branches that fetch encountered
271system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken
272system.cpu.fetch.Cycles 9222 # Number of cycles fetch has run and was not squashing or blocked
273system.cpu.fetch.SquashCycles 1202 # Number of cycles fetch has spent squashing
--- 14 unchanged lines hidden (view full) ---
288system.cpu.fetch.rateDist::5 227 1.04% 85.52% # Number of instructions fetched each cycle (Total)
289system.cpu.fetch.rateDist::6 339 1.55% 87.06% # Number of instructions fetched each cycle (Total)
290system.cpu.fetch.rateDist::7 205 0.94% 88.00% # Number of instructions fetched each cycle (Total)
291system.cpu.fetch.rateDist::8 2627 12.00% 100.00% # Number of instructions fetched each cycle (Total)
292system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
293system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
294system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
295system.cpu.fetch.rateDist::total 21893 # Number of instructions fetched each cycle (Total)
296system.cpu.fetch.branchRate 0.086973 # Number of branch fetches per cycle
297system.cpu.fetch.rate 0.394542 # Number of inst fetches per cycle
298system.cpu.decode.IdleCycles 10660 # Number of cycles decode is idle
299system.cpu.decode.BlockedCycles 6840 # Number of cycles decode is blocked
300system.cpu.decode.RunCycles 3336 # Number of cycles decode is running
301system.cpu.decode.UnblockCycles 456 # Number of cycles decode is unblocking
302system.cpu.decode.SquashCycles 601 # Number of cycles decode is squashing
303system.cpu.decode.DecodedInsts 25755 # Number of instructions handled by decode
304system.cpu.rename.SquashCycles 601 # Number of cycles rename is squashing
305system.cpu.rename.IdleCycles 10929 # Number of cycles rename is idle
--- 106 unchanged lines hidden (view full) ---
412system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.44% # Type of FU issued
413system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.44% # Type of FU issued
414system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.44% # Type of FU issued
415system.cpu.iq.FU_type_0::MemRead 2122 11.86% 92.29% # Type of FU issued
416system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Type of FU issued
417system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
418system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
419system.cpu.iq.FU_type_0::total 17897 # Type of FU issued
420system.cpu.iq.rate 0.454735 # Inst issue rate
421system.cpu.iq.fu_busy_cnt 224 # FU busy when requested
422system.cpu.iq.fu_busy_rate 0.012516 # FU busy rate (busy events/executed inst)
423system.cpu.iq.int_inst_queue_reads 57983 # Number of integer instruction queue reads
424system.cpu.iq.int_inst_queue_writes 32531 # Number of integer instruction queue writes
425system.cpu.iq.int_inst_queue_wakeup_accesses 16370 # Number of integer instruction queue wakeup accesses
426system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
427system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
428system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
--- 27 unchanged lines hidden (view full) ---
456system.cpu.iew.iewExecutedInsts 16926 # Number of executed instructions
457system.cpu.iew.iewExecLoadInsts 1969 # Number of load instructions executed
458system.cpu.iew.iewExecSquashedInsts 971 # Number of squashed instructions skipped in execute
459system.cpu.iew.exec_swp 0 # number of swp insts executed
460system.cpu.iew.exec_nop 0 # number of nop insts executed
461system.cpu.iew.exec_refs 3251 # number of memory reference insts executed
462system.cpu.iew.exec_branches 1662 # Number of branches executed
463system.cpu.iew.exec_stores 1282 # Number of stores executed
464system.cpu.iew.exec_rate 0.430063 # Inst execution rate
465system.cpu.iew.wb_sent 16636 # cumulative count of insts sent to commit
466system.cpu.iew.wb_count 16374 # cumulative count of insts written-back
467system.cpu.iew.wb_producers 11006 # num instructions producing a value
468system.cpu.iew.wb_consumers 17135 # num instructions consuming a value
469system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
470system.cpu.iew.wb_rate 0.416038 # insts written-back per cycle
471system.cpu.iew.wb_fanout 0.642311 # average fanout of values written-back
472system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
473system.cpu.commit.commitSquashedInsts 11720 # The number of squashed insts skipped by commit
474system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
475system.cpu.commit.branchMispredicts 588 # The number of times a branch was mispredicted
476system.cpu.commit.committed_per_cycle::samples 19925 # Number of insts commited each cycle
477system.cpu.commit.committed_per_cycle::mean 0.489184 # Number of insts commited each cycle
478system.cpu.commit.committed_per_cycle::stdev 1.394250 # Number of insts commited each cycle
--- 56 unchanged lines hidden (view full) ---
535system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
536system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
537system.cpu.commit.op_class_0::total 9747 # Class of committed instruction
538system.cpu.commit.bw_lim_events 260 # number cycles where commit BW limit reached
539system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
540system.cpu.rob.rob_reads 41132 # The number of ROB reads
541system.cpu.rob.rob_writes 44928 # The number of ROB writes
542system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself
543system.cpu.idleCycles 17464 # Total number of cycles that the CPU has spent unscheduled due to idling
544system.cpu.committedInsts 5380 # Number of Instructions Simulated
545system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
546system.cpu.cpi 7.315428 # CPI: Cycles Per Instruction
547system.cpu.cpi_total 7.315428 # CPI: Total CPI of All Threads
548system.cpu.ipc 0.136697 # IPC: Instructions Per Cycle
549system.cpu.ipc_total 0.136697 # IPC: Total IPC of All Threads
550system.cpu.int_regfile_reads 21340 # number of integer regfile reads
551system.cpu.int_regfile_writes 13120 # number of integer regfile writes
552system.cpu.fp_regfile_reads 4 # number of floating regfile reads
553system.cpu.cc_regfile_reads 8069 # number of cc regfile reads
554system.cpu.cc_regfile_writes 5036 # number of cc regfile writes
555system.cpu.misc_regfile_reads 7491 # number of misc regfile reads
556system.cpu.misc_regfile_writes 1 # number of misc regfile writes
557system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution
558system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
559system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution
560system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution
561system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes)
562system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes)
563system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes)
564system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes)
565system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
566system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes)
567system.cpu.toL2Bus.snoops 0 # Total snoops (count)
568system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
569system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
570system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
571system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
572system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
573system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
574system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
575system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram
576system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
577system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
578system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
579system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
580system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
581system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
582system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
583system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks)
584system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
585system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks)
586system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
587system.cpu.icache.tags.replacements 0 # number of replacements
588system.cpu.icache.tags.tagsinuse 131.539722 # Cycle average of tags in use
589system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks.
590system.cpu.icache.tags.sampled_refs 276 # Sample count of references to valid blocks.
591system.cpu.icache.tags.avg_refs 6.521739 # Average number of references to valid blocks.
592system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
593system.cpu.icache.tags.occ_blocks::cpu.inst 131.539722 # Average occupied blocks per requestor
594system.cpu.icache.tags.occ_percent::cpu.inst 0.064228 # Average percentage of cache occupancy
595system.cpu.icache.tags.occ_percent::total 0.064228 # Average percentage of cache occupancy
596system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id
597system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
598system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id
599system.cpu.icache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id
600system.cpu.icache.tags.tag_accesses 4612 # Number of tag accesses
601system.cpu.icache.tags.data_accesses 4612 # Number of data accesses
602system.cpu.icache.ReadReq_hits::cpu.inst 1800 # number of ReadReq hits
603system.cpu.icache.ReadReq_hits::total 1800 # number of ReadReq hits
604system.cpu.icache.demand_hits::cpu.inst 1800 # number of demand (read+write) hits
605system.cpu.icache.demand_hits::total 1800 # number of demand (read+write) hits
606system.cpu.icache.overall_hits::cpu.inst 1800 # number of overall hits
607system.cpu.icache.overall_hits::total 1800 # number of overall hits
608system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses
609system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses
610system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses
611system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses
612system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses
613system.cpu.icache.overall_misses::total 368 # number of overall misses
614system.cpu.icache.ReadReq_miss_latency::cpu.inst 25557250 # number of ReadReq miss cycles
615system.cpu.icache.ReadReq_miss_latency::total 25557250 # number of ReadReq miss cycles
616system.cpu.icache.demand_miss_latency::cpu.inst 25557250 # number of demand (read+write) miss cycles
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--- 4 unchanged lines hidden (view full) ---
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--- 7 unchanged lines hidden (view full) ---
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--- 6 unchanged lines hidden (view full) ---
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--- 8 unchanged lines hidden (view full) ---
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--- 8 unchanged lines hidden (view full) ---
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899system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles
900system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles
901system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses
902system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses
903system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses
904system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses
905system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses
906system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses
907system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses
908system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses
909system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency
910system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency
911system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency
912system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency
913system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency
914system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency
915system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency
916system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency
917system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
918
919---------- End Simulation Statistics ----------